1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5235EVB_H 15 #define _M5235EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 #define CONFIG_BAUDRATE 115200 25 26 #undef CONFIG_WATCHDOG 27 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 28 29 /* 30 * BOOTP options 31 */ 32 #define CONFIG_BOOTP_BOOTFILESIZE 33 #define CONFIG_BOOTP_BOOTPATH 34 #define CONFIG_BOOTP_GATEWAY 35 #define CONFIG_BOOTP_HOSTNAME 36 37 /* Command line configuration */ 38 #define CONFIG_CMD_CACHE 39 #define CONFIG_CMD_MII 40 #define CONFIG_CMD_PCI 41 #define CONFIG_CMD_REGINFO 42 43 #define CONFIG_MCFFEC 44 #ifdef CONFIG_MCFFEC 45 # define CONFIG_MII 1 46 # define CONFIG_MII_INIT 1 47 # define CONFIG_SYS_DISCOVER_PHY 48 # define CONFIG_SYS_RX_ETH_BUFFER 8 49 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 50 51 # define CONFIG_SYS_FEC0_PINMUX 0 52 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 53 # define MCFFEC_TOUT_LOOP 50000 54 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 55 # ifndef CONFIG_SYS_DISCOVER_PHY 56 # define FECDUPLEX FULL 57 # define FECSPEED _100BASET 58 # else 59 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 60 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 61 # endif 62 # endif /* CONFIG_SYS_DISCOVER_PHY */ 63 #endif 64 65 /* Timer */ 66 #define CONFIG_MCFTMR 67 #undef CONFIG_MCFPIT 68 69 /* I2C */ 70 #define CONFIG_SYS_I2C 71 #define CONFIG_SYS_i2C_FSL 72 #define CONFIG_SYS_FSL_I2C_SPEED 80000 73 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 74 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 75 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 76 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) 77 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) 78 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) 79 80 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 81 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 82 #define CONFIG_BOOTFILE "u-boot.bin" 83 #ifdef CONFIG_MCFFEC 84 # define CONFIG_IPADDR 192.162.1.2 85 # define CONFIG_NETMASK 255.255.255.0 86 # define CONFIG_SERVERIP 192.162.1.1 87 # define CONFIG_GATEWAYIP 192.162.1.1 88 #endif /* FEC_ENET */ 89 90 #define CONFIG_HOSTNAME M5235EVB 91 #define CONFIG_EXTRA_ENV_SETTINGS \ 92 "netdev=eth0\0" \ 93 "loadaddr=10000\0" \ 94 "u-boot=u-boot.bin\0" \ 95 "load=tftp ${loadaddr) ${u-boot}\0" \ 96 "upd=run load; run prog\0" \ 97 "prog=prot off ffe00000 ffe3ffff;" \ 98 "era ffe00000 ffe3ffff;" \ 99 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 100 "save\0" \ 101 "" 102 103 #define CONFIG_PRAM 512 /* 512 KB */ 104 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 105 106 #if defined(CONFIG_KGDB) 107 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 108 #else 109 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 110 #endif 111 112 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 113 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 114 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 115 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) 116 117 #define CONFIG_SYS_CLK 75000000 118 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 119 120 #define CONFIG_SYS_MBAR 0x40000000 121 122 /* 123 * Low Level Configuration Settings 124 * (address mappings, register initial values, etc.) 125 * You should know what you are doing if you make changes here. 126 */ 127 /*----------------------------------------------------------------------- 128 * Definitions for initial stack pointer and data area (in DPRAM) 129 */ 130 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 131 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 132 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 133 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) 134 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 135 136 /*----------------------------------------------------------------------- 137 * Start addresses for the final memory configuration 138 * (Set up by the startup code) 139 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 140 */ 141 #define CONFIG_SYS_SDRAM_BASE 0x00000000 142 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 143 144 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 145 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 146 147 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 148 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 149 150 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 151 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 152 153 /* 154 * For booting Linux, the board info and command line data 155 * have to be in the first 8 MB of memory, since this is 156 * the maximum mapped by the Linux kernel during initialization ?? 157 */ 158 /* Initial Memory map for Linux */ 159 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 160 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 161 162 /*----------------------------------------------------------------------- 163 * FLASH organization 164 */ 165 #define CONFIG_SYS_FLASH_CFI 166 #ifdef CONFIG_SYS_FLASH_CFI 167 # define CONFIG_FLASH_CFI_DRIVER 1 168 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 169 #ifdef NORFLASH_PS32BIT 170 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 171 #else 172 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 173 #endif 174 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 175 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 176 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 177 #endif 178 179 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 180 181 /* Configuration for environment 182 * Environment is embedded in u-boot in the second sector of the flash 183 */ 184 #define CONFIG_ENV_IS_IN_FLASH 1 185 186 #define LDS_BOARD_TEXT \ 187 . = DEFINED(env_offset) ? env_offset : .; \ 188 common/env_embedded.o (.text); 189 190 #ifdef NORFLASH_PS32BIT 191 # define CONFIG_ENV_OFFSET (0x8000) 192 # define CONFIG_ENV_SIZE 0x4000 193 # define CONFIG_ENV_SECT_SIZE 0x4000 194 #else 195 # define CONFIG_ENV_OFFSET (0x4000) 196 # define CONFIG_ENV_SIZE 0x2000 197 # define CONFIG_ENV_SECT_SIZE 0x2000 198 #endif 199 200 /*----------------------------------------------------------------------- 201 * Cache Configuration 202 */ 203 #define CONFIG_SYS_CACHELINE_SIZE 16 204 205 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 206 CONFIG_SYS_INIT_RAM_SIZE - 8) 207 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 208 CONFIG_SYS_INIT_RAM_SIZE - 4) 209 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) 210 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 211 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 212 CF_ACR_EN | CF_ACR_SM_ALL) 213 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 214 CF_CACR_CEIB | CF_CACR_DCM | \ 215 CF_CACR_EUSP) 216 217 /*----------------------------------------------------------------------- 218 * Chipselect bank definitions 219 */ 220 /* 221 * CS0 - NOR Flash 1, 2, 4, or 8MB 222 * CS1 - Available 223 * CS2 - Available 224 * CS3 - Available 225 * CS4 - Available 226 * CS5 - Available 227 * CS6 - Available 228 * CS7 - Available 229 */ 230 #ifdef NORFLASH_PS32BIT 231 # define CONFIG_SYS_CS0_BASE 0xFFC00000 232 # define CONFIG_SYS_CS0_MASK 0x003f0001 233 # define CONFIG_SYS_CS0_CTRL 0x00001D00 234 #else 235 # define CONFIG_SYS_CS0_BASE 0xFFE00000 236 # define CONFIG_SYS_CS0_MASK 0x001f0001 237 # define CONFIG_SYS_CS0_CTRL 0x00001D80 238 #endif 239 240 #endif /* _M5329EVB_H */ 241