1 /* 2 * Configuation settings for the Freescale MCF5329 FireEngine board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M5235EVB_H 15 #define _M5235EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22 #define CONFIG_MCFUART 23 #define CONFIG_SYS_UART_PORT (0) 24 #define CONFIG_BAUDRATE 115200 25 26 #undef CONFIG_WATCHDOG 27 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 28 29 /* 30 * BOOTP options 31 */ 32 #define CONFIG_BOOTP_BOOTFILESIZE 33 #define CONFIG_BOOTP_BOOTPATH 34 #define CONFIG_BOOTP_GATEWAY 35 #define CONFIG_BOOTP_HOSTNAME 36 37 /* Command line configuration */ 38 #define CONFIG_CMD_CACHE 39 #define CONFIG_CMD_MII 40 #define CONFIG_CMD_PCI 41 #define CONFIG_CMD_REGINFO 42 43 44 #define CONFIG_MCFFEC 45 #ifdef CONFIG_MCFFEC 46 # define CONFIG_MII 1 47 # define CONFIG_MII_INIT 1 48 # define CONFIG_SYS_DISCOVER_PHY 49 # define CONFIG_SYS_RX_ETH_BUFFER 8 50 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 51 52 # define CONFIG_SYS_FEC0_PINMUX 0 53 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 54 # define MCFFEC_TOUT_LOOP 50000 55 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 56 # ifndef CONFIG_SYS_DISCOVER_PHY 57 # define FECDUPLEX FULL 58 # define FECSPEED _100BASET 59 # else 60 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 61 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 62 # endif 63 # endif /* CONFIG_SYS_DISCOVER_PHY */ 64 #endif 65 66 /* Timer */ 67 #define CONFIG_MCFTMR 68 #undef CONFIG_MCFPIT 69 70 /* I2C */ 71 #define CONFIG_SYS_I2C 72 #define CONFIG_SYS_i2C_FSL 73 #define CONFIG_SYS_FSL_I2C_SPEED 80000 74 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 75 #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 76 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 77 #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) 78 #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) 79 #define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) 80 81 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ 82 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 83 #define CONFIG_BOOTFILE "u-boot.bin" 84 #ifdef CONFIG_MCFFEC 85 # define CONFIG_IPADDR 192.162.1.2 86 # define CONFIG_NETMASK 255.255.255.0 87 # define CONFIG_SERVERIP 192.162.1.1 88 # define CONFIG_GATEWAYIP 192.162.1.1 89 #endif /* FEC_ENET */ 90 91 #define CONFIG_HOSTNAME M5235EVB 92 #define CONFIG_EXTRA_ENV_SETTINGS \ 93 "netdev=eth0\0" \ 94 "loadaddr=10000\0" \ 95 "u-boot=u-boot.bin\0" \ 96 "load=tftp ${loadaddr) ${u-boot}\0" \ 97 "upd=run load; run prog\0" \ 98 "prog=prot off ffe00000 ffe3ffff;" \ 99 "era ffe00000 ffe3ffff;" \ 100 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 101 "save\0" \ 102 "" 103 104 #define CONFIG_PRAM 512 /* 512 KB */ 105 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 106 107 #if defined(CONFIG_KGDB) 108 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 109 #else 110 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 111 #endif 112 113 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 114 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 115 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 116 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) 117 118 #define CONFIG_SYS_CLK 75000000 119 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 120 121 #define CONFIG_SYS_MBAR 0x40000000 122 123 /* 124 * Low Level Configuration Settings 125 * (address mappings, register initial values, etc.) 126 * You should know what you are doing if you make changes here. 127 */ 128 /*----------------------------------------------------------------------- 129 * Definitions for initial stack pointer and data area (in DPRAM) 130 */ 131 #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 132 #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ 133 #define CONFIG_SYS_INIT_RAM_CTRL 0x21 134 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) 135 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 136 137 /*----------------------------------------------------------------------- 138 * Start addresses for the final memory configuration 139 * (Set up by the startup code) 140 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 141 */ 142 #define CONFIG_SYS_SDRAM_BASE 0x00000000 143 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ 144 145 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 146 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 147 148 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 149 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 150 151 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 152 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 153 154 /* 155 * For booting Linux, the board info and command line data 156 * have to be in the first 8 MB of memory, since this is 157 * the maximum mapped by the Linux kernel during initialization ?? 158 */ 159 /* Initial Memory map for Linux */ 160 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 161 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 162 163 /*----------------------------------------------------------------------- 164 * FLASH organization 165 */ 166 #define CONFIG_SYS_FLASH_CFI 167 #ifdef CONFIG_SYS_FLASH_CFI 168 # define CONFIG_FLASH_CFI_DRIVER 1 169 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 170 #ifdef NORFLASH_PS32BIT 171 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT 172 #else 173 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 174 #endif 175 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 176 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 177 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 178 #endif 179 180 #define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) 181 182 /* Configuration for environment 183 * Environment is embedded in u-boot in the second sector of the flash 184 */ 185 #define CONFIG_ENV_IS_IN_FLASH 1 186 187 #define LDS_BOARD_TEXT \ 188 . = DEFINED(env_offset) ? env_offset : .; \ 189 common/env_embedded.o (.text); 190 191 #ifdef NORFLASH_PS32BIT 192 # define CONFIG_ENV_OFFSET (0x8000) 193 # define CONFIG_ENV_SIZE 0x4000 194 # define CONFIG_ENV_SECT_SIZE 0x4000 195 #else 196 # define CONFIG_ENV_OFFSET (0x4000) 197 # define CONFIG_ENV_SIZE 0x2000 198 # define CONFIG_ENV_SECT_SIZE 0x2000 199 #endif 200 201 /*----------------------------------------------------------------------- 202 * Cache Configuration 203 */ 204 #define CONFIG_SYS_CACHELINE_SIZE 16 205 206 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 207 CONFIG_SYS_INIT_RAM_SIZE - 8) 208 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 209 CONFIG_SYS_INIT_RAM_SIZE - 4) 210 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) 211 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 212 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 213 CF_ACR_EN | CF_ACR_SM_ALL) 214 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ 215 CF_CACR_CEIB | CF_CACR_DCM | \ 216 CF_CACR_EUSP) 217 218 /*----------------------------------------------------------------------- 219 * Chipselect bank definitions 220 */ 221 /* 222 * CS0 - NOR Flash 1, 2, 4, or 8MB 223 * CS1 - Available 224 * CS2 - Available 225 * CS3 - Available 226 * CS4 - Available 227 * CS5 - Available 228 * CS6 - Available 229 * CS7 - Available 230 */ 231 #ifdef NORFLASH_PS32BIT 232 # define CONFIG_SYS_CS0_BASE 0xFFC00000 233 # define CONFIG_SYS_CS0_MASK 0x003f0001 234 # define CONFIG_SYS_CS0_CTRL 0x00001D00 235 #else 236 # define CONFIG_SYS_CS0_BASE 0xFFE00000 237 # define CONFIG_SYS_CS0_MASK 0x001f0001 238 # define CONFIG_SYS_CS0_CTRL 0x00001D80 239 #endif 240 241 #endif /* _M5329EVB_H */ 242