1 /* 2 * Configuation settings for the Freescale MCF52277 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /* 11 * board/config.h - configuration options, board specific 12 */ 13 14 #ifndef _M52277EVB_H 15 #define _M52277EVB_H 16 17 /* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 #define CONFIG_M52277EVB /* M52277EVB board */ 22 23 #define CONFIG_MCFUART 24 #define CONFIG_SYS_UART_PORT (0) 25 #define CONFIG_BAUDRATE 115200 26 27 #undef CONFIG_WATCHDOG 28 29 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 30 31 /* 32 * BOOTP options 33 */ 34 #define CONFIG_BOOTP_BOOTFILESIZE 35 #define CONFIG_BOOTP_BOOTPATH 36 #define CONFIG_BOOTP_GATEWAY 37 #define CONFIG_BOOTP_HOSTNAME 38 39 /* Command line configuration */ 40 #define CONFIG_CMD_CACHE 41 #define CONFIG_CMD_DATE 42 #define CONFIG_CMD_JFFS2 43 #define CONFIG_CMD_REGINFO 44 #undef CONFIG_CMD_BMP 45 46 #define CONFIG_HOSTNAME M52277EVB 47 #define CONFIG_SYS_UBOOT_END 0x3FFFF 48 #define CONFIG_SYS_LOAD_ADDR2 0x40010007 49 #ifdef CONFIG_SYS_STMICRO_BOOT 50 /* ST Micro serial flash */ 51 #define CONFIG_EXTRA_ENV_SETTINGS \ 52 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 53 "loadaddr=0x40010000\0" \ 54 "uboot=u-boot.bin\0" \ 55 "load=loadb ${loadaddr} ${baudrate};" \ 56 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 57 "upd=run load; run prog\0" \ 58 "prog=sf probe 0:2 10000 1;" \ 59 "sf erase 0 30000;" \ 60 "sf write ${loadaddr} 0 30000;" \ 61 "save\0" \ 62 "" 63 #endif 64 #ifdef CONFIG_SYS_SPANSION_BOOT 65 #define CONFIG_EXTRA_ENV_SETTINGS \ 66 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 67 "loadaddr=0x40010000\0" \ 68 "uboot=u-boot.bin\0" \ 69 "load=loadb ${loadaddr} ${baudrate}\0" \ 70 "upd=run load; run prog\0" \ 71 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 72 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 73 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 74 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 75 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 76 " ${filesize}; save\0" \ 77 "updsbf=run loadsbf; run progsbf\0" \ 78 "loadsbf=loadb ${loadaddr} ${baudrate};" \ 79 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 80 "progsbf=sf probe 0:2 10000 1;" \ 81 "sf erase 0 30000;" \ 82 "sf write ${loadaddr} 0 30000;" \ 83 "" 84 #endif 85 86 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 87 /* LCD */ 88 #ifdef CONFIG_CMD_BMP 89 #define CONFIG_LCD 90 #define CONFIG_SPLASH_SCREEN 91 #define CONFIG_LCD_LOGO 92 #define CONFIG_SHARP_LQ035Q7DH06 93 #endif 94 95 /* USB */ 96 #ifdef CONFIG_CMD_USB 97 #define CONFIG_USB_EHCI 98 #define CONFIG_USB_STORAGE 99 #define CONFIG_DOS_PARTITION 100 #define CONFIG_MAC_PARTITION 101 #define CONFIG_ISO_PARTITION 102 #define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 103 #define CONFIG_SYS_USB_EHCI_CPU_INIT 104 #endif 105 106 /* Realtime clock */ 107 #define CONFIG_MCFRTC 108 #undef RTC_DEBUG 109 #define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 110 111 /* Timer */ 112 #define CONFIG_MCFTMR 113 #undef CONFIG_MCFPIT 114 115 /* I2c */ 116 #define CONFIG_SYS_I2C 117 #define CONFIG_SYS_I2C_FSL 118 #define CONFIG_SYS_FSL_I2C_SPEED 80000 119 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 120 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 121 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 122 123 /* DSPI and Serial Flash */ 124 #define CONFIG_CF_SPI 125 #define CONFIG_CF_DSPI 126 #define CONFIG_HARD_SPI 127 #define CONFIG_SYS_SBFHDR_SIZE 0x7 128 #ifdef CONFIG_CMD_SPI 129 # define CONFIG_SYS_DSPI_CS2 130 131 # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 132 DSPI_CTAR_PCSSCK_1CLK | \ 133 DSPI_CTAR_PASC(0) | \ 134 DSPI_CTAR_PDT(0) | \ 135 DSPI_CTAR_CSSCK(0) | \ 136 DSPI_CTAR_ASC(0) | \ 137 DSPI_CTAR_DT(1)) 138 #endif 139 140 /* Input, PCI, Flexbus, and VCO */ 141 #define CONFIG_EXTRA_CLOCK 142 143 #define CONFIG_SYS_INPUT_CLKSRC 16000000 144 145 #define CONFIG_PRAM 2048 /* 2048 KB */ 146 147 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 148 149 #if defined(CONFIG_CMD_KGDB) 150 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 151 #else 152 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 153 #endif 154 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 155 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 156 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 157 158 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 159 160 #define CONFIG_SYS_MBAR 0xFC000000 161 162 /* 163 * Low Level Configuration Settings 164 * (address mappings, register initial values, etc.) 165 * You should know what you are doing if you make changes here. 166 */ 167 168 /* 169 * Definitions for initial stack pointer and data area (in DPRAM) 170 */ 171 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 172 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 173 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 174 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 175 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) 176 #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 177 178 /* 179 * Start addresses for the final memory configuration 180 * (Set up by the startup code) 181 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 182 */ 183 #define CONFIG_SYS_SDRAM_BASE 0x40000000 184 #define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 185 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 186 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 187 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 188 #define CONFIG_SYS_SDRAM_EMOD 0x81810000 189 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 190 #define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 191 192 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 193 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 194 195 #ifdef CONFIG_CF_SBF 196 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 197 #else 198 # define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 199 #endif 200 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 201 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 202 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 203 204 /* Initial Memory map for Linux */ 205 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 206 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 207 208 /* 209 * Configuration for environment 210 * Environment is not embedded in u-boot. First time runing may have env 211 * crc error warning if there is no correct environment on the flash. 212 */ 213 #ifdef CONFIG_CF_SBF 214 # define CONFIG_ENV_IS_IN_SPI_FLASH 215 # define CONFIG_ENV_SPI_CS 2 216 #else 217 # define CONFIG_ENV_IS_IN_FLASH 1 218 #endif 219 #define CONFIG_ENV_OVERWRITE 1 220 221 /*----------------------------------------------------------------------- 222 * FLASH organization 223 */ 224 #ifdef CONFIG_SYS_STMICRO_BOOT 225 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 226 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 227 # define CONFIG_ENV_OFFSET 0x30000 228 # define CONFIG_ENV_SIZE 0x1000 229 # define CONFIG_ENV_SECT_SIZE 0x10000 230 #endif 231 #ifdef CONFIG_SYS_SPANSION_BOOT 232 # define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 233 # define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 234 # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 235 # define CONFIG_ENV_SIZE 0x1000 236 # define CONFIG_ENV_SECT_SIZE 0x8000 237 #endif 238 239 #define CONFIG_SYS_FLASH_CFI 240 #ifdef CONFIG_SYS_FLASH_CFI 241 # define CONFIG_FLASH_CFI_DRIVER 1 242 # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 243 # define CONFIG_FLASH_SPANSION_S29WS_N 1 244 # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 245 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 246 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 247 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 248 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 249 # define CONFIG_SYS_FLASH_CHECKSUM 250 # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 251 #endif 252 253 #define LDS_BOARD_TEXT \ 254 arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ 255 arch/m68k/lib/built-in.o (.text*) 256 257 /* 258 * This is setting for JFFS2 support in u-boot. 259 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 260 */ 261 #ifdef CONFIG_CMD_JFFS2 262 # define CONFIG_JFFS2_DEV "nor0" 263 # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) 264 # define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) 265 #endif 266 267 /*----------------------------------------------------------------------- 268 * Cache Configuration 269 */ 270 #define CONFIG_SYS_CACHELINE_SIZE 16 271 272 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 273 CONFIG_SYS_INIT_RAM_SIZE - 8) 274 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 275 CONFIG_SYS_INIT_RAM_SIZE - 4) 276 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 277 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 278 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 279 CF_ACR_EN | CF_ACR_SM_ALL) 280 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 281 CF_CACR_DISD | CF_CACR_INVI | \ 282 CF_CACR_CEIB | CF_CACR_DCM | \ 283 CF_CACR_EUSP) 284 285 /*----------------------------------------------------------------------- 286 * Memory bank definitions 287 */ 288 /* 289 * CS0 - NOR Flash 290 * CS1 - Available 291 * CS2 - Available 292 * CS3 - Available 293 * CS4 - Available 294 * CS5 - Available 295 */ 296 297 #ifdef CONFIG_CF_SBF 298 #define CONFIG_SYS_CS0_BASE 0x04000000 299 #define CONFIG_SYS_CS0_MASK 0x00FF0001 300 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 301 #else 302 #define CONFIG_SYS_CS0_BASE 0x00000000 303 #define CONFIG_SYS_CS0_MASK 0x00FF0001 304 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 305 #endif 306 307 #endif /* _M52277EVB_H */ 308