1 /* 2 * Configuation settings for the Freescale MCF5208EVBe. 3 * 4 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef _M5208EVBE_H 11 #define _M5208EVBE_H 12 13 /* 14 * High Level Configuration Options 15 * (easy to change) 16 */ 17 #define CONFIG_MCFUART 18 #define CONFIG_SYS_UART_PORT (0) 19 #define CONFIG_BAUDRATE 115200 20 21 #undef CONFIG_WATCHDOG 22 #define CONFIG_WATCHDOG_TIMEOUT 5000 23 24 /* Command line configuration */ 25 #define CONFIG_CMD_CACHE 26 #define CONFIG_CMD_MII 27 #define CONFIG_CMD_REGINFO 28 29 #define CONFIG_MCFFEC 30 #ifdef CONFIG_MCFFEC 31 # define CONFIG_MII 1 32 # define CONFIG_MII_INIT 1 33 # define CONFIG_SYS_DISCOVER_PHY 34 # define CONFIG_SYS_RX_ETH_BUFFER 8 35 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 36 # define CONFIG_HAS_ETH1 37 38 # define CONFIG_SYS_FEC0_PINMUX 0 39 # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE 40 # define MCFFEC_TOUT_LOOP 50000 41 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 42 # ifndef CONFIG_SYS_DISCOVER_PHY 43 # define FECDUPLEX FULL 44 # define FECSPEED _100BASET 45 # else 46 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 47 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 48 # endif 49 # endif /* CONFIG_SYS_DISCOVER_PHY */ 50 #endif 51 52 /* Timer */ 53 #define CONFIG_MCFTMR 54 #undef CONFIG_MCFPIT 55 56 /* I2C */ 57 #define CONFIG_SYS_I2C 58 #define CONFIG_SYS_I2C_FSL 59 #define CONFIG_SYS_FSL_I2C_SPEED 80000 60 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 61 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 62 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 63 64 #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ 65 #define CONFIG_UDP_CHECKSUM 66 67 #ifdef CONFIG_MCFFEC 68 # define CONFIG_IPADDR 192.162.1.2 69 # define CONFIG_NETMASK 255.255.255.0 70 # define CONFIG_SERVERIP 192.162.1.1 71 # define CONFIG_GATEWAYIP 192.162.1.1 72 #endif /* CONFIG_MCFFEC */ 73 74 #define CONFIG_HOSTNAME M5208EVBe 75 #define CONFIG_EXTRA_ENV_SETTINGS \ 76 "netdev=eth0\0" \ 77 "loadaddr=40010000\0" \ 78 "u-boot=u-boot.bin\0" \ 79 "load=tftp ${loadaddr) ${u-boot}\0" \ 80 "upd=run load; run prog\0" \ 81 "prog=prot off 0 3ffff;" \ 82 "era 0 3ffff;" \ 83 "cp.b ${loadaddr} 0 ${filesize};" \ 84 "save\0" \ 85 "" 86 87 #define CONFIG_PRAM 512 /* 512 KB */ 88 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 89 90 #ifdef CONFIG_CMD_KGDB 91 # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 92 #else 93 # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 94 #endif 95 96 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 97 #define CONFIG_SYS_MAXARGS 16 /* max number of cmd args */ 98 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buf Sz */ 99 #define CONFIG_SYS_LOAD_ADDR 0x40010000 100 101 #define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ 102 #define CONFIG_SYS_PLL_ODR 0x36 103 #define CONFIG_SYS_PLL_FDR 0x7D 104 105 #define CONFIG_SYS_MBAR 0xFC000000 106 107 /* 108 * Low Level Configuration Settings 109 * (address mappings, register initial values, etc.) 110 * You should know what you are doing if you make changes here. 111 */ 112 /* Definitions for initial stack pointer and data area (in DPRAM) */ 113 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 114 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ 115 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 116 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 117 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 118 119 /* 120 * Start addresses for the final memory configuration 121 * (Set up by the startup code) 122 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 123 */ 124 #define CONFIG_SYS_SDRAM_BASE 0x40000000 125 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 126 #define CONFIG_SYS_SDRAM_CFG1 0x43711630 127 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 128 #define CONFIG_SYS_SDRAM_CTRL 0xE1002000 129 #define CONFIG_SYS_SDRAM_EMOD 0x80010000 130 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000 131 132 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 133 #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 134 135 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 136 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 137 138 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 139 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 140 141 /* 142 * For booting Linux, the board info and command line data 143 * have to be in the first 8 MB of memory, since this is 144 * the maximum mapped by the Linux kernel during initialization ?? 145 */ 146 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 147 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 148 149 /* FLASH organization */ 150 #define CONFIG_SYS_FLASH_CFI 151 #ifdef CONFIG_SYS_FLASH_CFI 152 # define CONFIG_FLASH_CFI_DRIVER 1 153 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 154 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 155 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 156 # define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ 157 # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 158 #endif 159 160 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 161 162 /* 163 * Configuration for environment 164 * Environment is embedded in u-boot in the second sector of the flash 165 */ 166 #define CONFIG_ENV_OFFSET 0x2000 167 #define CONFIG_ENV_SIZE 0x1000 168 #define CONFIG_ENV_SECT_SIZE 0x2000 169 #define CONFIG_ENV_IS_IN_FLASH 1 170 171 #define LDS_BOARD_TEXT \ 172 . = DEFINED(env_offset) ? env_offset : .; \ 173 common/env_embedded.o (.text*); 174 175 /* Cache Configuration */ 176 #define CONFIG_SYS_CACHELINE_SIZE 16 177 178 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 179 CONFIG_SYS_INIT_RAM_SIZE - 8) 180 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 181 CONFIG_SYS_INIT_RAM_SIZE - 4) 182 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 183 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 184 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 185 CF_ACR_EN | CF_ACR_SM_ALL) 186 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 187 CF_CACR_DISD | CF_CACR_INVI | \ 188 CF_CACR_CEIB | CF_CACR_DCM | \ 189 CF_CACR_EUSP) 190 191 /* Chipselect bank definitions */ 192 /* 193 * CS0 - NOR Flash 194 * CS1 - Available 195 * CS2 - Available 196 * CS3 - Available 197 * CS4 - Available 198 * CS5 - Available 199 */ 200 #define CONFIG_SYS_CS0_BASE 0 201 #define CONFIG_SYS_CS0_MASK 0x007F0001 202 #define CONFIG_SYS_CS0_CTRL 0x00001FA0 203 204 #endif /* _M5208EVBE_H */ 205