1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * C29XPCIE board configuration file 25 */ 26 27 #ifndef __CONFIG_H 28 #define __CONFIG_H 29 30 #define CONFIG_PHYS_64BIT 31 32 #ifdef CONFIG_C29XPCIE 33 #define CONFIG_PPC_C29X 34 #endif 35 36 #ifdef CONFIG_SPIFLASH 37 #define CONFIG_RAMBOOT_SPIFLASH 38 #define CONFIG_SYS_TEXT_BASE 0x11000000 39 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 40 #endif 41 42 #ifndef CONFIG_SYS_TEXT_BASE 43 #define CONFIG_SYS_TEXT_BASE 0xeff80000 44 #endif 45 46 #ifndef CONFIG_RESET_VECTOR_ADDRESS 47 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 48 #endif 49 50 #ifndef CONFIG_SYS_MONITOR_BASE 51 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 52 #endif 53 54 /* High Level Configuration Options */ 55 #define CONFIG_BOOKE /* BOOKE */ 56 #define CONFIG_E500 /* BOOKE e500 family */ 57 #define CONFIG_MPC85xx 58 #define CONFIG_FSL_IFC /* Enable IFC Support */ 59 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 60 61 #define CONFIG_PCI /* Enable PCI/PCIE */ 62 #ifdef CONFIG_PCI 63 #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ 64 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 65 #define CONFIG_PCI_INDIRECT_BRIDGE 66 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 67 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 68 69 #define CONFIG_CMD_NET 70 #define CONFIG_CMD_PCI 71 72 #define CONFIG_E1000 73 74 /* 75 * PCI Windows 76 * Memory space is mapped 1-1, but I/O space must start from 0. 77 */ 78 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 79 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 80 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 81 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 82 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 83 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 84 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 85 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 86 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 87 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 88 89 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 90 91 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 92 #define CONFIG_DOS_PARTITION 93 #endif 94 95 #define CONFIG_FSL_LAW /* Use common FSL init code */ 96 #define CONFIG_TSEC_ENET 97 #define CONFIG_ENV_OVERWRITE 98 99 #define CONFIG_DDR_CLK_FREQ 100000000 100 #define CONFIG_SYS_CLK_FREQ 66666666 101 102 #define CONFIG_HWCONFIG 103 104 /* 105 * These can be toggled for performance analysis, otherwise use default. 106 */ 107 #define CONFIG_L2_CACHE /* toggle L2 cache */ 108 #define CONFIG_BTB /* toggle branch predition */ 109 110 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 111 112 #define CONFIG_ENABLE_36BIT_PHYS 113 114 #define CONFIG_ADDR_MAP 1 115 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 116 117 #define CONFIG_SYS_MEMTEST_START 0x00200000 118 #define CONFIG_SYS_MEMTEST_END 0x00400000 119 #define CONFIG_PANIC_HANG 120 121 /* DDR Setup */ 122 #define CONFIG_FSL_DDR3 123 #define CONFIG_DDR_SPD 124 #define CONFIG_SYS_SPD_BUS_NUM 0 125 #define SPD_EEPROM_ADDRESS 0x50 126 #define CONFIG_SYS_DDR_RAW_TIMING 127 128 /* DDR ECC Setup*/ 129 #define CONFIG_DDR_ECC 130 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 131 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 132 133 #define CONFIG_SYS_SDRAM_SIZE 512 134 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 135 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 136 137 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 138 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 139 140 #define CONFIG_SYS_CCSRBAR 0xffe00000 141 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 142 143 /* Platform SRAM setting */ 144 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 145 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 146 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 147 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 148 149 /* 150 * IFC Definitions 151 */ 152 /* NOR Flash on IFC */ 153 #define CONFIG_SYS_FLASH_BASE 0xec000000 154 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 155 156 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 157 158 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 159 #define CONFIG_SYS_MAX_FLASH_BANKS 1 160 161 #define CONFIG_SYS_FLASH_QUIET_TEST 162 #define CONFIG_FLASH_SHOW_PROGRESS 45 163 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 164 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 165 166 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 167 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 168 CSPR_PORT_SIZE_16 | \ 169 CSPR_MSEL_NOR | \ 170 CSPR_V) 171 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 172 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 173 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 174 FTIM0_NOR_TEADC(0x5) | \ 175 FTIM0_NOR_TEAHC(0x5)) 176 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1e) | \ 177 FTIM1_NOR_TRAD_NOR(0x0f) | \ 178 FTIM1_NOR_TSEQRAD_NOR(0x0f)) 179 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 180 FTIM2_NOR_TCH(0x4) | \ 181 FTIM2_NOR_TWP(0x1c)) 182 #define CONFIG_SYS_NOR_FTIM3 0x0 183 184 /* CFI for NOR Flash */ 185 #define CONFIG_FLASH_CFI_DRIVER 186 #define CONFIG_SYS_FLASH_CFI 187 #define CONFIG_SYS_FLASH_EMPTY_INFO 188 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 189 190 /* NAND Flash on IFC */ 191 #define CONFIG_NAND_FSL_IFC 192 #define CONFIG_SYS_NAND_BASE 0xff800000 193 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 194 195 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 196 197 #define CONFIG_SYS_MAX_NAND_DEVICE 1 198 #define CONFIG_MTD_NAND_VERIFY_WRITE 199 #define CONFIG_CMD_NAND 200 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 201 202 /* 8Bit NAND Flash - K9F1G08U0B */ 203 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 204 | CSPR_PORT_SIZE_8 \ 205 | CSPR_MSEL_NAND \ 206 | CSPR_V) 207 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 208 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 209 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 210 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 211 | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ 212 | CSOR_NAND_PGS_2K /* Page Size = 2k */ \ 213 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ 214 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ 215 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 216 FTIM0_NAND_TWP(0x0c) | \ 217 FTIM0_NAND_TWCHT(0x08) | \ 218 FTIM0_NAND_TWH(0x06)) 219 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 220 FTIM1_NAND_TWBE(0x1d) | \ 221 FTIM1_NAND_TRR(0x08) | \ 222 FTIM1_NAND_TRP(0x0c)) 223 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 224 FTIM2_NAND_TREH(0x0a) | \ 225 FTIM2_NAND_TWHRE(0x18)) 226 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 227 228 #define CONFIG_SYS_NAND_DDR_LAW 11 229 230 /* Set up IFC registers for boot location NOR/NAND */ 231 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 232 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 233 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 234 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 235 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 236 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 237 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 238 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 239 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 240 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 241 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 242 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 243 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 244 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 245 246 /* CPLD on IFC, selected by CS2 */ 247 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 248 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 249 | CONFIG_SYS_CPLD_BASE) 250 251 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 252 | CSPR_PORT_SIZE_8 \ 253 | CSPR_MSEL_GPCM \ 254 | CSPR_V) 255 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 256 #define CONFIG_SYS_CSOR2 0x0 257 /* CPLD Timing parameters for IFC CS2 */ 258 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 259 FTIM0_GPCM_TEADC(0x0e) | \ 260 FTIM0_GPCM_TEAHC(0x0e)) 261 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 262 FTIM1_GPCM_TRAD(0x1f)) 263 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 264 FTIM2_GPCM_TCH(0x0) | \ 265 FTIM2_GPCM_TWP(0x1f)) 266 #define CONFIG_SYS_CS2_FTIM3 0x0 267 268 #if defined(CONFIG_RAMBOOT_SPIFLASH) 269 #define CONFIG_SYS_RAMBOOT 270 #define CONFIG_SYS_EXTRA_ENV_RELOC 271 #endif 272 273 #define CONFIG_BOARD_EARLY_INIT_R 274 275 #define CONFIG_SYS_INIT_RAM_LOCK 276 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 277 #define CONFIG_SYS_INIT_RAM_END 0x00004000 278 279 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ 280 - GENERATED_GBL_DATA_SIZE) 281 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 282 283 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 284 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) 285 286 /* Serial Port */ 287 #define CONFIG_CONS_INDEX 1 288 #define CONFIG_SYS_NS16550 289 #define CONFIG_SYS_NS16550_SERIAL 290 #define CONFIG_SYS_NS16550_REG_SIZE 1 291 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 292 293 #define CONFIG_SERIAL_MULTI /* Enable both serial ports */ 294 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 295 296 #define CONFIG_SYS_BAUDRATE_TABLE \ 297 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 298 299 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 300 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 301 302 /* Use the HUSH parser */ 303 #define CONFIG_SYS_HUSH_PARSER 304 305 /* 306 * Pass open firmware flat tree 307 */ 308 #define CONFIG_OF_LIBFDT 309 #define CONFIG_OF_BOARD_SETUP 310 #define CONFIG_OF_STDOUT_VIA_ALIAS 311 312 /* new uImage format support */ 313 #define CONFIG_FIT 314 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 315 316 #define CONFIG_SYS_I2C 317 #define CONFIG_SYS_I2C_FSL 318 #define CONFIG_SYS_FSL_I2C_SPEED 400000 319 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 320 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 321 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 322 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 323 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 324 325 /* I2C EEPROM */ 326 /* enable read and write access to EEPROM */ 327 #define CONFIG_CMD_EEPROM 328 #define CONFIG_SYS_I2C_MULTI_EEPROMS 329 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 330 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 331 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 332 333 #define CONFIG_CMD_I2C 334 335 /* eSPI - Enhanced SPI */ 336 #define CONFIG_FSL_ESPI 337 #define CONFIG_SPI_FLASH 338 #define CONFIG_SPI_FLASH_SPANSION 339 #define CONFIG_SPI_FLASH_EON 340 #define CONFIG_CMD_SF 341 #define CONFIG_SF_DEFAULT_SPEED 10000000 342 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 343 344 #ifdef CONFIG_TSEC_ENET 345 #define CONFIG_NET_MULTI 346 #define CONFIG_MII /* MII PHY management */ 347 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 348 #define CONFIG_TSEC1 1 349 #define CONFIG_TSEC1_NAME "eTSEC1" 350 #define CONFIG_TSEC2 1 351 #define CONFIG_TSEC2_NAME "eTSEC2" 352 353 /* Default mode is RGMII mode */ 354 #define TSEC1_PHY_ADDR 0 355 #define TSEC2_PHY_ADDR 2 356 357 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 358 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 359 360 #define CONFIG_ETHPRIME "eTSEC1" 361 362 #define CONFIG_PHY_GIGE 363 #endif /* CONFIG_TSEC_ENET */ 364 365 /* 366 * Environment 367 */ 368 #if defined(CONFIG_SYS_RAMBOOT) 369 #if defined(CONFIG_RAMBOOT_SPIFLASH) 370 #define CONFIG_ENV_IS_IN_SPI_FLASH 371 #define CONFIG_ENV_SPI_BUS 0 372 #define CONFIG_ENV_SPI_CS 0 373 #define CONFIG_ENV_SPI_MAX_HZ 10000000 374 #define CONFIG_ENV_SPI_MODE 0 375 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 376 #define CONFIG_ENV_SECT_SIZE 0x10000 377 #define CONFIG_ENV_SIZE 0x2000 378 #endif 379 #else 380 #define CONFIG_ENV_IS_IN_FLASH 381 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 382 #define CONFIG_ENV_ADDR 0xfff80000 383 #else 384 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 385 #endif 386 #define CONFIG_ENV_SIZE 0x2000 387 #define CONFIG_ENV_SECT_SIZE 0x20000 388 #endif 389 390 #define CONFIG_LOADS_ECHO 391 #define CONFIG_SYS_LOADS_BAUD_CHANGE 392 393 /* 394 * Command line configuration. 395 */ 396 #include <config_cmd_default.h> 397 398 #define CONFIG_CMD_ERRATA 399 #define CONFIG_CMD_ELF 400 #define CONFIG_CMD_IRQ 401 #define CONFIG_CMD_MII 402 #define CONFIG_CMD_PING 403 #define CONFIG_CMD_SETEXPR 404 #define CONFIG_CMD_REGINFO 405 406 /* 407 * Miscellaneous configurable options 408 */ 409 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 410 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 411 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 412 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 413 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 414 415 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 416 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 417 /* Print Buffer Size */ 418 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 419 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 420 #define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */ 421 422 /* 423 * For booting Linux, the board info and command line data 424 * have to be in the first 64 MB of memory, since this is 425 * the maximum mapped by the Linux kernel during initialization. 426 */ 427 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 428 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 429 430 /* 431 * Environment Configuration 432 */ 433 434 #ifdef CONFIG_TSEC_ENET 435 #define CONFIG_HAS_ETH0 436 #define CONFIG_HAS_ETH1 437 #endif 438 439 #define CONFIG_ROOTPATH "/opt/nfsroot" 440 #define CONFIG_BOOTFILE "uImage" 441 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 442 443 /* default location for tftp and bootm */ 444 #define CONFIG_LOADADDR 1000000 445 446 #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ 447 448 #define CONFIG_BAUDRATE 115200 449 450 #define CONFIG_EXTRA_ENV_SETTINGS \ 451 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 452 "netdev=eth0\0" \ 453 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 454 "loadaddr=1000000\0" \ 455 "consoledev=ttyS0\0" \ 456 "ramdiskaddr=2000000\0" \ 457 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 458 "fdtaddr=c00000\0" \ 459 "fdtfile=name/of/device-tree.dtb\0" \ 460 "othbootargs=ramdisk_size=600000\0" \ 461 462 #define CONFIG_RAMBOOTCOMMAND \ 463 "setenv bootargs root=/dev/ram rw " \ 464 "console=$consoledev,$baudrate $othbootargs; " \ 465 "tftp $ramdiskaddr $ramdiskfile;" \ 466 "tftp $loadaddr $bootfile;" \ 467 "tftp $fdtaddr $fdtfile;" \ 468 "bootm $loadaddr $ramdiskaddr $fdtaddr" 469 470 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 471 472 #endif /* __CONFIG_H */ 473