1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * C29XPCIE board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_DISPLAY_BOARDINFO 15 16 #ifdef CONFIG_C29XPCIE 17 #define CONFIG_PPC_C29X 18 #endif 19 20 #ifdef CONFIG_SPIFLASH 21 #define CONFIG_RAMBOOT_SPIFLASH 22 #define CONFIG_SYS_TEXT_BASE 0x11000000 23 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 24 #endif 25 26 #ifdef CONFIG_NAND 27 #ifdef CONFIG_TPL_BUILD 28 #define CONFIG_SPL_NAND_BOOT 29 #define CONFIG_SPL_FLUSH_IMAGE 30 #define CONFIG_SPL_NAND_INIT 31 #define CONFIG_TPL_SERIAL_SUPPORT 32 #define CONFIG_TPL_DRIVERS_MISC_SUPPORT 33 #define CONFIG_TPL_NAND_SUPPORT 34 #define CONFIG_SPL_COMMON_INIT_DDR 35 #define CONFIG_SPL_MAX_SIZE (128 << 10) 36 #define CONFIG_SPL_TEXT_BASE 0xf8f81000 37 #define CONFIG_SYS_MPC85XX_NO_RESETVEC 38 #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) 39 #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) 40 #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) 41 #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) 42 #elif defined(CONFIG_SPL_BUILD) 43 #define CONFIG_SPL_INIT_MINIMAL 44 #define CONFIG_SPL_SERIAL_SUPPORT 45 #define CONFIG_SPL_NAND_SUPPORT 46 #define CONFIG_SPL_NAND_MINIMAL 47 #define CONFIG_SPL_FLUSH_IMAGE 48 #define CONFIG_SPL_TEXT_BASE 0xff800000 49 #define CONFIG_SPL_MAX_SIZE 8192 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) 51 #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 52 #define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) 54 #endif 55 #define CONFIG_SPL_PAD_TO 0x20000 56 #define CONFIG_TPL_PAD_TO 0x20000 57 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 58 #define CONFIG_SYS_TEXT_BASE 0x11001000 59 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 60 #endif 61 62 #ifndef CONFIG_SYS_TEXT_BASE 63 #define CONFIG_SYS_TEXT_BASE 0xeff40000 64 #endif 65 66 #ifndef CONFIG_RESET_VECTOR_ADDRESS 67 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 68 #endif 69 70 #ifdef CONFIG_SPL_BUILD 71 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 72 #else 73 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 74 #endif 75 76 #ifdef CONFIG_SPL_BUILD 77 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 78 #endif 79 80 /* High Level Configuration Options */ 81 #define CONFIG_BOOKE /* BOOKE */ 82 #define CONFIG_E500 /* BOOKE e500 family */ 83 #define CONFIG_FSL_IFC /* Enable IFC Support */ 84 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 85 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 86 87 #define CONFIG_PCI /* Enable PCI/PCIE */ 88 #ifdef CONFIG_PCI 89 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 90 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 91 #define CONFIG_PCI_INDIRECT_BRIDGE 92 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 93 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 94 95 #define CONFIG_CMD_PCI 96 97 /* 98 * PCI Windows 99 * Memory space is mapped 1-1, but I/O space must start from 0. 100 */ 101 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 102 #define CONFIG_SYS_PCIE1_NAME "Slot 1" 103 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 104 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 105 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 106 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 107 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 108 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 109 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 110 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull 111 112 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 113 114 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 115 #define CONFIG_DOS_PARTITION 116 #endif 117 118 #define CONFIG_FSL_LAW /* Use common FSL init code */ 119 #define CONFIG_TSEC_ENET 120 #define CONFIG_ENV_OVERWRITE 121 122 #define CONFIG_DDR_CLK_FREQ 100000000 123 #define CONFIG_SYS_CLK_FREQ 66666666 124 125 #define CONFIG_HWCONFIG 126 127 /* 128 * These can be toggled for performance analysis, otherwise use default. 129 */ 130 #define CONFIG_L2_CACHE /* toggle L2 cache */ 131 #define CONFIG_BTB /* toggle branch predition */ 132 133 #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ 134 135 #define CONFIG_ENABLE_36BIT_PHYS 136 137 #define CONFIG_ADDR_MAP 1 138 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 139 140 #define CONFIG_SYS_MEMTEST_START 0x00200000 141 #define CONFIG_SYS_MEMTEST_END 0x00400000 142 #define CONFIG_PANIC_HANG 143 144 /* DDR Setup */ 145 #define CONFIG_SYS_FSL_DDR3 146 #define CONFIG_DDR_SPD 147 #define CONFIG_SYS_SPD_BUS_NUM 0 148 #define SPD_EEPROM_ADDRESS 0x50 149 #define CONFIG_SYS_DDR_RAW_TIMING 150 151 /* DDR ECC Setup*/ 152 #define CONFIG_DDR_ECC 153 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 154 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 155 156 #define CONFIG_SYS_SDRAM_SIZE 512 157 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 158 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 159 160 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 161 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 162 163 #define CONFIG_SYS_CCSRBAR 0xffe00000 164 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 165 166 /* Platform SRAM setting */ 167 #define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 168 #define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ 169 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) 170 #define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) 171 172 #ifdef CONFIG_SPL_BUILD 173 #define CONFIG_SYS_NO_FLASH 174 #endif 175 176 /* 177 * IFC Definitions 178 */ 179 /* NOR Flash on IFC */ 180 #define CONFIG_SYS_FLASH_BASE 0xec000000 181 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ 182 183 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 184 185 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } 186 #define CONFIG_SYS_MAX_FLASH_BANKS 1 187 188 #define CONFIG_SYS_FLASH_QUIET_TEST 189 #define CONFIG_FLASH_SHOW_PROGRESS 45 190 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ 191 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ 192 193 /* 16Bit NOR Flash - S29GL512S10TFI01 */ 194 #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 195 CSPR_PORT_SIZE_16 | \ 196 CSPR_MSEL_NOR | \ 197 CSPR_V) 198 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) 199 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 200 201 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ 202 FTIM0_NOR_TEADC(0x5) | \ 203 FTIM0_NOR_TEAHC(0x5)) 204 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 205 FTIM1_NOR_TRAD_NOR(0x1A) |\ 206 FTIM1_NOR_TSEQRAD_NOR(0x13)) 207 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ 208 FTIM2_NOR_TCH(0x4) | \ 209 FTIM2_NOR_TWPH(0x0E) | \ 210 FTIM2_NOR_TWP(0x1c)) 211 #define CONFIG_SYS_NOR_FTIM3 0x0 212 213 /* CFI for NOR Flash */ 214 #define CONFIG_FLASH_CFI_DRIVER 215 #define CONFIG_SYS_FLASH_CFI 216 #define CONFIG_SYS_FLASH_EMPTY_INFO 217 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 218 219 /* NAND Flash on IFC */ 220 #define CONFIG_NAND_FSL_IFC 221 #define CONFIG_SYS_NAND_BASE 0xff800000 222 #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull 223 224 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 225 226 #define CONFIG_SYS_MAX_NAND_DEVICE 1 227 #define CONFIG_CMD_NAND 228 #define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) 229 230 /* 8Bit NAND Flash - K9F1G08U0B */ 231 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 232 | CSPR_PORT_SIZE_8 \ 233 | CSPR_MSEL_NAND \ 234 | CSPR_V) 235 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 236 #define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ 237 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 238 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 239 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 240 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ 241 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ 242 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ 243 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ 244 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ 245 FTIM0_NAND_TWP(0x0c) | \ 246 FTIM0_NAND_TWCHT(0x08) | \ 247 FTIM0_NAND_TWH(0x06)) 248 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ 249 FTIM1_NAND_TWBE(0x1d) | \ 250 FTIM1_NAND_TRR(0x08) | \ 251 FTIM1_NAND_TRP(0x0c)) 252 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ 253 FTIM2_NAND_TREH(0x0a) | \ 254 FTIM2_NAND_TWHRE(0x18)) 255 #define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) 256 257 #define CONFIG_SYS_NAND_DDR_LAW 11 258 259 /* Set up IFC registers for boot location NOR/NAND */ 260 #ifdef CONFIG_NAND 261 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 262 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 263 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 264 #define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE 265 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 266 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 267 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 268 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 269 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 270 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 271 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 272 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 273 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 274 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 275 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 276 #else 277 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 278 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 279 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 280 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 281 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 282 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 283 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 284 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 285 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 286 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 287 #define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE 288 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 289 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 290 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 291 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 292 #endif 293 294 /* CPLD on IFC, selected by CS2 */ 295 #define CONFIG_SYS_CPLD_BASE 0xffdf0000 296 #define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ 297 | CONFIG_SYS_CPLD_BASE) 298 299 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ 300 | CSPR_PORT_SIZE_8 \ 301 | CSPR_MSEL_GPCM \ 302 | CSPR_V) 303 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 304 #define CONFIG_SYS_CSOR2 0x0 305 /* CPLD Timing parameters for IFC CS2 */ 306 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 307 FTIM0_GPCM_TEADC(0x0e) | \ 308 FTIM0_GPCM_TEAHC(0x0e)) 309 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 310 FTIM1_GPCM_TRAD(0x1f)) 311 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 312 FTIM2_GPCM_TCH(0x8) | \ 313 FTIM2_GPCM_TWP(0x1f)) 314 #define CONFIG_SYS_CS2_FTIM3 0x0 315 316 #if defined(CONFIG_RAMBOOT_SPIFLASH) 317 #define CONFIG_SYS_RAMBOOT 318 #define CONFIG_SYS_EXTRA_ENV_RELOC 319 #endif 320 321 #define CONFIG_BOARD_EARLY_INIT_R 322 323 #define CONFIG_SYS_INIT_RAM_LOCK 324 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 325 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 326 327 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 328 - GENERATED_GBL_DATA_SIZE) 329 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 330 331 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 332 #define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) 333 334 /* 335 * Config the L2 Cache as L2 SRAM 336 */ 337 #if defined(CONFIG_SPL_BUILD) 338 #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) 339 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 340 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 341 #define CONFIG_SYS_L2_SIZE (256 << 10) 342 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 343 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 344 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) 345 #define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) 346 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) 347 #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) 348 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) 349 #elif defined(CONFIG_NAND) 350 #ifdef CONFIG_TPL_BUILD 351 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 352 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 353 #define CONFIG_SYS_L2_SIZE (256 << 10) 354 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 355 #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 356 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) 357 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) 358 #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) 359 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) 360 #else 361 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 362 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 363 #define CONFIG_SYS_L2_SIZE (256 << 10) 364 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 365 #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) 366 #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 367 #endif 368 #endif 369 #endif 370 371 /* Serial Port */ 372 #define CONFIG_CONS_INDEX 1 373 #define CONFIG_SYS_NS16550_SERIAL 374 #define CONFIG_SYS_NS16550_REG_SIZE 1 375 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 376 377 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) 378 #define CONFIG_NS16550_MIN_FUNCTIONS 379 #endif 380 381 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 382 383 #define CONFIG_SYS_BAUDRATE_TABLE \ 384 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 385 386 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 387 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 388 389 #define CONFIG_SYS_I2C 390 #define CONFIG_SYS_I2C_FSL 391 #define CONFIG_SYS_FSL_I2C_SPEED 400000 392 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 393 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 394 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 395 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 396 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 397 398 /* I2C EEPROM */ 399 /* enable read and write access to EEPROM */ 400 #define CONFIG_CMD_EEPROM 401 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 402 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 403 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 404 405 /* eSPI - Enhanced SPI */ 406 #define CONFIG_SF_DEFAULT_SPEED 10000000 407 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 408 409 #ifdef CONFIG_TSEC_ENET 410 #define CONFIG_MII /* MII PHY management */ 411 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 412 #define CONFIG_TSEC1 1 413 #define CONFIG_TSEC1_NAME "eTSEC1" 414 #define CONFIG_TSEC2 1 415 #define CONFIG_TSEC2_NAME "eTSEC2" 416 417 /* Default mode is RGMII mode */ 418 #define TSEC1_PHY_ADDR 0 419 #define TSEC2_PHY_ADDR 2 420 421 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 422 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 423 424 #define CONFIG_ETHPRIME "eTSEC1" 425 426 #define CONFIG_PHY_GIGE 427 #endif /* CONFIG_TSEC_ENET */ 428 429 /* 430 * Environment 431 */ 432 #if defined(CONFIG_SYS_RAMBOOT) 433 #if defined(CONFIG_RAMBOOT_SPIFLASH) 434 #define CONFIG_ENV_IS_IN_SPI_FLASH 435 #define CONFIG_ENV_SPI_BUS 0 436 #define CONFIG_ENV_SPI_CS 0 437 #define CONFIG_ENV_SPI_MAX_HZ 10000000 438 #define CONFIG_ENV_SPI_MODE 0 439 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 440 #define CONFIG_ENV_SECT_SIZE 0x10000 441 #define CONFIG_ENV_SIZE 0x2000 442 #endif 443 #elif defined(CONFIG_NAND) 444 #define CONFIG_ENV_IS_IN_NAND 445 #ifdef CONFIG_TPL_BUILD 446 #define CONFIG_ENV_SIZE 0x2000 447 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) 448 #else 449 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 450 #define CONFIG_ENV_RANGE CONFIG_ENV_SIZE 451 #endif 452 #define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE 453 #else 454 #define CONFIG_ENV_IS_IN_FLASH 455 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 456 #define CONFIG_ENV_SIZE 0x2000 457 #define CONFIG_ENV_SECT_SIZE 0x20000 458 #endif 459 460 #define CONFIG_LOADS_ECHO 461 #define CONFIG_SYS_LOADS_BAUD_CHANGE 462 463 /* 464 * Command line configuration. 465 */ 466 #define CONFIG_CMD_ERRATA 467 #define CONFIG_CMD_IRQ 468 #define CONFIG_CMD_REGINFO 469 470 /* Hash command with SHA acceleration supported in hardware */ 471 #ifdef CONFIG_FSL_CAAM 472 #define CONFIG_CMD_HASH 473 #define CONFIG_SHA_HW_ACCEL 474 #endif 475 476 /* 477 * Miscellaneous configurable options 478 */ 479 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 480 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 481 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 482 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 483 484 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 485 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 486 /* Print Buffer Size */ 487 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 488 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 489 490 /* 491 * For booting Linux, the board info and command line data 492 * have to be in the first 64 MB of memory, since this is 493 * the maximum mapped by the Linux kernel during initialization. 494 */ 495 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 496 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 497 498 /* 499 * Environment Configuration 500 */ 501 502 #ifdef CONFIG_TSEC_ENET 503 #define CONFIG_HAS_ETH0 504 #define CONFIG_HAS_ETH1 505 #endif 506 507 #define CONFIG_ROOTPATH "/opt/nfsroot" 508 #define CONFIG_BOOTFILE "uImage" 509 #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ 510 511 /* default location for tftp and bootm */ 512 #define CONFIG_LOADADDR 1000000 513 514 515 #define CONFIG_BAUDRATE 115200 516 517 #define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on 518 519 #define CONFIG_EXTRA_ENV_SETTINGS \ 520 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ 521 "netdev=eth0\0" \ 522 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 523 "loadaddr=1000000\0" \ 524 "consoledev=ttyS0\0" \ 525 "ramdiskaddr=2000000\0" \ 526 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 527 "fdtaddr=1e00000\0" \ 528 "fdtfile=name/of/device-tree.dtb\0" \ 529 "othbootargs=ramdisk_size=600000\0" \ 530 531 #define CONFIG_RAMBOOTCOMMAND \ 532 "setenv bootargs root=/dev/ram rw " \ 533 "console=$consoledev,$baudrate $othbootargs; " \ 534 "tftp $ramdiskaddr $ramdiskfile;" \ 535 "tftp $loadaddr $bootfile;" \ 536 "tftp $fdtaddr $fdtfile;" \ 537 "bootm $loadaddr $ramdiskaddr $fdtaddr" 538 539 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 540 541 #include <asm/fsl_secure_boot.h> 542 543 #endif /* __CONFIG_H */ 544