1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9132 QDS board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #ifdef CONFIG_BSC9132QDS 15 #define CONFIG_BSC9132 16 #endif 17 18 #define CONFIG_MISC_INIT_R 19 20 #ifdef CONFIG_SDCARD 21 #define CONFIG_RAMBOOT_SDCARD 22 #define CONFIG_SYS_RAMBOOT 23 #define CONFIG_SYS_EXTRA_ENV_RELOC 24 #define CONFIG_SYS_TEXT_BASE 0x11000000 25 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 26 #endif 27 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 28 #ifdef CONFIG_SPIFLASH 29 #define CONFIG_RAMBOOT_SPIFLASH 30 #define CONFIG_SYS_RAMBOOT 31 #define CONFIG_SYS_EXTRA_ENV_RELOC 32 #define CONFIG_SYS_TEXT_BASE 0x11000000 33 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 34 #endif 35 #ifdef CONFIG_NAND_SECBOOT 36 #define CONFIG_RAMBOOT_NAND 37 #define CONFIG_SYS_RAMBOOT 38 #define CONFIG_SYS_EXTRA_ENV_RELOC 39 #define CONFIG_SYS_TEXT_BASE 0x11000000 40 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 41 #endif 42 43 #ifdef CONFIG_NAND 44 #define CONFIG_SPL_INIT_MINIMAL 45 #define CONFIG_SPL_NAND_BOOT 46 #define CONFIG_SPL_FLUSH_IMAGE 47 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 48 49 #define CONFIG_SYS_TEXT_BASE 0x00201000 50 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 51 #define CONFIG_SPL_MAX_SIZE 8192 52 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 53 #define CONFIG_SPL_RELOC_STACK 0x00100000 54 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 55 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 56 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 57 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 58 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 59 #endif 60 61 #ifndef CONFIG_SYS_TEXT_BASE 62 #define CONFIG_SYS_TEXT_BASE 0x8ff40000 63 #endif 64 65 #ifndef CONFIG_RESET_VECTOR_ADDRESS 66 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 67 #endif 68 69 #ifdef CONFIG_SPL_BUILD 70 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 71 #else 72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 73 #endif 74 75 /* High Level Configuration Options */ 76 #define CONFIG_BOOKE /* BOOKE */ 77 #define CONFIG_E500 /* BOOKE e500 family */ 78 #define CONFIG_FSL_IFC /* Enable IFC Support */ 79 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 80 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 81 82 #if defined(CONFIG_PCI) 83 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 84 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 85 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 86 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 87 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 88 89 #define CONFIG_CMD_PCI 90 91 /* 92 * PCI Windows 93 * Memory space is mapped 1-1, but I/O space must start from 0. 94 */ 95 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 96 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 97 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 98 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 99 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 100 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 101 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 102 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 103 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 104 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 105 106 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 107 108 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 109 #define CONFIG_DOS_PARTITION 110 #endif 111 112 #define CONFIG_FSL_LAW /* Use common FSL init code */ 113 #define CONFIG_ENV_OVERWRITE 114 #define CONFIG_TSEC_ENET /* ethernet */ 115 116 #if defined(CONFIG_SYS_CLK_100_DDR_100) 117 #define CONFIG_SYS_CLK_FREQ 100000000 118 #define CONFIG_DDR_CLK_FREQ 100000000 119 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 120 #define CONFIG_SYS_CLK_FREQ 100000000 121 #define CONFIG_DDR_CLK_FREQ 133000000 122 #endif 123 124 #define CONFIG_MP 125 126 #define CONFIG_HWCONFIG 127 /* 128 * These can be toggled for performance analysis, otherwise use default. 129 */ 130 #define CONFIG_L2_CACHE /* toggle L2 cache */ 131 #define CONFIG_BTB /* enable branch predition */ 132 133 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 134 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 135 136 /* DDR Setup */ 137 #define CONFIG_SYS_FSL_DDR3 138 #define CONFIG_SYS_SPD_BUS_NUM 0 139 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 140 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 141 #define CONFIG_FSL_DDR_INTERACTIVE 142 143 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 144 145 #define CONFIG_SYS_SDRAM_SIZE (1024) 146 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 147 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 148 149 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 150 151 /* DDR3 Controller Settings */ 152 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 153 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 154 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 155 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 156 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 157 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 158 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 159 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 160 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 161 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 162 163 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 164 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 165 #define CONFIG_SYS_DDR_RCW_1 0x00000000 166 #define CONFIG_SYS_DDR_RCW_2 0x00000000 167 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 168 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 169 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 170 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 171 172 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 173 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 174 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 175 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 176 177 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 178 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 179 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 180 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 181 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 182 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 183 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 184 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 185 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 186 187 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 188 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 189 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 190 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 191 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 192 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 193 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 194 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 195 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 196 197 /*FIXME: the following params are constant w.r.t diff freq 198 combinations. this should be removed later 199 */ 200 #if CONFIG_DDR_CLK_FREQ == 100000000 201 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 202 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 203 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 204 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 205 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 206 #elif CONFIG_DDR_CLK_FREQ == 133000000 207 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 208 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 209 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 210 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 211 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 212 #else 213 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 214 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 215 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 216 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 217 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 218 #endif 219 220 /* relocated CCSRBAR */ 221 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 222 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 223 224 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 225 226 /* DSP CCSRBAR */ 227 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 228 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 229 230 /* 231 * IFC Definitions 232 */ 233 /* NOR Flash on IFC */ 234 235 #ifdef CONFIG_SPL_BUILD 236 #define CONFIG_SYS_NO_FLASH 237 #endif 238 #define CONFIG_SYS_FLASH_BASE 0x88000000 239 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 240 241 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 242 243 #define CONFIG_SYS_NOR_CSPR 0x88000101 244 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 245 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 246 /* NOR Flash Timing Params */ 247 248 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 249 | FTIM0_NOR_TEADC(0x03) \ 250 | FTIM0_NOR_TAVDS(0x00) \ 251 | FTIM0_NOR_TEAHC(0x0f)) 252 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 253 | FTIM1_NOR_TRAD_NOR(0x09) \ 254 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 255 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 256 | FTIM2_NOR_TCH(0x4) \ 257 | FTIM2_NOR_TWPH(0x7) \ 258 | FTIM2_NOR_TWP(0x1e)) 259 #define CONFIG_SYS_NOR_FTIM3 0x0 260 261 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 262 #define CONFIG_SYS_FLASH_QUIET_TEST 263 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 264 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 265 266 #undef CONFIG_SYS_FLASH_CHECKSUM 267 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 268 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 269 270 /* CFI for NOR Flash */ 271 #define CONFIG_FLASH_CFI_DRIVER 272 #define CONFIG_SYS_FLASH_CFI 273 #define CONFIG_SYS_FLASH_EMPTY_INFO 274 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 275 276 /* NAND Flash on IFC */ 277 #define CONFIG_SYS_NAND_BASE 0xff800000 278 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 279 280 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 281 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 282 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 283 | CSPR_V) 284 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 285 286 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 287 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 288 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 289 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 290 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 291 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 292 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 293 294 /* NAND Flash Timing Params */ 295 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 296 | FTIM0_NAND_TWP(0x05) \ 297 | FTIM0_NAND_TWCHT(0x02) \ 298 | FTIM0_NAND_TWH(0x04)) 299 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 300 | FTIM1_NAND_TWBE(0x1e) \ 301 | FTIM1_NAND_TRR(0x07) \ 302 | FTIM1_NAND_TRP(0x05)) 303 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 304 | FTIM2_NAND_TREH(0x04) \ 305 | FTIM2_NAND_TWHRE(0x11)) 306 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 307 308 #define CONFIG_SYS_NAND_DDR_LAW 11 309 310 /* NAND */ 311 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 312 #define CONFIG_SYS_MAX_NAND_DEVICE 1 313 #define CONFIG_CMD_NAND 314 315 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 316 317 #ifndef CONFIG_SPL_BUILD 318 #define CONFIG_FSL_QIXIS 319 #endif 320 #ifdef CONFIG_FSL_QIXIS 321 #define CONFIG_SYS_FPGA_BASE 0xffb00000 322 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 323 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 324 #define QIXIS_LBMAP_SWITCH 9 325 #define QIXIS_LBMAP_MASK 0x07 326 #define QIXIS_LBMAP_SHIFT 0 327 #define QIXIS_LBMAP_DFLTBANK 0x00 328 #define QIXIS_LBMAP_ALTBANK 0x04 329 #define QIXIS_RST_CTL_RESET 0x83 330 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 331 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 332 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 333 334 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 335 336 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 337 | CSPR_PORT_SIZE_8 \ 338 | CSPR_MSEL_GPCM \ 339 | CSPR_V) 340 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 341 #define CONFIG_SYS_CSOR2 0x0 342 /* CPLD Timing parameters for IFC CS3 */ 343 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 344 FTIM0_GPCM_TEADC(0x0e) | \ 345 FTIM0_GPCM_TEAHC(0x0e)) 346 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 347 FTIM1_GPCM_TRAD(0x1f)) 348 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 349 FTIM2_GPCM_TCH(0x8) | \ 350 FTIM2_GPCM_TWP(0x1f)) 351 #define CONFIG_SYS_CS2_FTIM3 0x0 352 #endif 353 354 /* Set up IFC registers for boot location NOR/NAND */ 355 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 356 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 357 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 358 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 359 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 360 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 361 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 362 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 363 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 364 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 365 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 366 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 367 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 368 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 369 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 370 #else 371 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 372 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 373 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 374 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 375 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 376 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 377 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 378 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 379 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 380 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 381 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 382 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 383 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 384 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 385 #endif 386 387 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 388 #define CONFIG_BOARD_EARLY_INIT_R 389 390 #define CONFIG_SYS_INIT_RAM_LOCK 391 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 392 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 393 394 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 395 - GENERATED_GBL_DATA_SIZE) 396 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 397 398 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 399 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 400 401 /* Serial Port */ 402 #define CONFIG_CONS_INDEX 1 403 #undef CONFIG_SERIAL_SOFTWARE_FIFO 404 #define CONFIG_SYS_NS16550_SERIAL 405 #define CONFIG_SYS_NS16550_REG_SIZE 1 406 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 407 #ifdef CONFIG_SPL_BUILD 408 #define CONFIG_NS16550_MIN_FUNCTIONS 409 #endif 410 411 #define CONFIG_SYS_BAUDRATE_TABLE \ 412 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 413 414 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 415 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 416 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 417 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 418 419 #define CONFIG_SYS_I2C 420 #define CONFIG_SYS_I2C_FSL 421 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 422 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 423 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 424 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 425 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 426 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 427 428 /* I2C EEPROM */ 429 #define CONFIG_ID_EEPROM 430 #ifdef CONFIG_ID_EEPROM 431 #define CONFIG_SYS_I2C_EEPROM_NXID 432 #endif 433 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 434 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 435 #define CONFIG_SYS_EEPROM_BUS_NUM 0 436 437 /* enable read and write access to EEPROM */ 438 #define CONFIG_CMD_EEPROM 439 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 440 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 441 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 442 443 /* I2C FPGA */ 444 #define CONFIG_I2C_FPGA 445 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 446 447 #define CONFIG_RTC_DS3231 448 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 449 450 /* 451 * SPI interface will not be available in case of NAND boot SPI CS0 will be 452 * used for SLIC 453 */ 454 /* eSPI - Enhanced SPI */ 455 #ifdef CONFIG_FSL_ESPI 456 #define CONFIG_SF_DEFAULT_SPEED 10000000 457 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 458 #endif 459 460 #if defined(CONFIG_TSEC_ENET) 461 462 #define CONFIG_MII /* MII PHY management */ 463 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 464 #define CONFIG_TSEC1 1 465 #define CONFIG_TSEC1_NAME "eTSEC1" 466 #define CONFIG_TSEC2 1 467 #define CONFIG_TSEC2_NAME "eTSEC2" 468 469 #define TSEC1_PHY_ADDR 0 470 #define TSEC2_PHY_ADDR 1 471 472 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 473 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 474 475 #define TSEC1_PHYIDX 0 476 #define TSEC2_PHYIDX 0 477 478 #define CONFIG_ETHPRIME "eTSEC1" 479 480 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 481 482 /* TBI PHY configuration for SGMII mode */ 483 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 484 TBICR_PHY_RESET \ 485 | TBICR_ANEG_ENABLE \ 486 | TBICR_FULL_DUPLEX \ 487 | TBICR_SPEED1_SET \ 488 ) 489 490 #endif /* CONFIG_TSEC_ENET */ 491 492 #define CONFIG_MMC 493 #ifdef CONFIG_MMC 494 #define CONFIG_DOS_PARTITION 495 #define CONFIG_FSL_ESDHC 496 #define CONFIG_GENERIC_MMC 497 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 498 #endif 499 500 #define CONFIG_USB_EHCI /* USB */ 501 #ifdef CONFIG_USB_EHCI 502 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 503 #define CONFIG_USB_EHCI_FSL 504 #define CONFIG_HAS_FSL_DR_USB 505 #endif 506 507 /* 508 * Environment 509 */ 510 #if defined(CONFIG_RAMBOOT_SDCARD) 511 #define CONFIG_ENV_IS_IN_MMC 512 #define CONFIG_FSL_FIXED_MMC_LOCATION 513 #define CONFIG_SYS_MMC_ENV_DEV 0 514 #define CONFIG_ENV_SIZE 0x2000 515 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 516 #define CONFIG_ENV_IS_IN_SPI_FLASH 517 #define CONFIG_ENV_SPI_BUS 0 518 #define CONFIG_ENV_SPI_CS 0 519 #define CONFIG_ENV_SPI_MAX_HZ 10000000 520 #define CONFIG_ENV_SPI_MODE 0 521 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 522 #define CONFIG_ENV_SECT_SIZE 0x10000 523 #define CONFIG_ENV_SIZE 0x2000 524 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 525 #define CONFIG_ENV_IS_IN_NAND 526 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 527 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 528 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 529 #elif defined(CONFIG_SYS_RAMBOOT) 530 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 531 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 532 #define CONFIG_ENV_SIZE 0x2000 533 #else 534 #define CONFIG_ENV_IS_IN_FLASH 535 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 536 #define CONFIG_ENV_SIZE 0x2000 537 #define CONFIG_ENV_SECT_SIZE 0x20000 538 #endif 539 540 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 541 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 542 543 /* 544 * Command line configuration. 545 */ 546 #define CONFIG_CMD_DATE 547 #define CONFIG_CMD_ERRATA 548 #define CONFIG_CMD_IRQ 549 #define CONFIG_CMD_REGINFO 550 551 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 552 #define CONFIG_DOS_PARTITION 553 #endif 554 555 /* Hash command with SHA acceleration supported in hardware */ 556 #ifdef CONFIG_FSL_CAAM 557 #define CONFIG_CMD_HASH 558 #define CONFIG_SHA_HW_ACCEL 559 #endif 560 561 /* 562 * Miscellaneous configurable options 563 */ 564 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 565 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 566 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 567 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 568 569 #if defined(CONFIG_CMD_KGDB) 570 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 571 #else 572 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 573 #endif 574 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 575 /* Print Buffer Size */ 576 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 577 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 578 579 /* 580 * For booting Linux, the board info and command line data 581 * have to be in the first 64 MB of memory, since this is 582 * the maximum mapped by the Linux kernel during initialization. 583 */ 584 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 585 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 586 587 #if defined(CONFIG_CMD_KGDB) 588 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 589 #endif 590 591 /* 592 * Dynamic MTD Partition support with mtdparts 593 */ 594 #ifndef CONFIG_SYS_NO_FLASH 595 #define CONFIG_MTD_DEVICE 596 #define CONFIG_MTD_PARTITIONS 597 #define CONFIG_CMD_MTDPARTS 598 #define CONFIG_FLASH_CFI_MTD 599 #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," 600 #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ 601 "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ 602 "8m(kernel),512k(dtb),-(fs)" 603 #endif 604 /* 605 * Environment Configuration 606 */ 607 608 #if defined(CONFIG_TSEC_ENET) 609 #define CONFIG_HAS_ETH0 610 #define CONFIG_HAS_ETH1 611 #endif 612 613 #define CONFIG_HOSTNAME BSC9132qds 614 #define CONFIG_ROOTPATH "/opt/nfsroot" 615 #define CONFIG_BOOTFILE "uImage" 616 #define CONFIG_UBOOTPATH "u-boot.bin" 617 618 #define CONFIG_BAUDRATE 115200 619 620 #ifdef CONFIG_SDCARD 621 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 622 #else 623 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 624 #endif 625 626 #define CONFIG_EXTRA_ENV_SETTINGS \ 627 "netdev=eth0\0" \ 628 "uboot=" CONFIG_UBOOTPATH "\0" \ 629 "loadaddr=1000000\0" \ 630 "bootfile=uImage\0" \ 631 "consoledev=ttyS0\0" \ 632 "ramdiskaddr=2000000\0" \ 633 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 634 "fdtaddr=1e00000\0" \ 635 "fdtfile=bsc9132qds.dtb\0" \ 636 "bdev=sda1\0" \ 637 CONFIG_DEF_HWCONFIG\ 638 "othbootargs=mem=880M ramdisk_size=600000 " \ 639 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 640 "isolcpus=0\0" \ 641 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 642 "console=$consoledev,$baudrate $othbootargs; " \ 643 "usb start;" \ 644 "ext2load usb 0:4 $loadaddr $bootfile;" \ 645 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 646 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 647 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 648 "debug_halt_off=mw ff7e0e30 0xf0000000;" 649 650 #define CONFIG_NFSBOOTCOMMAND \ 651 "setenv bootargs root=/dev/nfs rw " \ 652 "nfsroot=$serverip:$rootpath " \ 653 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 654 "console=$consoledev,$baudrate $othbootargs;" \ 655 "tftp $loadaddr $bootfile;" \ 656 "tftp $fdtaddr $fdtfile;" \ 657 "bootm $loadaddr - $fdtaddr" 658 659 #define CONFIG_HDBOOT \ 660 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 661 "console=$consoledev,$baudrate $othbootargs;" \ 662 "usb start;" \ 663 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 664 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 665 "bootm $loadaddr - $fdtaddr" 666 667 #define CONFIG_RAMBOOTCOMMAND \ 668 "setenv bootargs root=/dev/ram rw " \ 669 "console=$consoledev,$baudrate $othbootargs; " \ 670 "tftp $ramdiskaddr $ramdiskfile;" \ 671 "tftp $loadaddr $bootfile;" \ 672 "tftp $fdtaddr $fdtfile;" \ 673 "bootm $loadaddr $ramdiskaddr $fdtaddr" 674 675 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 676 677 #include <asm/fsl_secure_boot.h> 678 679 #endif /* __CONFIG_H */ 680