1 /* 2 * Copyright 2013 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * BSC9132 QDS board configuration file 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #define CONFIG_MISC_INIT_R 15 16 #ifdef CONFIG_SDCARD 17 #define CONFIG_RAMBOOT_SDCARD 18 #define CONFIG_SYS_RAMBOOT 19 #define CONFIG_SYS_EXTRA_ENV_RELOC 20 #define CONFIG_SYS_TEXT_BASE 0x11000000 21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 22 #endif 23 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 24 #ifdef CONFIG_SPIFLASH 25 #define CONFIG_RAMBOOT_SPIFLASH 26 #define CONFIG_SYS_RAMBOOT 27 #define CONFIG_SYS_EXTRA_ENV_RELOC 28 #define CONFIG_SYS_TEXT_BASE 0x11000000 29 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 30 #endif 31 #ifdef CONFIG_NAND_SECBOOT 32 #define CONFIG_RAMBOOT_NAND 33 #define CONFIG_SYS_RAMBOOT 34 #define CONFIG_SYS_EXTRA_ENV_RELOC 35 #define CONFIG_SYS_TEXT_BASE 0x11000000 36 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc 37 #endif 38 39 #ifdef CONFIG_NAND 40 #define CONFIG_SPL_INIT_MINIMAL 41 #define CONFIG_SPL_NAND_BOOT 42 #define CONFIG_SPL_FLUSH_IMAGE 43 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 44 45 #define CONFIG_SYS_TEXT_BASE 0x00201000 46 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 47 #define CONFIG_SPL_MAX_SIZE 8192 48 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 49 #define CONFIG_SPL_RELOC_STACK 0x00100000 50 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) 51 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) 52 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 53 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 54 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 55 #endif 56 57 #ifndef CONFIG_SYS_TEXT_BASE 58 #define CONFIG_SYS_TEXT_BASE 0x8ff40000 59 #endif 60 61 #ifndef CONFIG_RESET_VECTOR_ADDRESS 62 #define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc 63 #endif 64 65 #ifdef CONFIG_SPL_BUILD 66 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 67 #else 68 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 69 #endif 70 71 /* High Level Configuration Options */ 72 #define CONFIG_FSL_IFC /* Enable IFC Support */ 73 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 74 #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ 75 76 #if defined(CONFIG_PCI) 77 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 78 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 79 #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 80 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 81 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 82 83 #define CONFIG_CMD_PCI 84 85 /* 86 * PCI Windows 87 * Memory space is mapped 1-1, but I/O space must start from 0. 88 */ 89 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 90 #define CONFIG_SYS_PCIE1_NAME "PCIe Slot" 91 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 92 #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 93 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 94 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ 95 #define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 96 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 97 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 98 #define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 99 100 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 101 #define CONFIG_DOS_PARTITION 102 #endif 103 104 #define CONFIG_ENV_OVERWRITE 105 #define CONFIG_TSEC_ENET /* ethernet */ 106 107 #if defined(CONFIG_SYS_CLK_100_DDR_100) 108 #define CONFIG_SYS_CLK_FREQ 100000000 109 #define CONFIG_DDR_CLK_FREQ 100000000 110 #elif defined(CONFIG_SYS_CLK_100_DDR_133) 111 #define CONFIG_SYS_CLK_FREQ 100000000 112 #define CONFIG_DDR_CLK_FREQ 133000000 113 #endif 114 115 #define CONFIG_MP 116 117 #define CONFIG_HWCONFIG 118 /* 119 * These can be toggled for performance analysis, otherwise use default. 120 */ 121 #define CONFIG_L2_CACHE /* toggle L2 cache */ 122 #define CONFIG_BTB /* enable branch predition */ 123 124 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ 125 #define CONFIG_SYS_MEMTEST_END 0x01ffffff 126 127 /* DDR Setup */ 128 #define CONFIG_SYS_FSL_DDR3 129 #define CONFIG_SYS_SPD_BUS_NUM 0 130 #define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ 131 #define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ 132 #define CONFIG_FSL_DDR_INTERACTIVE 133 134 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 135 136 #define CONFIG_SYS_SDRAM_SIZE (1024) 137 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 138 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 139 140 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 141 142 /* DDR3 Controller Settings */ 143 #define CONFIG_CHIP_SELECTS_PER_CTRL 1 144 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F 145 #define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 146 #define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 147 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 148 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 149 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 150 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 151 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 152 #define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F 153 154 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 155 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 156 #define CONFIG_SYS_DDR_RCW_1 0x00000000 157 #define CONFIG_SYS_DDR_RCW_2 0x00000000 158 #define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 159 #define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 160 #define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 161 #define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 162 163 #define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 164 #define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 165 #define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 166 #define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 167 168 #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 169 #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 170 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 171 #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF 172 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 173 #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 174 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 175 #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 176 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 177 178 #define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 179 #define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 180 #define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 181 #define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 182 #define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 183 #define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 184 #define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 185 #define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 186 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 187 188 /*FIXME: the following params are constant w.r.t diff freq 189 combinations. this should be removed later 190 */ 191 #if CONFIG_DDR_CLK_FREQ == 100000000 192 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 193 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 194 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 195 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 196 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 197 #elif CONFIG_DDR_CLK_FREQ == 133000000 198 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 199 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 200 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 201 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 202 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 203 #else 204 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 205 #define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 206 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 207 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 208 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 209 #endif 210 211 /* relocated CCSRBAR */ 212 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 213 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT 214 215 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR 216 217 /* DSP CCSRBAR */ 218 #define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 219 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 220 221 /* 222 * IFC Definitions 223 */ 224 /* NOR Flash on IFC */ 225 226 #ifdef CONFIG_SPL_BUILD 227 #define CONFIG_SYS_NO_FLASH 228 #endif 229 #define CONFIG_SYS_FLASH_BASE 0x88000000 230 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ 231 232 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 233 234 #define CONFIG_SYS_NOR_CSPR 0x88000101 235 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) 236 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) 237 /* NOR Flash Timing Params */ 238 239 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ 240 | FTIM0_NOR_TEADC(0x03) \ 241 | FTIM0_NOR_TAVDS(0x00) \ 242 | FTIM0_NOR_TEAHC(0x0f)) 243 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ 244 | FTIM1_NOR_TRAD_NOR(0x09) \ 245 | FTIM1_NOR_TSEQRAD_NOR(0x09)) 246 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ 247 | FTIM2_NOR_TCH(0x4) \ 248 | FTIM2_NOR_TWPH(0x7) \ 249 | FTIM2_NOR_TWP(0x1e)) 250 #define CONFIG_SYS_NOR_FTIM3 0x0 251 252 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} 253 #define CONFIG_SYS_FLASH_QUIET_TEST 254 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 255 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 256 257 #undef CONFIG_SYS_FLASH_CHECKSUM 258 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 259 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 260 261 /* CFI for NOR Flash */ 262 #define CONFIG_FLASH_CFI_DRIVER 263 #define CONFIG_SYS_FLASH_CFI 264 #define CONFIG_SYS_FLASH_EMPTY_INFO 265 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 266 267 /* NAND Flash on IFC */ 268 #define CONFIG_SYS_NAND_BASE 0xff800000 269 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 270 271 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 272 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 273 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 274 | CSPR_V) 275 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) 276 277 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 278 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 279 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 280 | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ 281 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 282 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 283 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 284 285 /* NAND Flash Timing Params */ 286 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ 287 | FTIM0_NAND_TWP(0x05) \ 288 | FTIM0_NAND_TWCHT(0x02) \ 289 | FTIM0_NAND_TWH(0x04)) 290 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ 291 | FTIM1_NAND_TWBE(0x1e) \ 292 | FTIM1_NAND_TRR(0x07) \ 293 | FTIM1_NAND_TRP(0x05)) 294 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ 295 | FTIM2_NAND_TREH(0x04) \ 296 | FTIM2_NAND_TWHRE(0x11)) 297 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) 298 299 #define CONFIG_SYS_NAND_DDR_LAW 11 300 301 /* NAND */ 302 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 303 #define CONFIG_SYS_MAX_NAND_DEVICE 1 304 #define CONFIG_CMD_NAND 305 306 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 307 308 #ifndef CONFIG_SPL_BUILD 309 #define CONFIG_FSL_QIXIS 310 #endif 311 #ifdef CONFIG_FSL_QIXIS 312 #define CONFIG_SYS_FPGA_BASE 0xffb00000 313 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 314 #define QIXIS_BASE CONFIG_SYS_FPGA_BASE 315 #define QIXIS_LBMAP_SWITCH 9 316 #define QIXIS_LBMAP_MASK 0x07 317 #define QIXIS_LBMAP_SHIFT 0 318 #define QIXIS_LBMAP_DFLTBANK 0x00 319 #define QIXIS_LBMAP_ALTBANK 0x04 320 #define QIXIS_RST_CTL_RESET 0x83 321 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 322 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 323 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 324 325 #define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE 326 327 #define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ 328 | CSPR_PORT_SIZE_8 \ 329 | CSPR_MSEL_GPCM \ 330 | CSPR_V) 331 #define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) 332 #define CONFIG_SYS_CSOR2 0x0 333 /* CPLD Timing parameters for IFC CS3 */ 334 #define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 335 FTIM0_GPCM_TEADC(0x0e) | \ 336 FTIM0_GPCM_TEAHC(0x0e)) 337 #define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 338 FTIM1_GPCM_TRAD(0x1f)) 339 #define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 340 FTIM2_GPCM_TCH(0x8) | \ 341 FTIM2_GPCM_TWP(0x1f)) 342 #define CONFIG_SYS_CS2_FTIM3 0x0 343 #endif 344 345 /* Set up IFC registers for boot location NOR/NAND */ 346 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 347 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 348 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 349 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 350 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 351 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 352 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 353 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 354 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR 355 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 356 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 357 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 358 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 359 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 360 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 361 #else 362 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR 363 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 364 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 365 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 366 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 367 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 368 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 369 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR 370 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK 371 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR 372 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 373 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 374 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 375 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 376 #endif 377 378 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ 379 #define CONFIG_BOARD_EARLY_INIT_R 380 381 #define CONFIG_SYS_INIT_RAM_LOCK 382 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ 383 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ 384 385 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ 386 - GENERATED_GBL_DATA_SIZE) 387 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 388 389 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 390 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ 391 392 /* Serial Port */ 393 #define CONFIG_CONS_INDEX 1 394 #undef CONFIG_SERIAL_SOFTWARE_FIFO 395 #define CONFIG_SYS_NS16550_SERIAL 396 #define CONFIG_SYS_NS16550_REG_SIZE 1 397 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 398 #ifdef CONFIG_SPL_BUILD 399 #define CONFIG_NS16550_MIN_FUNCTIONS 400 #endif 401 402 #define CONFIG_SYS_BAUDRATE_TABLE \ 403 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 404 405 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) 406 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) 407 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) 408 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) 409 410 #define CONFIG_SYS_I2C 411 #define CONFIG_SYS_I2C_FSL 412 #define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ 413 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 414 #define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ 415 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 416 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 417 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 418 419 /* I2C EEPROM */ 420 #define CONFIG_ID_EEPROM 421 #ifdef CONFIG_ID_EEPROM 422 #define CONFIG_SYS_I2C_EEPROM_NXID 423 #endif 424 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 425 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 426 #define CONFIG_SYS_EEPROM_BUS_NUM 0 427 428 /* enable read and write access to EEPROM */ 429 #define CONFIG_CMD_EEPROM 430 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 431 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 432 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 433 434 /* I2C FPGA */ 435 #define CONFIG_I2C_FPGA 436 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 437 438 #define CONFIG_RTC_DS3231 439 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 440 441 /* 442 * SPI interface will not be available in case of NAND boot SPI CS0 will be 443 * used for SLIC 444 */ 445 /* eSPI - Enhanced SPI */ 446 #ifdef CONFIG_FSL_ESPI 447 #define CONFIG_SF_DEFAULT_SPEED 10000000 448 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 449 #endif 450 451 #if defined(CONFIG_TSEC_ENET) 452 453 #define CONFIG_MII /* MII PHY management */ 454 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 455 #define CONFIG_TSEC1 1 456 #define CONFIG_TSEC1_NAME "eTSEC1" 457 #define CONFIG_TSEC2 1 458 #define CONFIG_TSEC2_NAME "eTSEC2" 459 460 #define TSEC1_PHY_ADDR 0 461 #define TSEC2_PHY_ADDR 1 462 463 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 464 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 465 466 #define TSEC1_PHYIDX 0 467 #define TSEC2_PHYIDX 0 468 469 #define CONFIG_ETHPRIME "eTSEC1" 470 471 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 472 473 /* TBI PHY configuration for SGMII mode */ 474 #define CONFIG_TSEC_TBICR_SETTINGS ( \ 475 TBICR_PHY_RESET \ 476 | TBICR_ANEG_ENABLE \ 477 | TBICR_FULL_DUPLEX \ 478 | TBICR_SPEED1_SET \ 479 ) 480 481 #endif /* CONFIG_TSEC_ENET */ 482 483 #ifdef CONFIG_MMC 484 #define CONFIG_DOS_PARTITION 485 #define CONFIG_FSL_ESDHC 486 #define CONFIG_GENERIC_MMC 487 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 488 #endif 489 490 #define CONFIG_USB_EHCI /* USB */ 491 #ifdef CONFIG_USB_EHCI 492 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 493 #define CONFIG_USB_EHCI_FSL 494 #define CONFIG_HAS_FSL_DR_USB 495 #endif 496 497 /* 498 * Environment 499 */ 500 #if defined(CONFIG_RAMBOOT_SDCARD) 501 #define CONFIG_ENV_IS_IN_MMC 502 #define CONFIG_FSL_FIXED_MMC_LOCATION 503 #define CONFIG_SYS_MMC_ENV_DEV 0 504 #define CONFIG_ENV_SIZE 0x2000 505 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 506 #define CONFIG_ENV_IS_IN_SPI_FLASH 507 #define CONFIG_ENV_SPI_BUS 0 508 #define CONFIG_ENV_SPI_CS 0 509 #define CONFIG_ENV_SPI_MAX_HZ 10000000 510 #define CONFIG_ENV_SPI_MODE 0 511 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 512 #define CONFIG_ENV_SECT_SIZE 0x10000 513 #define CONFIG_ENV_SIZE 0x2000 514 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) 515 #define CONFIG_ENV_IS_IN_NAND 516 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 517 #define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) 518 #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) 519 #elif defined(CONFIG_SYS_RAMBOOT) 520 #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ 521 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 522 #define CONFIG_ENV_SIZE 0x2000 523 #else 524 #define CONFIG_ENV_IS_IN_FLASH 525 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 526 #define CONFIG_ENV_SIZE 0x2000 527 #define CONFIG_ENV_SECT_SIZE 0x20000 528 #endif 529 530 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 531 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 532 533 /* 534 * Command line configuration. 535 */ 536 #define CONFIG_CMD_DATE 537 #define CONFIG_CMD_ERRATA 538 #define CONFIG_CMD_IRQ 539 #define CONFIG_CMD_REGINFO 540 541 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) 542 #define CONFIG_DOS_PARTITION 543 #endif 544 545 /* Hash command with SHA acceleration supported in hardware */ 546 #ifdef CONFIG_FSL_CAAM 547 #define CONFIG_CMD_HASH 548 #define CONFIG_SHA_HW_ACCEL 549 #endif 550 551 /* 552 * Miscellaneous configurable options 553 */ 554 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 555 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 556 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 557 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 558 559 #if defined(CONFIG_CMD_KGDB) 560 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 561 #else 562 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 563 #endif 564 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 565 /* Print Buffer Size */ 566 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 567 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 568 569 /* 570 * For booting Linux, the board info and command line data 571 * have to be in the first 64 MB of memory, since this is 572 * the maximum mapped by the Linux kernel during initialization. 573 */ 574 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ 575 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 576 577 #if defined(CONFIG_CMD_KGDB) 578 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 579 #endif 580 581 /* 582 * Dynamic MTD Partition support with mtdparts 583 */ 584 #ifndef CONFIG_SYS_NO_FLASH 585 #define CONFIG_MTD_DEVICE 586 #define CONFIG_MTD_PARTITIONS 587 #define CONFIG_CMD_MTDPARTS 588 #define CONFIG_FLASH_CFI_MTD 589 #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash," 590 #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \ 591 "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \ 592 "8m(kernel),512k(dtb),-(fs)" 593 #endif 594 /* 595 * Environment Configuration 596 */ 597 598 #if defined(CONFIG_TSEC_ENET) 599 #define CONFIG_HAS_ETH0 600 #define CONFIG_HAS_ETH1 601 #endif 602 603 #define CONFIG_HOSTNAME BSC9132qds 604 #define CONFIG_ROOTPATH "/opt/nfsroot" 605 #define CONFIG_BOOTFILE "uImage" 606 #define CONFIG_UBOOTPATH "u-boot.bin" 607 608 #define CONFIG_BAUDRATE 115200 609 610 #ifdef CONFIG_SDCARD 611 #define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" 612 #else 613 #define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" 614 #endif 615 616 #define CONFIG_EXTRA_ENV_SETTINGS \ 617 "netdev=eth0\0" \ 618 "uboot=" CONFIG_UBOOTPATH "\0" \ 619 "loadaddr=1000000\0" \ 620 "bootfile=uImage\0" \ 621 "consoledev=ttyS0\0" \ 622 "ramdiskaddr=2000000\0" \ 623 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 624 "fdtaddr=1e00000\0" \ 625 "fdtfile=bsc9132qds.dtb\0" \ 626 "bdev=sda1\0" \ 627 CONFIG_DEF_HWCONFIG\ 628 "othbootargs=mem=880M ramdisk_size=600000 " \ 629 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ 630 "isolcpus=0\0" \ 631 "usbext2boot=setenv bootargs root=/dev/ram rw " \ 632 "console=$consoledev,$baudrate $othbootargs; " \ 633 "usb start;" \ 634 "ext2load usb 0:4 $loadaddr $bootfile;" \ 635 "ext2load usb 0:4 $fdtaddr $fdtfile;" \ 636 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ 637 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ 638 "debug_halt_off=mw ff7e0e30 0xf0000000;" 639 640 #define CONFIG_NFSBOOTCOMMAND \ 641 "setenv bootargs root=/dev/nfs rw " \ 642 "nfsroot=$serverip:$rootpath " \ 643 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 644 "console=$consoledev,$baudrate $othbootargs;" \ 645 "tftp $loadaddr $bootfile;" \ 646 "tftp $fdtaddr $fdtfile;" \ 647 "bootm $loadaddr - $fdtaddr" 648 649 #define CONFIG_HDBOOT \ 650 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ 651 "console=$consoledev,$baudrate $othbootargs;" \ 652 "usb start;" \ 653 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ 654 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ 655 "bootm $loadaddr - $fdtaddr" 656 657 #define CONFIG_RAMBOOTCOMMAND \ 658 "setenv bootargs root=/dev/ram rw " \ 659 "console=$consoledev,$baudrate $othbootargs; " \ 660 "tftp $ramdiskaddr $ramdiskfile;" \ 661 "tftp $loadaddr $bootfile;" \ 662 "tftp $fdtaddr $fdtfile;" \ 663 "bootm $loadaddr $ramdiskaddr $fdtaddr" 664 665 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 666 667 #include <asm/fsl_secure_boot.h> 668 669 #endif /* __CONFIG_H */ 670