1 /* 2 * Copyright 2011-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_DISPLAY_BOARDINFO 11 12 /* 13 * B4860 QDS board configuration file 14 */ 15 #define CONFIG_B4860QDS 16 17 #ifdef CONFIG_RAMBOOT_PBL 18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg 19 #define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg 20 #ifndef CONFIG_NAND 21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 23 #else 24 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT 25 #define CONFIG_SPL_SERIAL_SUPPORT 26 #define CONFIG_SPL_FLUSH_IMAGE 27 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 28 #define CONFIG_SPL_LIBGENERIC_SUPPORT 29 #define CONFIG_SPL_LIBCOMMON_SUPPORT 30 #define CONFIG_FSL_LAW /* Use common FSL init code */ 31 #define CONFIG_SYS_TEXT_BASE 0x00201000 32 #define CONFIG_SPL_TEXT_BASE 0xFFFD8000 33 #define CONFIG_SPL_PAD_TO 0x40000 34 #define CONFIG_SPL_MAX_SIZE 0x28000 35 #define RESET_VECTOR_OFFSET 0x27FFC 36 #define BOOT_PAGE_OFFSET 0x27000 37 #define CONFIG_SPL_NAND_SUPPORT 38 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) 39 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 40 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 41 #define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) 42 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" 43 #define CONFIG_SPL_NAND_BOOT 44 #ifdef CONFIG_SPL_BUILD 45 #define CONFIG_SPL_SKIP_RELOCATE 46 #define CONFIG_SPL_COMMON_INIT_DDR 47 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 48 #define CONFIG_SYS_NO_FLASH 49 #endif 50 #endif 51 #endif 52 53 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 54 /* Set 1M boot space */ 55 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 56 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 57 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 58 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 59 #define CONFIG_SYS_NO_FLASH 60 #endif 61 62 /* High Level Configuration Options */ 63 #define CONFIG_BOOKE 64 #define CONFIG_E500 /* BOOKE e500 family */ 65 #define CONFIG_E500MC /* BOOKE e500mc family */ 66 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 67 #define CONFIG_MP /* support multiple processors */ 68 69 #ifndef CONFIG_SYS_TEXT_BASE 70 #define CONFIG_SYS_TEXT_BASE 0xeff40000 71 #endif 72 73 #ifndef CONFIG_RESET_VECTOR_ADDRESS 74 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 75 #endif 76 77 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 78 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 79 #define CONFIG_FSL_IFC /* Enable IFC Support */ 80 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 81 #define CONFIG_PCI /* Enable PCI/PCIE */ 82 #define CONFIG_PCIE1 /* PCIE controller 1 */ 83 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 84 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 85 86 #ifndef CONFIG_PPC_B4420 87 #define CONFIG_SYS_SRIO 88 #define CONFIG_SRIO1 /* SRIO port 1 */ 89 #define CONFIG_SRIO2 /* SRIO port 2 */ 90 #define CONFIG_SRIO_PCIE_BOOT_MASTER 91 #endif 92 93 #define CONFIG_FSL_LAW /* Use common FSL init code */ 94 95 /* I2C bus multiplexer */ 96 #define I2C_MUX_PCA_ADDR 0x77 97 98 /* VSC Crossbar switches */ 99 #define CONFIG_VSC_CROSSBAR 100 #define I2C_CH_DEFAULT 0x8 101 #define I2C_CH_VSC3316 0xc 102 #define I2C_CH_VSC3308 0xd 103 104 #define VSC3316_TX_ADDRESS 0x70 105 #define VSC3316_RX_ADDRESS 0x71 106 #define VSC3308_TX_ADDRESS 0x02 107 #define VSC3308_RX_ADDRESS 0x03 108 109 /* IDT clock synthesizers */ 110 #define CONFIG_IDT8T49N222A 111 #define I2C_CH_IDT 0x9 112 113 #define IDT_SERDES1_ADDRESS 0x6E 114 #define IDT_SERDES2_ADDRESS 0x6C 115 116 /* Voltage monitor on channel 2*/ 117 #define I2C_MUX_CH_VOL_MONITOR 0xa 118 #define I2C_VOL_MONITOR_ADDR 0x40 119 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 120 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1 121 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3 122 123 #define CONFIG_ZM7300 124 #define I2C_MUX_CH_DPM 0xa 125 #define I2C_DPM_ADDR 0x28 126 127 #define CONFIG_ENV_OVERWRITE 128 129 #ifdef CONFIG_SYS_NO_FLASH 130 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 131 #define CONFIG_ENV_IS_NOWHERE 132 #endif 133 #else 134 #define CONFIG_FLASH_CFI_DRIVER 135 #define CONFIG_SYS_FLASH_CFI 136 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 137 #endif 138 139 #if defined(CONFIG_SPIFLASH) 140 #define CONFIG_SYS_EXTRA_ENV_RELOC 141 #define CONFIG_ENV_IS_IN_SPI_FLASH 142 #define CONFIG_ENV_SPI_BUS 0 143 #define CONFIG_ENV_SPI_CS 0 144 #define CONFIG_ENV_SPI_MAX_HZ 10000000 145 #define CONFIG_ENV_SPI_MODE 0 146 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 147 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 148 #define CONFIG_ENV_SECT_SIZE 0x10000 149 #elif defined(CONFIG_SDCARD) 150 #define CONFIG_SYS_EXTRA_ENV_RELOC 151 #define CONFIG_ENV_IS_IN_MMC 152 #define CONFIG_SYS_MMC_ENV_DEV 0 153 #define CONFIG_ENV_SIZE 0x2000 154 #define CONFIG_ENV_OFFSET (512 * 1097) 155 #elif defined(CONFIG_NAND) 156 #define CONFIG_SYS_EXTRA_ENV_RELOC 157 #define CONFIG_ENV_IS_IN_NAND 158 #define CONFIG_ENV_SIZE 0x2000 159 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) 160 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 161 #define CONFIG_ENV_IS_IN_REMOTE 162 #define CONFIG_ENV_ADDR 0xffe20000 163 #define CONFIG_ENV_SIZE 0x2000 164 #elif defined(CONFIG_ENV_IS_NOWHERE) 165 #define CONFIG_ENV_SIZE 0x2000 166 #else 167 #define CONFIG_ENV_IS_IN_FLASH 168 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 169 #define CONFIG_ENV_SIZE 0x2000 170 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 171 #endif 172 173 #ifndef __ASSEMBLY__ 174 unsigned long get_board_sys_clk(void); 175 unsigned long get_board_ddr_clk(void); 176 #endif 177 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 178 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() 179 180 /* 181 * These can be toggled for performance analysis, otherwise use default. 182 */ 183 #define CONFIG_SYS_CACHE_STASHING 184 #define CONFIG_BTB /* toggle branch predition */ 185 #define CONFIG_DDR_ECC 186 #ifdef CONFIG_DDR_ECC 187 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 188 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 189 #endif 190 191 #define CONFIG_ENABLE_36BIT_PHYS 192 193 #ifdef CONFIG_PHYS_64BIT 194 #define CONFIG_ADDR_MAP 195 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 196 #endif 197 198 #if 0 199 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 200 #endif 201 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 202 #define CONFIG_SYS_MEMTEST_END 0x00400000 203 #define CONFIG_SYS_ALT_MEMTEST 204 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 205 206 /* 207 * Config the L3 Cache as L3 SRAM 208 */ 209 #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 210 #define CONFIG_SYS_L3_SIZE 256 << 10 211 #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) 212 #ifdef CONFIG_NAND 213 #define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) 214 #endif 215 #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) 216 #define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) 217 #define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) 218 #define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10) 219 220 #ifdef CONFIG_PHYS_64BIT 221 #define CONFIG_SYS_DCSRBAR 0xf0000000 222 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 223 #endif 224 225 /* EEPROM */ 226 #define CONFIG_ID_EEPROM 227 #define CONFIG_SYS_I2C_EEPROM_NXID 228 #define CONFIG_SYS_EEPROM_BUS_NUM 0 229 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 230 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 231 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 232 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 233 234 /* 235 * DDR Setup 236 */ 237 #define CONFIG_VERY_BIG_RAM 238 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 239 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 240 241 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ 242 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 243 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 244 245 #define CONFIG_DDR_SPD 246 #define CONFIG_SYS_DDR_RAW_TIMING 247 #define CONFIG_SYS_FSL_DDR3 248 #ifndef CONFIG_SPL_BUILD 249 #define CONFIG_FSL_DDR_INTERACTIVE 250 #endif 251 252 #define CONFIG_SYS_SPD_BUS_NUM 0 253 #define SPD_EEPROM_ADDRESS1 0x51 254 #define SPD_EEPROM_ADDRESS2 0x53 255 256 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 257 #define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ 258 259 /* 260 * IFC Definitions 261 */ 262 #define CONFIG_SYS_FLASH_BASE 0xe0000000 263 #ifdef CONFIG_PHYS_64BIT 264 #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) 265 #else 266 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 267 #endif 268 269 #define CONFIG_SYS_NOR0_CSPR_EXT (0xf) 270 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ 271 + 0x8000000) | \ 272 CSPR_PORT_SIZE_16 | \ 273 CSPR_MSEL_NOR | \ 274 CSPR_V) 275 #define CONFIG_SYS_NOR1_CSPR_EXT (0xf) 276 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ 277 CSPR_PORT_SIZE_16 | \ 278 CSPR_MSEL_NOR | \ 279 CSPR_V) 280 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) 281 /* NOR Flash Timing Params */ 282 #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) 283 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ 284 FTIM0_NOR_TEADC(0x04) | \ 285 FTIM0_NOR_TEAHC(0x20)) 286 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ 287 FTIM1_NOR_TRAD_NOR(0x1A) |\ 288 FTIM1_NOR_TSEQRAD_NOR(0x13)) 289 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ 290 FTIM2_NOR_TCH(0x0E) | \ 291 FTIM2_NOR_TWPH(0x0E) | \ 292 FTIM2_NOR_TWP(0x1c)) 293 #define CONFIG_SYS_NOR_FTIM3 0x0 294 295 #define CONFIG_SYS_FLASH_QUIET_TEST 296 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 297 298 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 299 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 300 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 301 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 302 303 #define CONFIG_SYS_FLASH_EMPTY_INFO 304 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ 305 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 306 307 #define CONFIG_FSL_QIXIS /* use common QIXIS code */ 308 #define CONFIG_FSL_QIXIS_V2 309 #define QIXIS_BASE 0xffdf0000 310 #ifdef CONFIG_PHYS_64BIT 311 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) 312 #else 313 #define QIXIS_BASE_PHYS QIXIS_BASE 314 #endif 315 #define QIXIS_LBMAP_SWITCH 0x01 316 #define QIXIS_LBMAP_MASK 0x0f 317 #define QIXIS_LBMAP_SHIFT 0 318 #define QIXIS_LBMAP_DFLTBANK 0x00 319 #define QIXIS_LBMAP_ALTBANK 0x02 320 #define QIXIS_RST_CTL_RESET 0x31 321 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 322 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 323 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 324 325 #define CONFIG_SYS_CSPR3_EXT (0xf) 326 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ 327 | CSPR_PORT_SIZE_8 \ 328 | CSPR_MSEL_GPCM \ 329 | CSPR_V) 330 #define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) 331 #define CONFIG_SYS_CSOR3 0x0 332 /* QIXIS Timing parameters for IFC CS3 */ 333 #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ 334 FTIM0_GPCM_TEADC(0x0e) | \ 335 FTIM0_GPCM_TEAHC(0x0e)) 336 #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ 337 FTIM1_GPCM_TRAD(0x1f)) 338 #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ 339 FTIM2_GPCM_TCH(0x8) | \ 340 FTIM2_GPCM_TWP(0x1f)) 341 #define CONFIG_SYS_CS3_FTIM3 0x0 342 343 /* NAND Flash on IFC */ 344 #define CONFIG_NAND_FSL_IFC 345 #define CONFIG_SYS_NAND_MAX_ECCPOS 256 346 #define CONFIG_SYS_NAND_MAX_OOBFREE 2 347 #define CONFIG_SYS_NAND_BASE 0xff800000 348 #ifdef CONFIG_PHYS_64BIT 349 #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) 350 #else 351 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 352 #endif 353 354 #define CONFIG_SYS_NAND_CSPR_EXT (0xf) 355 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 356 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ 357 | CSPR_MSEL_NAND /* MSEL = NAND */ \ 358 | CSPR_V) 359 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) 360 361 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ 362 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ 363 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ 364 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ 365 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ 366 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ 367 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ 368 369 #define CONFIG_SYS_NAND_ONFI_DETECTION 370 371 /* ONFI NAND Flash mode0 Timing Params */ 372 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ 373 FTIM0_NAND_TWP(0x18) | \ 374 FTIM0_NAND_TWCHT(0x07) | \ 375 FTIM0_NAND_TWH(0x0a)) 376 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ 377 FTIM1_NAND_TWBE(0x39) | \ 378 FTIM1_NAND_TRR(0x0e) | \ 379 FTIM1_NAND_TRP(0x18)) 380 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ 381 FTIM2_NAND_TREH(0x0a) | \ 382 FTIM2_NAND_TWHRE(0x1e)) 383 #define CONFIG_SYS_NAND_FTIM3 0x0 384 385 #define CONFIG_SYS_NAND_DDR_LAW 11 386 387 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 388 #define CONFIG_SYS_MAX_NAND_DEVICE 1 389 #define CONFIG_CMD_NAND 390 391 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 392 393 #if defined(CONFIG_NAND) 394 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT 395 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR 396 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK 397 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR 398 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 399 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 400 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 401 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 402 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT 403 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR 404 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK 405 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR 406 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 407 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 408 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 409 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 410 #else 411 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT 412 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR 413 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK 414 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR 415 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 416 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 417 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 418 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 419 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT 420 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR 421 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK 422 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR 423 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 424 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 425 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 426 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 427 #endif 428 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT 429 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR 430 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK 431 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR 432 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 433 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 434 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 435 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 436 437 #ifdef CONFIG_SPL_BUILD 438 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE 439 #else 440 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 441 #endif 442 443 #if defined(CONFIG_RAMBOOT_PBL) 444 #define CONFIG_SYS_RAMBOOT 445 #endif 446 447 #define CONFIG_BOARD_EARLY_INIT_R 448 #define CONFIG_MISC_INIT_R 449 450 #define CONFIG_HWCONFIG 451 452 /* define to use L1 as initial stack */ 453 #define CONFIG_L1_INIT_RAM 454 #define CONFIG_SYS_INIT_RAM_LOCK 455 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 456 #ifdef CONFIG_PHYS_64BIT 457 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 458 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 459 /* The assembler doesn't like typecast */ 460 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 461 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 462 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 463 #else 464 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ 465 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 466 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 467 #endif 468 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 469 470 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 471 GENERATED_GBL_DATA_SIZE) 472 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 473 474 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 475 #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) 476 477 /* Serial Port - controlled on board with jumper J8 478 * open - index 2 479 * shorted - index 1 480 */ 481 #define CONFIG_CONS_INDEX 1 482 #define CONFIG_SYS_NS16550_SERIAL 483 #define CONFIG_SYS_NS16550_REG_SIZE 1 484 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 485 486 #define CONFIG_SYS_BAUDRATE_TABLE \ 487 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 488 489 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 490 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 491 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 492 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 493 #ifndef CONFIG_SPL_BUILD 494 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ 495 #endif 496 497 /* I2C */ 498 #define CONFIG_SYS_I2C 499 #define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ 500 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ 501 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 502 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ 503 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 504 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 505 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 506 507 /* 508 * RTC configuration 509 */ 510 #define RTC 511 #define CONFIG_RTC_DS3231 1 512 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 513 514 /* 515 * RapidIO 516 */ 517 #ifdef CONFIG_SYS_SRIO 518 #ifdef CONFIG_SRIO1 519 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 520 #ifdef CONFIG_PHYS_64BIT 521 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 522 #else 523 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 524 #endif 525 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 526 #endif 527 528 #ifdef CONFIG_SRIO2 529 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 530 #ifdef CONFIG_PHYS_64BIT 531 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 532 #else 533 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 534 #endif 535 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 536 #endif 537 #endif 538 539 /* 540 * for slave u-boot IMAGE instored in master memory space, 541 * PHYS must be aligned based on the SIZE 542 */ 543 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 544 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 545 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 546 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 547 /* 548 * for slave UCODE and ENV instored in master memory space, 549 * PHYS must be aligned based on the SIZE 550 */ 551 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 552 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 553 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 554 555 /* slave core release by master*/ 556 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 557 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 558 559 /* 560 * SRIO_PCIE_BOOT - SLAVE 561 */ 562 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 563 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 564 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 565 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 566 #endif 567 568 /* 569 * eSPI - Enhanced SPI 570 */ 571 #define CONFIG_SF_DEFAULT_SPEED 10000000 572 #define CONFIG_SF_DEFAULT_MODE 0 573 574 /* 575 * MAPLE 576 */ 577 #ifdef CONFIG_PHYS_64BIT 578 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull 579 #else 580 #define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 581 #endif 582 583 /* 584 * General PCI 585 * Memory space is mapped 1-1, but I/O space must start from 0. 586 */ 587 588 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 589 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 590 #ifdef CONFIG_PHYS_64BIT 591 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 592 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 593 #else 594 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 595 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 596 #endif 597 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 598 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 599 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 600 #ifdef CONFIG_PHYS_64BIT 601 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 602 #else 603 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 604 #endif 605 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 606 607 /* Qman/Bman */ 608 #ifndef CONFIG_NOBQFMAN 609 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 610 #define CONFIG_SYS_BMAN_NUM_PORTALS 25 611 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 612 #ifdef CONFIG_PHYS_64BIT 613 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 614 #else 615 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 616 #endif 617 #define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 618 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 619 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 620 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 621 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 622 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 623 CONFIG_SYS_BMAN_CENA_SIZE) 624 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 625 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 626 #define CONFIG_SYS_QMAN_NUM_PORTALS 25 627 #define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 628 #ifdef CONFIG_PHYS_64BIT 629 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull 630 #else 631 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 632 #endif 633 #define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 634 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 635 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 636 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 637 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 638 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 639 CONFIG_SYS_QMAN_CENA_SIZE) 640 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 641 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 642 643 #define CONFIG_SYS_DPAA_FMAN 644 645 #define CONFIG_SYS_DPAA_RMAN 646 647 /* Default address of microcode for the Linux Fman driver */ 648 #if defined(CONFIG_SPIFLASH) 649 /* 650 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 651 * env, so we got 0x110000. 652 */ 653 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 654 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 655 #elif defined(CONFIG_SDCARD) 656 /* 657 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 658 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 659 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 660 */ 661 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 662 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) 663 #elif defined(CONFIG_NAND) 664 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 665 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) 666 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 667 /* 668 * Slave has no ucode locally, it can fetch this from remote. When implementing 669 * in two corenet boards, slave's ucode could be stored in master's memory 670 * space, the address can be mapped from slave TLB->slave LAW-> 671 * slave SRIO or PCIE outbound window->master inbound window-> 672 * master LAW->the ucode address in master's memory space. 673 */ 674 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 675 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 676 #else 677 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 678 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 679 #endif 680 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 681 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 682 #endif /* CONFIG_NOBQFMAN */ 683 684 #ifdef CONFIG_SYS_DPAA_FMAN 685 #define CONFIG_FMAN_ENET 686 #define CONFIG_PHYLIB_10G 687 #define CONFIG_PHY_VITESSE 688 #define CONFIG_PHY_TERANETICS 689 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C 690 #define SGMII_CARD_PORT2_PHY_ADDR 0x10 691 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E 692 #define SGMII_CARD_PORT4_PHY_ADDR 0x11 693 #endif 694 695 #ifdef CONFIG_PCI 696 #define CONFIG_PCI_INDIRECT_BRIDGE 697 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 698 699 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 700 #define CONFIG_DOS_PARTITION 701 #endif /* CONFIG_PCI */ 702 703 #ifdef CONFIG_FMAN_ENET 704 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 705 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 706 707 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */ 708 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ 709 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ 710 711 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c 712 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d 713 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e 714 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f 715 716 #define CONFIG_MII /* MII PHY management */ 717 #define CONFIG_ETHPRIME "FM1@DTSEC1" 718 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 719 #endif 720 721 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR 722 723 /* 724 * Environment 725 */ 726 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 727 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 728 729 /* 730 * Command line configuration. 731 */ 732 #define CONFIG_CMD_DATE 733 #define CONFIG_CMD_EEPROM 734 #define CONFIG_CMD_ERRATA 735 #define CONFIG_CMD_IRQ 736 #define CONFIG_CMD_REGINFO 737 738 #ifdef CONFIG_PCI 739 #define CONFIG_CMD_PCI 740 #endif 741 742 /* Hash command with SHA acceleration supported in hardware */ 743 #ifdef CONFIG_FSL_CAAM 744 #define CONFIG_CMD_HASH 745 #define CONFIG_SHA_HW_ACCEL 746 #endif 747 748 /* 749 * USB 750 */ 751 #define CONFIG_HAS_FSL_DR_USB 752 753 #ifdef CONFIG_HAS_FSL_DR_USB 754 #define CONFIG_USB_EHCI 755 756 #ifdef CONFIG_USB_EHCI 757 #define CONFIG_USB_EHCI_FSL 758 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 759 #endif 760 #endif 761 762 /* 763 * Miscellaneous configurable options 764 */ 765 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 766 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 767 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 768 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 769 #ifdef CONFIG_CMD_KGDB 770 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 771 #else 772 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 773 #endif 774 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 775 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 776 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ 777 778 /* 779 * For booting Linux, the board info and command line data 780 * have to be in the first 64 MB of memory, since this is 781 * the maximum mapped by the Linux kernel during initialization. 782 */ 783 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ 784 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 785 786 #ifdef CONFIG_CMD_KGDB 787 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 788 #endif 789 790 /* 791 * Environment Configuration 792 */ 793 #define CONFIG_ROOTPATH "/opt/nfsroot" 794 #define CONFIG_BOOTFILE "uImage" 795 #define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ 796 797 /* default location for tftp and bootm */ 798 #define CONFIG_LOADADDR 1000000 799 800 801 #define CONFIG_BAUDRATE 115200 802 803 #define __USB_PHY_TYPE ulpi 804 805 #ifdef CONFIG_PPC_B4860 806 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ 807 "bank_intlv=cs0_cs1;" \ 808 "en_cpc:cpc2;" 809 #else 810 #define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" 811 #endif 812 813 #define CONFIG_EXTRA_ENV_SETTINGS \ 814 HWCONFIG \ 815 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 816 "netdev=eth0\0" \ 817 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 818 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 819 "tftpflash=tftpboot $loadaddr $uboot && " \ 820 "protect off $ubootaddr +$filesize && " \ 821 "erase $ubootaddr +$filesize && " \ 822 "cp.b $loadaddr $ubootaddr $filesize && " \ 823 "protect on $ubootaddr +$filesize && " \ 824 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 825 "consoledev=ttyS0\0" \ 826 "ramdiskaddr=2000000\0" \ 827 "ramdiskfile=b4860qds/ramdisk.uboot\0" \ 828 "fdtaddr=1e00000\0" \ 829 "fdtfile=b4860qds/b4860qds.dtb\0" \ 830 "bdev=sda3\0" 831 832 /* For emulation this causes u-boot to jump to the start of the proof point 833 app code automatically */ 834 #define CONFIG_PROOF_POINTS \ 835 "setenv bootargs root=/dev/$bdev rw " \ 836 "console=$consoledev,$baudrate $othbootargs;" \ 837 "cpu 1 release 0x29000000 - - -;" \ 838 "cpu 2 release 0x29000000 - - -;" \ 839 "cpu 3 release 0x29000000 - - -;" \ 840 "cpu 4 release 0x29000000 - - -;" \ 841 "cpu 5 release 0x29000000 - - -;" \ 842 "cpu 6 release 0x29000000 - - -;" \ 843 "cpu 7 release 0x29000000 - - -;" \ 844 "go 0x29000000" 845 846 #define CONFIG_HVBOOT \ 847 "setenv bootargs config-addr=0x60000000; " \ 848 "bootm 0x01000000 - 0x00f00000" 849 850 #define CONFIG_ALU \ 851 "setenv bootargs root=/dev/$bdev rw " \ 852 "console=$consoledev,$baudrate $othbootargs;" \ 853 "cpu 1 release 0x01000000 - - -;" \ 854 "cpu 2 release 0x01000000 - - -;" \ 855 "cpu 3 release 0x01000000 - - -;" \ 856 "cpu 4 release 0x01000000 - - -;" \ 857 "cpu 5 release 0x01000000 - - -;" \ 858 "cpu 6 release 0x01000000 - - -;" \ 859 "cpu 7 release 0x01000000 - - -;" \ 860 "go 0x01000000" 861 862 #define CONFIG_LINUX \ 863 "setenv bootargs root=/dev/ram rw " \ 864 "console=$consoledev,$baudrate $othbootargs;" \ 865 "setenv ramdiskaddr 0x02000000;" \ 866 "setenv fdtaddr 0x01e00000;" \ 867 "setenv loadaddr 0x1000000;" \ 868 "bootm $loadaddr $ramdiskaddr $fdtaddr" 869 870 #define CONFIG_HDBOOT \ 871 "setenv bootargs root=/dev/$bdev rw " \ 872 "console=$consoledev,$baudrate $othbootargs;" \ 873 "tftp $loadaddr $bootfile;" \ 874 "tftp $fdtaddr $fdtfile;" \ 875 "bootm $loadaddr - $fdtaddr" 876 877 #define CONFIG_NFSBOOTCOMMAND \ 878 "setenv bootargs root=/dev/nfs rw " \ 879 "nfsroot=$serverip:$rootpath " \ 880 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 881 "console=$consoledev,$baudrate $othbootargs;" \ 882 "tftp $loadaddr $bootfile;" \ 883 "tftp $fdtaddr $fdtfile;" \ 884 "bootm $loadaddr - $fdtaddr" 885 886 #define CONFIG_RAMBOOTCOMMAND \ 887 "setenv bootargs root=/dev/ram rw " \ 888 "console=$consoledev,$baudrate $othbootargs;" \ 889 "tftp $ramdiskaddr $ramdiskfile;" \ 890 "tftp $loadaddr $bootfile;" \ 891 "tftp $fdtaddr $fdtfile;" \ 892 "bootm $loadaddr $ramdiskaddr $fdtaddr" 893 894 #define CONFIG_BOOTCOMMAND CONFIG_LINUX 895 896 #include <asm/fsl_secure_boot.h> 897 898 #endif /* __CONFIG_H */ 899