1*5614e71bSYork Sun /* 2*5614e71bSYork Sun * Copyright 2008 Freescale Semiconductor, Inc. 3*5614e71bSYork Sun * 4*5614e71bSYork Sun * This program is free software; you can redistribute it and/or 5*5614e71bSYork Sun * modify it under the terms of the GNU General Public License 6*5614e71bSYork Sun * Version 2 as published by the Free Software Foundation. 7*5614e71bSYork Sun */ 8*5614e71bSYork Sun 9*5614e71bSYork Sun #ifndef COMMON_TIMING_PARAMS_H 10*5614e71bSYork Sun #define COMMON_TIMING_PARAMS_H 11*5614e71bSYork Sun 12*5614e71bSYork Sun typedef struct { 13*5614e71bSYork Sun /* parameters to constrict */ 14*5614e71bSYork Sun 15*5614e71bSYork Sun unsigned int tckmin_x_ps; 16*5614e71bSYork Sun unsigned int tckmax_ps; 17*5614e71bSYork Sun unsigned int tckmax_max_ps; 18*5614e71bSYork Sun unsigned int trcd_ps; 19*5614e71bSYork Sun unsigned int trp_ps; 20*5614e71bSYork Sun unsigned int tras_ps; 21*5614e71bSYork Sun 22*5614e71bSYork Sun unsigned int twr_ps; /* maximum = 63750 ps */ 23*5614e71bSYork Sun unsigned int twtr_ps; /* maximum = 63750 ps */ 24*5614e71bSYork Sun unsigned int trfc_ps; /* maximum = 255 ns + 256 ns + .75 ns 25*5614e71bSYork Sun = 511750 ps */ 26*5614e71bSYork Sun 27*5614e71bSYork Sun unsigned int trrd_ps; /* maximum = 63750 ps */ 28*5614e71bSYork Sun unsigned int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ 29*5614e71bSYork Sun 30*5614e71bSYork Sun unsigned int refresh_rate_ps; 31*5614e71bSYork Sun unsigned int extended_op_srt; 32*5614e71bSYork Sun 33*5614e71bSYork Sun unsigned int tis_ps; /* byte 32, spd->ca_setup */ 34*5614e71bSYork Sun unsigned int tih_ps; /* byte 33, spd->ca_hold */ 35*5614e71bSYork Sun unsigned int tds_ps; /* byte 34, spd->data_setup */ 36*5614e71bSYork Sun unsigned int tdh_ps; /* byte 35, spd->data_hold */ 37*5614e71bSYork Sun unsigned int trtp_ps; /* byte 38, spd->trtp */ 38*5614e71bSYork Sun unsigned int tdqsq_max_ps; /* byte 44, spd->tdqsq */ 39*5614e71bSYork Sun unsigned int tqhs_ps; /* byte 45, spd->tqhs */ 40*5614e71bSYork Sun 41*5614e71bSYork Sun unsigned int ndimms_present; 42*5614e71bSYork Sun unsigned int lowest_common_SPD_caslat; 43*5614e71bSYork Sun unsigned int highest_common_derated_caslat; 44*5614e71bSYork Sun unsigned int additive_latency; 45*5614e71bSYork Sun unsigned int all_dimms_burst_lengths_bitmask; 46*5614e71bSYork Sun unsigned int all_dimms_registered; 47*5614e71bSYork Sun unsigned int all_dimms_unbuffered; 48*5614e71bSYork Sun unsigned int all_dimms_ecc_capable; 49*5614e71bSYork Sun 50*5614e71bSYork Sun unsigned long long total_mem; 51*5614e71bSYork Sun unsigned long long base_address; 52*5614e71bSYork Sun 53*5614e71bSYork Sun /* DDR3 RDIMM */ 54*5614e71bSYork Sun unsigned char rcw[16]; /* Register Control Word 0-15 */ 55*5614e71bSYork Sun } common_timing_params_t; 56*5614e71bSYork Sun 57*5614e71bSYork Sun #endif 58