xref: /rk3399_rockchip-uboot/include/atmel_lcdc.h (revision 39cf480484fcce5c04a590ee1c30be0c17b02c34)
1*39cf4804SStelian Pop /*
2*39cf4804SStelian Pop  *  Header file for AT91/AT32 LCD Controller
3*39cf4804SStelian Pop  *
4*39cf4804SStelian Pop  *  Data structure and register user interface
5*39cf4804SStelian Pop  *
6*39cf4804SStelian Pop  *  Copyright (C) 2007 Atmel Corporation
7*39cf4804SStelian Pop  *
8*39cf4804SStelian Pop  * This program is free software; you can redistribute it and/or modify
9*39cf4804SStelian Pop  * it under the terms of the GNU General Public License as published by
10*39cf4804SStelian Pop  * the Free Software Foundation; either version 2 of the License, or
11*39cf4804SStelian Pop  * (at your option) any later version.
12*39cf4804SStelian Pop  *
13*39cf4804SStelian Pop  * This program is distributed in the hope that it will be useful,
14*39cf4804SStelian Pop  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15*39cf4804SStelian Pop  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16*39cf4804SStelian Pop  * GNU General Public License for more details.
17*39cf4804SStelian Pop  *
18*39cf4804SStelian Pop  * You should have received a copy of the GNU General Public License
19*39cf4804SStelian Pop  * along with this program; if not, write to the Free Software
20*39cf4804SStelian Pop  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
21*39cf4804SStelian Pop  */
22*39cf4804SStelian Pop #ifndef __ATMEL_LCDC_H__
23*39cf4804SStelian Pop #define __ATMEL_LCDC_H__
24*39cf4804SStelian Pop 
25*39cf4804SStelian Pop #define ATMEL_LCDC_DMABADDR1	0x00
26*39cf4804SStelian Pop #define ATMEL_LCDC_DMABADDR2	0x04
27*39cf4804SStelian Pop #define ATMEL_LCDC_DMAFRMPT1	0x08
28*39cf4804SStelian Pop #define ATMEL_LCDC_DMAFRMPT2	0x0c
29*39cf4804SStelian Pop #define ATMEL_LCDC_DMAFRMADD1	0x10
30*39cf4804SStelian Pop #define ATMEL_LCDC_DMAFRMADD2	0x14
31*39cf4804SStelian Pop 
32*39cf4804SStelian Pop #define ATMEL_LCDC_DMAFRMCFG	0x18
33*39cf4804SStelian Pop #define	ATMEL_LCDC_FRSIZE	(0x7fffff <<  0)
34*39cf4804SStelian Pop #define	ATMEL_LCDC_BLENGTH_OFFSET	24
35*39cf4804SStelian Pop #define	ATMEL_LCDC_BLENGTH	(0x7f     << ATMEL_LCDC_BLENGTH_OFFSET)
36*39cf4804SStelian Pop 
37*39cf4804SStelian Pop #define ATMEL_LCDC_DMACON	0x1c
38*39cf4804SStelian Pop #define	ATMEL_LCDC_DMAEN	(0x1 << 0)
39*39cf4804SStelian Pop #define	ATMEL_LCDC_DMARST	(0x1 << 1)
40*39cf4804SStelian Pop #define	ATMEL_LCDC_DMABUSY	(0x1 << 2)
41*39cf4804SStelian Pop #define		ATMEL_LCDC_DMAUPDT	(0x1 << 3)
42*39cf4804SStelian Pop #define		ATMEL_LCDC_DMA2DEN	(0x1 << 4)
43*39cf4804SStelian Pop 
44*39cf4804SStelian Pop #define ATMEL_LCDC_DMA2DCFG	0x20
45*39cf4804SStelian Pop #define		ATMEL_LCDC_ADDRINC_OFFSET	0
46*39cf4804SStelian Pop #define		ATMEL_LCDC_ADDRINC		(0xffff)
47*39cf4804SStelian Pop #define		ATMEL_LCDC_PIXELOFF_OFFSET	24
48*39cf4804SStelian Pop #define		ATMEL_LCDC_PIXELOFF		(0x1f << 24)
49*39cf4804SStelian Pop 
50*39cf4804SStelian Pop #define ATMEL_LCDC_LCDCON1	0x0800
51*39cf4804SStelian Pop #define	ATMEL_LCDC_BYPASS	(1     <<  0)
52*39cf4804SStelian Pop #define	ATMEL_LCDC_CLKVAL_OFFSET	12
53*39cf4804SStelian Pop #define	ATMEL_LCDC_CLKVAL	(0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
54*39cf4804SStelian Pop #define	ATMEL_LCDC_LINCNT	(0x7ff << 21)
55*39cf4804SStelian Pop 
56*39cf4804SStelian Pop #define ATMEL_LCDC_LCDCON2	0x0804
57*39cf4804SStelian Pop #define	ATMEL_LCDC_DISTYPE	(3 << 0)
58*39cf4804SStelian Pop #define		ATMEL_LCDC_DISTYPE_STNMONO	(0 << 0)
59*39cf4804SStelian Pop #define		ATMEL_LCDC_DISTYPE_STNCOLOR	(1 << 0)
60*39cf4804SStelian Pop #define		ATMEL_LCDC_DISTYPE_TFT		(2 << 0)
61*39cf4804SStelian Pop #define	ATMEL_LCDC_SCANMOD	(1 << 2)
62*39cf4804SStelian Pop #define		ATMEL_LCDC_SCANMOD_SINGLE	(0 << 2)
63*39cf4804SStelian Pop #define		ATMEL_LCDC_SCANMOD_DUAL		(1 << 2)
64*39cf4804SStelian Pop #define	ATMEL_LCDC_IFWIDTH	(3 << 3)
65*39cf4804SStelian Pop #define		ATMEL_LCDC_IFWIDTH_4		(0 << 3)
66*39cf4804SStelian Pop #define		ATMEL_LCDC_IFWIDTH_8		(1 << 3)
67*39cf4804SStelian Pop #define		ATMEL_LCDC_IFWIDTH_16		(2 << 3)
68*39cf4804SStelian Pop #define	ATMEL_LCDC_PIXELSIZE	(7 << 5)
69*39cf4804SStelian Pop #define		ATMEL_LCDC_PIXELSIZE_1		(0 << 5)
70*39cf4804SStelian Pop #define		ATMEL_LCDC_PIXELSIZE_2		(1 << 5)
71*39cf4804SStelian Pop #define		ATMEL_LCDC_PIXELSIZE_4		(2 << 5)
72*39cf4804SStelian Pop #define		ATMEL_LCDC_PIXELSIZE_8		(3 << 5)
73*39cf4804SStelian Pop #define		ATMEL_LCDC_PIXELSIZE_16		(4 << 5)
74*39cf4804SStelian Pop #define		ATMEL_LCDC_PIXELSIZE_24		(5 << 5)
75*39cf4804SStelian Pop #define		ATMEL_LCDC_PIXELSIZE_32		(6 << 5)
76*39cf4804SStelian Pop #define	ATMEL_LCDC_INVVD	(1 << 8)
77*39cf4804SStelian Pop #define		ATMEL_LCDC_INVVD_NORMAL		(0 << 8)
78*39cf4804SStelian Pop #define		ATMEL_LCDC_INVVD_INVERTED	(1 << 8)
79*39cf4804SStelian Pop #define	ATMEL_LCDC_INVFRAME	(1 << 9 )
80*39cf4804SStelian Pop #define		ATMEL_LCDC_INVFRAME_NORMAL	(0 << 9)
81*39cf4804SStelian Pop #define		ATMEL_LCDC_INVFRAME_INVERTED	(1 << 9)
82*39cf4804SStelian Pop #define	ATMEL_LCDC_INVLINE	(1 << 10)
83*39cf4804SStelian Pop #define		ATMEL_LCDC_INVLINE_NORMAL	(0 << 10)
84*39cf4804SStelian Pop #define		ATMEL_LCDC_INVLINE_INVERTED	(1 << 10)
85*39cf4804SStelian Pop #define	ATMEL_LCDC_INVCLK	(1 << 11)
86*39cf4804SStelian Pop #define		ATMEL_LCDC_INVCLK_NORMAL	(0 << 11)
87*39cf4804SStelian Pop #define		ATMEL_LCDC_INVCLK_INVERTED	(1 << 11)
88*39cf4804SStelian Pop #define	ATMEL_LCDC_INVDVAL	(1 << 12)
89*39cf4804SStelian Pop #define		ATMEL_LCDC_INVDVAL_NORMAL	(0 << 12)
90*39cf4804SStelian Pop #define		ATMEL_LCDC_INVDVAL_INVERTED	(1 << 12)
91*39cf4804SStelian Pop #define	ATMEL_LCDC_CLKMOD	(1 << 15)
92*39cf4804SStelian Pop #define		ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY	(0 << 15)
93*39cf4804SStelian Pop #define		ATMEL_LCDC_CLKMOD_ALWAYSACTIVE	(1 << 15)
94*39cf4804SStelian Pop #define	ATMEL_LCDC_MEMOR	(1 << 31)
95*39cf4804SStelian Pop #define		ATMEL_LCDC_MEMOR_BIG		(0 << 31)
96*39cf4804SStelian Pop #define		ATMEL_LCDC_MEMOR_LITTLE		(1 << 31)
97*39cf4804SStelian Pop 
98*39cf4804SStelian Pop #define ATMEL_LCDC_TIM1		0x0808
99*39cf4804SStelian Pop #define	ATMEL_LCDC_VFP		(0xffU <<  0)
100*39cf4804SStelian Pop #define	ATMEL_LCDC_VBP_OFFSET		8
101*39cf4804SStelian Pop #define	ATMEL_LCDC_VBP		(0xffU <<  ATMEL_LCDC_VBP_OFFSET)
102*39cf4804SStelian Pop #define	ATMEL_LCDC_VPW_OFFSET		16
103*39cf4804SStelian Pop #define	ATMEL_LCDC_VPW		(0x3fU << ATMEL_LCDC_VPW_OFFSET)
104*39cf4804SStelian Pop #define	ATMEL_LCDC_VHDLY_OFFSET		24
105*39cf4804SStelian Pop #define	ATMEL_LCDC_VHDLY	(0xfU  << ATMEL_LCDC_VHDLY_OFFSET)
106*39cf4804SStelian Pop 
107*39cf4804SStelian Pop #define ATMEL_LCDC_TIM2		0x080c
108*39cf4804SStelian Pop #define	ATMEL_LCDC_HBP		(0xffU  <<  0)
109*39cf4804SStelian Pop #define	ATMEL_LCDC_HPW_OFFSET		8
110*39cf4804SStelian Pop #define	ATMEL_LCDC_HPW		(0x3fU  <<  ATMEL_LCDC_HPW_OFFSET)
111*39cf4804SStelian Pop #define	ATMEL_LCDC_HFP_OFFSET		21
112*39cf4804SStelian Pop #define	ATMEL_LCDC_HFP		(0x7ffU << ATMEL_LCDC_HFP_OFFSET)
113*39cf4804SStelian Pop 
114*39cf4804SStelian Pop #define ATMEL_LCDC_LCDFRMCFG	0x0810
115*39cf4804SStelian Pop #define	ATMEL_LCDC_LINEVAL	(0x7ff <<  0)
116*39cf4804SStelian Pop #define	ATMEL_LCDC_HOZVAL_OFFSET	21
117*39cf4804SStelian Pop #define	ATMEL_LCDC_HOZVAL	(0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
118*39cf4804SStelian Pop 
119*39cf4804SStelian Pop #define ATMEL_LCDC_FIFO		0x0814
120*39cf4804SStelian Pop #define	ATMEL_LCDC_FIFOTH	(0xffff)
121*39cf4804SStelian Pop 
122*39cf4804SStelian Pop #define ATMEL_LCDC_MVAL		0x0818
123*39cf4804SStelian Pop 
124*39cf4804SStelian Pop #define ATMEL_LCDC_DP1_2	0x081c
125*39cf4804SStelian Pop #define ATMEL_LCDC_DP4_7	0x0820
126*39cf4804SStelian Pop #define ATMEL_LCDC_DP3_5	0x0824
127*39cf4804SStelian Pop #define ATMEL_LCDC_DP2_3	0x0828
128*39cf4804SStelian Pop #define ATMEL_LCDC_DP5_7	0x082c
129*39cf4804SStelian Pop #define ATMEL_LCDC_DP3_4	0x0830
130*39cf4804SStelian Pop #define ATMEL_LCDC_DP4_5	0x0834
131*39cf4804SStelian Pop #define ATMEL_LCDC_DP6_7	0x0838
132*39cf4804SStelian Pop #define	ATMEL_LCDC_DP1_2_VAL	(0xff)
133*39cf4804SStelian Pop #define	ATMEL_LCDC_DP4_7_VAL	(0xfffffff)
134*39cf4804SStelian Pop #define	ATMEL_LCDC_DP3_5_VAL	(0xfffff)
135*39cf4804SStelian Pop #define	ATMEL_LCDC_DP2_3_VAL	(0xfff)
136*39cf4804SStelian Pop #define	ATMEL_LCDC_DP5_7_VAL	(0xfffffff)
137*39cf4804SStelian Pop #define	ATMEL_LCDC_DP3_4_VAL	(0xffff)
138*39cf4804SStelian Pop #define	ATMEL_LCDC_DP4_5_VAL	(0xfffff)
139*39cf4804SStelian Pop #define	ATMEL_LCDC_DP6_7_VAL	(0xfffffff)
140*39cf4804SStelian Pop 
141*39cf4804SStelian Pop #define ATMEL_LCDC_PWRCON	0x083c
142*39cf4804SStelian Pop #define	ATMEL_LCDC_PWR		(1    <<  0)
143*39cf4804SStelian Pop #define	ATMEL_LCDC_GUARDT_OFFSET	1
144*39cf4804SStelian Pop #define	ATMEL_LCDC_GUARDT	(0x7f <<  ATMEL_LCDC_GUARDT_OFFSET)
145*39cf4804SStelian Pop #define	ATMEL_LCDC_BUSY		(1    << 31)
146*39cf4804SStelian Pop 
147*39cf4804SStelian Pop #define ATMEL_LCDC_CONTRAST_CTR	0x0840
148*39cf4804SStelian Pop #define	ATMEL_LCDC_PS		(3 << 0)
149*39cf4804SStelian Pop #define		ATMEL_LCDC_PS_DIV1		(0 << 0)
150*39cf4804SStelian Pop #define		ATMEL_LCDC_PS_DIV2		(1 << 0)
151*39cf4804SStelian Pop #define		ATMEL_LCDC_PS_DIV4		(2 << 0)
152*39cf4804SStelian Pop #define		ATMEL_LCDC_PS_DIV8		(3 << 0)
153*39cf4804SStelian Pop #define	ATMEL_LCDC_POL		(1 << 2)
154*39cf4804SStelian Pop #define		ATMEL_LCDC_POL_NEGATIVE		(0 << 2)
155*39cf4804SStelian Pop #define		ATMEL_LCDC_POL_POSITIVE		(1 << 2)
156*39cf4804SStelian Pop #define	ATMEL_LCDC_ENA		(1 << 3)
157*39cf4804SStelian Pop #define		ATMEL_LCDC_ENA_PWMDISABLE	(0 << 3)
158*39cf4804SStelian Pop #define		ATMEL_LCDC_ENA_PWMENABLE	(1 << 3)
159*39cf4804SStelian Pop 
160*39cf4804SStelian Pop #define ATMEL_LCDC_CONTRAST_VAL	0x0844
161*39cf4804SStelian Pop #define	ATMEL_LCDC_CVAL	(0xff)
162*39cf4804SStelian Pop 
163*39cf4804SStelian Pop #define ATMEL_LCDC_IER		0x0848
164*39cf4804SStelian Pop #define ATMEL_LCDC_IDR		0x084c
165*39cf4804SStelian Pop #define ATMEL_LCDC_IMR		0x0850
166*39cf4804SStelian Pop #define ATMEL_LCDC_ISR		0x0854
167*39cf4804SStelian Pop #define ATMEL_LCDC_ICR		0x0858
168*39cf4804SStelian Pop #define	ATMEL_LCDC_LNI		(1 << 0)
169*39cf4804SStelian Pop #define	ATMEL_LCDC_LSTLNI	(1 << 1)
170*39cf4804SStelian Pop #define	ATMEL_LCDC_EOFI		(1 << 2)
171*39cf4804SStelian Pop #define	ATMEL_LCDC_UFLWI	(1 << 4)
172*39cf4804SStelian Pop #define	ATMEL_LCDC_OWRI		(1 << 5)
173*39cf4804SStelian Pop #define	ATMEL_LCDC_MERI		(1 << 6)
174*39cf4804SStelian Pop 
175*39cf4804SStelian Pop #define ATMEL_LCDC_LUT(n)	(0x0c00 + ((n)*4))
176*39cf4804SStelian Pop 
177*39cf4804SStelian Pop #endif /* __ATMEL_LCDC_H__ */
178