xref: /rk3399_rockchip-uboot/include/atmel_lcdc.h (revision 326ea986ac150acdc7656d57fca647db80b50158)
139cf4804SStelian Pop /*
239cf4804SStelian Pop  *  Header file for AT91/AT32 LCD Controller
339cf4804SStelian Pop  *
439cf4804SStelian Pop  *  Data structure and register user interface
539cf4804SStelian Pop  *
639cf4804SStelian Pop  *  Copyright (C) 2007 Atmel Corporation
739cf4804SStelian Pop  *
8*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
939cf4804SStelian Pop  */
1039cf4804SStelian Pop #ifndef __ATMEL_LCDC_H__
1139cf4804SStelian Pop #define __ATMEL_LCDC_H__
1239cf4804SStelian Pop 
1339cf4804SStelian Pop #define ATMEL_LCDC_DMABADDR1	0x00
1439cf4804SStelian Pop #define ATMEL_LCDC_DMABADDR2	0x04
1539cf4804SStelian Pop #define ATMEL_LCDC_DMAFRMPT1	0x08
1639cf4804SStelian Pop #define ATMEL_LCDC_DMAFRMPT2	0x0c
1739cf4804SStelian Pop #define ATMEL_LCDC_DMAFRMADD1	0x10
1839cf4804SStelian Pop #define ATMEL_LCDC_DMAFRMADD2	0x14
1939cf4804SStelian Pop 
2039cf4804SStelian Pop #define ATMEL_LCDC_DMAFRMCFG	0x18
2139cf4804SStelian Pop #define	ATMEL_LCDC_FRSIZE	(0x7fffff <<  0)
2239cf4804SStelian Pop #define	ATMEL_LCDC_BLENGTH_OFFSET	24
2339cf4804SStelian Pop #define	ATMEL_LCDC_BLENGTH	(0x7f     << ATMEL_LCDC_BLENGTH_OFFSET)
2439cf4804SStelian Pop 
2539cf4804SStelian Pop #define ATMEL_LCDC_DMACON	0x1c
2639cf4804SStelian Pop #define	ATMEL_LCDC_DMAEN	(0x1 << 0)
2739cf4804SStelian Pop #define	ATMEL_LCDC_DMARST	(0x1 << 1)
2839cf4804SStelian Pop #define	ATMEL_LCDC_DMABUSY	(0x1 << 2)
2939cf4804SStelian Pop #define		ATMEL_LCDC_DMAUPDT	(0x1 << 3)
3039cf4804SStelian Pop #define		ATMEL_LCDC_DMA2DEN	(0x1 << 4)
3139cf4804SStelian Pop 
3239cf4804SStelian Pop #define ATMEL_LCDC_DMA2DCFG	0x20
3339cf4804SStelian Pop #define		ATMEL_LCDC_ADDRINC_OFFSET	0
3439cf4804SStelian Pop #define		ATMEL_LCDC_ADDRINC		(0xffff)
3539cf4804SStelian Pop #define		ATMEL_LCDC_PIXELOFF_OFFSET	24
3639cf4804SStelian Pop #define		ATMEL_LCDC_PIXELOFF		(0x1f << 24)
3739cf4804SStelian Pop 
3839cf4804SStelian Pop #define ATMEL_LCDC_LCDCON1	0x0800
3939cf4804SStelian Pop #define	ATMEL_LCDC_BYPASS	(1     <<  0)
4039cf4804SStelian Pop #define	ATMEL_LCDC_CLKVAL_OFFSET	12
4139cf4804SStelian Pop #define	ATMEL_LCDC_CLKVAL	(0x1ff << ATMEL_LCDC_CLKVAL_OFFSET)
4239cf4804SStelian Pop #define	ATMEL_LCDC_LINCNT	(0x7ff << 21)
4339cf4804SStelian Pop 
4439cf4804SStelian Pop #define ATMEL_LCDC_LCDCON2	0x0804
4539cf4804SStelian Pop #define	ATMEL_LCDC_DISTYPE	(3 << 0)
4639cf4804SStelian Pop #define		ATMEL_LCDC_DISTYPE_STNMONO	(0 << 0)
4739cf4804SStelian Pop #define		ATMEL_LCDC_DISTYPE_STNCOLOR	(1 << 0)
4839cf4804SStelian Pop #define		ATMEL_LCDC_DISTYPE_TFT		(2 << 0)
4939cf4804SStelian Pop #define	ATMEL_LCDC_SCANMOD	(1 << 2)
5039cf4804SStelian Pop #define		ATMEL_LCDC_SCANMOD_SINGLE	(0 << 2)
5139cf4804SStelian Pop #define		ATMEL_LCDC_SCANMOD_DUAL		(1 << 2)
5239cf4804SStelian Pop #define	ATMEL_LCDC_IFWIDTH	(3 << 3)
5339cf4804SStelian Pop #define		ATMEL_LCDC_IFWIDTH_4		(0 << 3)
5439cf4804SStelian Pop #define		ATMEL_LCDC_IFWIDTH_8		(1 << 3)
5539cf4804SStelian Pop #define		ATMEL_LCDC_IFWIDTH_16		(2 << 3)
5639cf4804SStelian Pop #define	ATMEL_LCDC_PIXELSIZE	(7 << 5)
5739cf4804SStelian Pop #define		ATMEL_LCDC_PIXELSIZE_1		(0 << 5)
5839cf4804SStelian Pop #define		ATMEL_LCDC_PIXELSIZE_2		(1 << 5)
5939cf4804SStelian Pop #define		ATMEL_LCDC_PIXELSIZE_4		(2 << 5)
6039cf4804SStelian Pop #define		ATMEL_LCDC_PIXELSIZE_8		(3 << 5)
6139cf4804SStelian Pop #define		ATMEL_LCDC_PIXELSIZE_16		(4 << 5)
6239cf4804SStelian Pop #define		ATMEL_LCDC_PIXELSIZE_24		(5 << 5)
6339cf4804SStelian Pop #define		ATMEL_LCDC_PIXELSIZE_32		(6 << 5)
6439cf4804SStelian Pop #define	ATMEL_LCDC_INVVD	(1 << 8)
6539cf4804SStelian Pop #define		ATMEL_LCDC_INVVD_NORMAL		(0 << 8)
6639cf4804SStelian Pop #define		ATMEL_LCDC_INVVD_INVERTED	(1 << 8)
6739cf4804SStelian Pop #define	ATMEL_LCDC_INVFRAME	(1 << 9 )
6839cf4804SStelian Pop #define		ATMEL_LCDC_INVFRAME_NORMAL	(0 << 9)
6939cf4804SStelian Pop #define		ATMEL_LCDC_INVFRAME_INVERTED	(1 << 9)
7039cf4804SStelian Pop #define	ATMEL_LCDC_INVLINE	(1 << 10)
7139cf4804SStelian Pop #define		ATMEL_LCDC_INVLINE_NORMAL	(0 << 10)
7239cf4804SStelian Pop #define		ATMEL_LCDC_INVLINE_INVERTED	(1 << 10)
7339cf4804SStelian Pop #define	ATMEL_LCDC_INVCLK	(1 << 11)
7439cf4804SStelian Pop #define		ATMEL_LCDC_INVCLK_NORMAL	(0 << 11)
7539cf4804SStelian Pop #define		ATMEL_LCDC_INVCLK_INVERTED	(1 << 11)
7639cf4804SStelian Pop #define	ATMEL_LCDC_INVDVAL	(1 << 12)
7739cf4804SStelian Pop #define		ATMEL_LCDC_INVDVAL_NORMAL	(0 << 12)
7839cf4804SStelian Pop #define		ATMEL_LCDC_INVDVAL_INVERTED	(1 << 12)
7939cf4804SStelian Pop #define	ATMEL_LCDC_CLKMOD	(1 << 15)
8039cf4804SStelian Pop #define		ATMEL_LCDC_CLKMOD_ACTIVEDISPLAY	(0 << 15)
8139cf4804SStelian Pop #define		ATMEL_LCDC_CLKMOD_ALWAYSACTIVE	(1 << 15)
8239cf4804SStelian Pop #define	ATMEL_LCDC_MEMOR	(1 << 31)
8339cf4804SStelian Pop #define		ATMEL_LCDC_MEMOR_BIG		(0 << 31)
8439cf4804SStelian Pop #define		ATMEL_LCDC_MEMOR_LITTLE		(1 << 31)
8539cf4804SStelian Pop 
8639cf4804SStelian Pop #define ATMEL_LCDC_TIM1		0x0808
8739cf4804SStelian Pop #define	ATMEL_LCDC_VFP		(0xffU <<  0)
8839cf4804SStelian Pop #define	ATMEL_LCDC_VBP_OFFSET		8
8939cf4804SStelian Pop #define	ATMEL_LCDC_VBP		(0xffU <<  ATMEL_LCDC_VBP_OFFSET)
9039cf4804SStelian Pop #define	ATMEL_LCDC_VPW_OFFSET		16
9139cf4804SStelian Pop #define	ATMEL_LCDC_VPW		(0x3fU << ATMEL_LCDC_VPW_OFFSET)
9239cf4804SStelian Pop #define	ATMEL_LCDC_VHDLY_OFFSET		24
9339cf4804SStelian Pop #define	ATMEL_LCDC_VHDLY	(0xfU  << ATMEL_LCDC_VHDLY_OFFSET)
9439cf4804SStelian Pop 
9539cf4804SStelian Pop #define ATMEL_LCDC_TIM2		0x080c
9639cf4804SStelian Pop #define	ATMEL_LCDC_HBP		(0xffU  <<  0)
9739cf4804SStelian Pop #define	ATMEL_LCDC_HPW_OFFSET		8
9839cf4804SStelian Pop #define	ATMEL_LCDC_HPW		(0x3fU  <<  ATMEL_LCDC_HPW_OFFSET)
9939cf4804SStelian Pop #define	ATMEL_LCDC_HFP_OFFSET		21
10039cf4804SStelian Pop #define	ATMEL_LCDC_HFP		(0x7ffU << ATMEL_LCDC_HFP_OFFSET)
10139cf4804SStelian Pop 
10239cf4804SStelian Pop #define ATMEL_LCDC_LCDFRMCFG	0x0810
10339cf4804SStelian Pop #define	ATMEL_LCDC_LINEVAL	(0x7ff <<  0)
10439cf4804SStelian Pop #define	ATMEL_LCDC_HOZVAL_OFFSET	21
10539cf4804SStelian Pop #define	ATMEL_LCDC_HOZVAL	(0x7ff << ATMEL_LCDC_HOZVAL_OFFSET)
10639cf4804SStelian Pop 
10739cf4804SStelian Pop #define ATMEL_LCDC_FIFO		0x0814
10839cf4804SStelian Pop #define	ATMEL_LCDC_FIFOTH	(0xffff)
10939cf4804SStelian Pop 
11039cf4804SStelian Pop #define ATMEL_LCDC_MVAL		0x0818
11139cf4804SStelian Pop 
11239cf4804SStelian Pop #define ATMEL_LCDC_DP1_2	0x081c
11339cf4804SStelian Pop #define ATMEL_LCDC_DP4_7	0x0820
11439cf4804SStelian Pop #define ATMEL_LCDC_DP3_5	0x0824
11539cf4804SStelian Pop #define ATMEL_LCDC_DP2_3	0x0828
11639cf4804SStelian Pop #define ATMEL_LCDC_DP5_7	0x082c
11739cf4804SStelian Pop #define ATMEL_LCDC_DP3_4	0x0830
11839cf4804SStelian Pop #define ATMEL_LCDC_DP4_5	0x0834
11939cf4804SStelian Pop #define ATMEL_LCDC_DP6_7	0x0838
12039cf4804SStelian Pop #define	ATMEL_LCDC_DP1_2_VAL	(0xff)
12139cf4804SStelian Pop #define	ATMEL_LCDC_DP4_7_VAL	(0xfffffff)
12239cf4804SStelian Pop #define	ATMEL_LCDC_DP3_5_VAL	(0xfffff)
12339cf4804SStelian Pop #define	ATMEL_LCDC_DP2_3_VAL	(0xfff)
12439cf4804SStelian Pop #define	ATMEL_LCDC_DP5_7_VAL	(0xfffffff)
12539cf4804SStelian Pop #define	ATMEL_LCDC_DP3_4_VAL	(0xffff)
12639cf4804SStelian Pop #define	ATMEL_LCDC_DP4_5_VAL	(0xfffff)
12739cf4804SStelian Pop #define	ATMEL_LCDC_DP6_7_VAL	(0xfffffff)
12839cf4804SStelian Pop 
12939cf4804SStelian Pop #define ATMEL_LCDC_PWRCON	0x083c
13039cf4804SStelian Pop #define	ATMEL_LCDC_PWR		(1    <<  0)
13139cf4804SStelian Pop #define	ATMEL_LCDC_GUARDT_OFFSET	1
13239cf4804SStelian Pop #define	ATMEL_LCDC_GUARDT	(0x7f <<  ATMEL_LCDC_GUARDT_OFFSET)
13339cf4804SStelian Pop #define	ATMEL_LCDC_BUSY		(1    << 31)
13439cf4804SStelian Pop 
13539cf4804SStelian Pop #define ATMEL_LCDC_CONTRAST_CTR	0x0840
13639cf4804SStelian Pop #define	ATMEL_LCDC_PS		(3 << 0)
13739cf4804SStelian Pop #define		ATMEL_LCDC_PS_DIV1		(0 << 0)
13839cf4804SStelian Pop #define		ATMEL_LCDC_PS_DIV2		(1 << 0)
13939cf4804SStelian Pop #define		ATMEL_LCDC_PS_DIV4		(2 << 0)
14039cf4804SStelian Pop #define		ATMEL_LCDC_PS_DIV8		(3 << 0)
14139cf4804SStelian Pop #define	ATMEL_LCDC_POL		(1 << 2)
14239cf4804SStelian Pop #define		ATMEL_LCDC_POL_NEGATIVE		(0 << 2)
14339cf4804SStelian Pop #define		ATMEL_LCDC_POL_POSITIVE		(1 << 2)
14439cf4804SStelian Pop #define	ATMEL_LCDC_ENA		(1 << 3)
14539cf4804SStelian Pop #define		ATMEL_LCDC_ENA_PWMDISABLE	(0 << 3)
14639cf4804SStelian Pop #define		ATMEL_LCDC_ENA_PWMENABLE	(1 << 3)
14739cf4804SStelian Pop 
14839cf4804SStelian Pop #define ATMEL_LCDC_CONTRAST_VAL	0x0844
14939cf4804SStelian Pop #define	ATMEL_LCDC_CVAL	(0xff)
15039cf4804SStelian Pop 
15139cf4804SStelian Pop #define ATMEL_LCDC_IER		0x0848
15239cf4804SStelian Pop #define ATMEL_LCDC_IDR		0x084c
15339cf4804SStelian Pop #define ATMEL_LCDC_IMR		0x0850
15439cf4804SStelian Pop #define ATMEL_LCDC_ISR		0x0854
15539cf4804SStelian Pop #define ATMEL_LCDC_ICR		0x0858
15639cf4804SStelian Pop #define	ATMEL_LCDC_LNI		(1 << 0)
15739cf4804SStelian Pop #define	ATMEL_LCDC_LSTLNI	(1 << 1)
15839cf4804SStelian Pop #define	ATMEL_LCDC_EOFI		(1 << 2)
15939cf4804SStelian Pop #define	ATMEL_LCDC_UFLWI	(1 << 4)
16039cf4804SStelian Pop #define	ATMEL_LCDC_OWRI		(1 << 5)
16139cf4804SStelian Pop #define	ATMEL_LCDC_MERI		(1 << 6)
16239cf4804SStelian Pop 
16339cf4804SStelian Pop #define ATMEL_LCDC_LUT(n)	(0x0c00 + ((n)*4))
16439cf4804SStelian Pop 
16539cf4804SStelian Pop #endif /* __ATMEL_LCDC_H__ */
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