1fe8c2806Swdenk /* 2fe8c2806Swdenk * (C) Copyright 2000 3fe8c2806Swdenk * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4fe8c2806Swdenk * 5fe8c2806Swdenk * See file CREDITS for list of people who contributed to this 6fe8c2806Swdenk * project. 7fe8c2806Swdenk * 8fe8c2806Swdenk * This program is free software; you can redistribute it and/or 9fe8c2806Swdenk * modify it under the terms of the GNU General Public License as 10fe8c2806Swdenk * published by the Free Software Foundation; either version 2 of 11fe8c2806Swdenk * the License, or (at your option) any later version. 12fe8c2806Swdenk * 13fe8c2806Swdenk * This program is distributed in the hope that it will be useful, 14fe8c2806Swdenk * but WITHOUT ANY WARRANTY; without even the implied warranty of 15fe8c2806Swdenk * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16fe8c2806Swdenk * GNU General Public License for more details. 17fe8c2806Swdenk * 18fe8c2806Swdenk * You should have received a copy of the GNU General Public License 19fe8c2806Swdenk * along with this program; if not, write to the Free Software 20fe8c2806Swdenk * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21fe8c2806Swdenk * MA 02111-1307 USA 22fe8c2806Swdenk */ 23fe8c2806Swdenk 24fe8c2806Swdenk /* 25fe8c2806Swdenk * Most of the following information was derived from the document 26fe8c2806Swdenk * "Information Technology - AT Attachment-3 Interface (ATA-3)" 27fe8c2806Swdenk * which can be found at: 28fe8c2806Swdenk * http://www.dt.wdc.com/ata/ata-3/ata3r5v.zip 29fe8c2806Swdenk * ftp://poctok.iae.nsk.su/pub/asm/Documents/IDE/ATA3R5V.ZIP 30fe8c2806Swdenk * ftp://ftp.fee.vutbr.cz/pub/doc/io/ata/ata-3/ata3r5v.zip 31fe8c2806Swdenk */ 32fe8c2806Swdenk 33fe8c2806Swdenk #ifndef _ATA_H 34fe8c2806Swdenk #define _ATA_H 35fe8c2806Swdenk 36fe8c2806Swdenk /* Register addressing depends on the hardware design; for instance, 37fe8c2806Swdenk * 8-bit (register) and 16-bit (data) accesses might use different 38fe8c2806Swdenk * address spaces. This is implemented by the following definitions. 39fe8c2806Swdenk */ 409fd5e31fSwdenk #ifndef CFG_ATA_STRIDE 419fd5e31fSwdenk #define CFG_ATA_STRIDE 1 429fd5e31fSwdenk #endif 43fe8c2806Swdenk 449fd5e31fSwdenk #define ATA_IO_DATA(x) (CFG_ATA_DATA_OFFSET+((x) * CFG_ATA_STRIDE)) 459fd5e31fSwdenk #define ATA_IO_REG(x) (CFG_ATA_REG_OFFSET +((x) * CFG_ATA_STRIDE)) 469fd5e31fSwdenk #define ATA_IO_ALT(x) (CFG_ATA_ALT_OFFSET +((x) * CFG_ATA_STRIDE)) 47fe8c2806Swdenk 48fe8c2806Swdenk /* 49fe8c2806Swdenk * I/O Register Descriptions 50fe8c2806Swdenk */ 51fe8c2806Swdenk #define ATA_DATA_REG ATA_IO_DATA(0) 52fe8c2806Swdenk #define ATA_ERROR_REG ATA_IO_REG(1) 53fe8c2806Swdenk #define ATA_SECT_CNT ATA_IO_REG(2) 54fe8c2806Swdenk #define ATA_SECT_NUM ATA_IO_REG(3) 55fe8c2806Swdenk #define ATA_CYL_LOW ATA_IO_REG(4) 56fe8c2806Swdenk #define ATA_CYL_HIGH ATA_IO_REG(5) 57fe8c2806Swdenk #define ATA_DEV_HD ATA_IO_REG(6) 58fe8c2806Swdenk #define ATA_COMMAND ATA_IO_REG(7) 59*a522fa0eSwdenk #define ATA_DATA_EVEN ATA_IO_REG(8) 60*a522fa0eSwdenk #define ATA_DATA_ODD ATA_IO_REG(9) 61fe8c2806Swdenk #define ATA_STATUS ATA_COMMAND 62fe8c2806Swdenk #define ATA_DEV_CTL ATA_IO_ALT(6) 63fe8c2806Swdenk #define ATA_LBA_LOW ATA_SECT_NUM 64fe8c2806Swdenk #define ATA_LBA_MID ATA_CYL_LOW 65fe8c2806Swdenk #define ATA_LBA_HIGH ATA_CYL_HIGH 66fe8c2806Swdenk #define ATA_LBA_SEL ATA_DEV_CTL 67fe8c2806Swdenk 68fe8c2806Swdenk /* 69fe8c2806Swdenk * Status register bits 70fe8c2806Swdenk */ 71fe8c2806Swdenk #define ATA_STAT_BUSY 0x80 /* Device Busy */ 72fe8c2806Swdenk #define ATA_STAT_READY 0x40 /* Device Ready */ 73fe8c2806Swdenk #define ATA_STAT_FAULT 0x20 /* Device Fault */ 74fe8c2806Swdenk #define ATA_STAT_SEEK 0x10 /* Device Seek Complete */ 75fe8c2806Swdenk #define ATA_STAT_DRQ 0x08 /* Data Request (ready) */ 76fe8c2806Swdenk #define ATA_STAT_CORR 0x04 /* Corrected Data Error */ 77fe8c2806Swdenk #define ATA_STAT_INDEX 0x02 /* Vendor specific */ 78fe8c2806Swdenk #define ATA_STAT_ERR 0x01 /* Error */ 79fe8c2806Swdenk 80fe8c2806Swdenk /* 81fe8c2806Swdenk * Device / Head Register Bits 82fe8c2806Swdenk */ 83fe8c2806Swdenk #define ATA_DEVICE(x) ((x & 1)<<4) 84fe8c2806Swdenk #define ATA_LBA 0xE0 85fe8c2806Swdenk 86fe8c2806Swdenk /* 87fe8c2806Swdenk * ATA Commands (only mandatory commands listed here) 88fe8c2806Swdenk */ 89fe8c2806Swdenk #define ATA_CMD_READ 0x20 /* Read Sectors (with retries) */ 90fe8c2806Swdenk #define ATA_CMD_READN 0x21 /* Read Sectors ( no retries) */ 91fe8c2806Swdenk #define ATA_CMD_WRITE 0x30 /* Write Sectores (with retries)*/ 92fe8c2806Swdenk #define ATA_CMD_WRITEN 0x31 /* Write Sectors ( no retries)*/ 93fe8c2806Swdenk #define ATA_CMD_VRFY 0x40 /* Read Verify (with retries) */ 94fe8c2806Swdenk #define ATA_CMD_VRFYN 0x41 /* Read verify ( no retries) */ 95fe8c2806Swdenk #define ATA_CMD_SEEK 0x70 /* Seek */ 96fe8c2806Swdenk #define ATA_CMD_DIAG 0x90 /* Execute Device Diagnostic */ 97fe8c2806Swdenk #define ATA_CMD_INIT 0x91 /* Initialize Device Parameters */ 98fe8c2806Swdenk #define ATA_CMD_RD_MULT 0xC4 /* Read Multiple */ 99fe8c2806Swdenk #define ATA_CMD_WR_MULT 0xC5 /* Write Multiple */ 100fe8c2806Swdenk #define ATA_CMD_SETMULT 0xC6 /* Set Multiple Mode */ 101fe8c2806Swdenk #define ATA_CMD_RD_DMA 0xC8 /* Read DMA (with retries) */ 102fe8c2806Swdenk #define ATA_CMD_RD_DMAN 0xC9 /* Read DMS ( no retries) */ 103fe8c2806Swdenk #define ATA_CMD_WR_DMA 0xCA /* Write DMA (with retries) */ 104fe8c2806Swdenk #define ATA_CMD_WR_DMAN 0xCB /* Write DMA ( no retires) */ 105fe8c2806Swdenk #define ATA_CMD_IDENT 0xEC /* Identify Device */ 106fe8c2806Swdenk #define ATA_CMD_SETF 0xEF /* Set Features */ 107fe8c2806Swdenk #define ATA_CMD_CHK_PWR 0xE5 /* Check Power Mode */ 108fe8c2806Swdenk 109fe8c2806Swdenk /* 110fe8c2806Swdenk * ATAPI Commands 111fe8c2806Swdenk */ 112fe8c2806Swdenk #define ATAPI_CMD_IDENT 0xA1 /* Identify AT Atachment Packed Interface Device */ 113fe8c2806Swdenk #define ATAPI_CMD_PACKET 0xA0 /* Packed Command */ 114fe8c2806Swdenk 115fe8c2806Swdenk 116fe8c2806Swdenk #define ATAPI_CMD_INQUIRY 0x12 117fe8c2806Swdenk #define ATAPI_CMD_REQ_SENSE 0x03 118fe8c2806Swdenk #define ATAPI_CMD_READ_CAP 0x25 119fe8c2806Swdenk #define ATAPI_CMD_START_STOP 0x1B 120fe8c2806Swdenk #define ATAPI_CMD_READ_12 0xA8 121fe8c2806Swdenk 122fe8c2806Swdenk 123fe8c2806Swdenk #define ATA_GET_ERR() inb(ATA_STATUS) 124fe8c2806Swdenk #define ATA_GET_STAT() inb(ATA_STATUS) 125fe8c2806Swdenk #define ATA_OK_STAT(stat,good,bad) (((stat)&((good)|(bad)))==(good)) 126fe8c2806Swdenk #define ATA_BAD_R_STAT (ATA_STAT_BUSY | ATA_STAT_ERR) 127fe8c2806Swdenk #define ATA_BAD_W_STAT (ATA_BAD_R_STAT | ATA_STAT_FAULT) 128fe8c2806Swdenk #define ATA_BAD_STAT (ATA_BAD_R_STAT | ATA_STAT_DRQ) 129fe8c2806Swdenk #define ATA_DRIVE_READY (ATA_READY_STAT | ATA_STAT_SEEK) 130fe8c2806Swdenk #define ATA_DATA_READY (ATA_STAT_DRQ) 131fe8c2806Swdenk 132fe8c2806Swdenk #define ATA_BLOCKSIZE 512 /* bytes */ 133fe8c2806Swdenk #define ATA_BLOCKSHIFT 9 /* 2 ^ ATA_BLOCKSIZESHIFT = 512 */ 134fe8c2806Swdenk #define ATA_SECTORWORDS (512 / sizeof(unsigned long)) 135fe8c2806Swdenk 136fe8c2806Swdenk #ifndef ATA_RESET_TIME 137fe8c2806Swdenk #define ATA_RESET_TIME 60 /* spec allows up to 31 seconds */ 138fe8c2806Swdenk #endif 139fe8c2806Swdenk 140fe8c2806Swdenk /* ------------------------------------------------------------------------- */ 141fe8c2806Swdenk 142fe8c2806Swdenk /* 143fe8c2806Swdenk * structure returned by ATA_CMD_IDENT, as per ANSI ATA2 rev.2f spec 144fe8c2806Swdenk */ 145fe8c2806Swdenk typedef struct hd_driveid { 146fe8c2806Swdenk unsigned short config; /* lots of obsolete bit flags */ 147fe8c2806Swdenk unsigned short cyls; /* "physical" cyls */ 148fe8c2806Swdenk unsigned short reserved2; /* reserved (word 2) */ 149fe8c2806Swdenk unsigned short heads; /* "physical" heads */ 150fe8c2806Swdenk unsigned short track_bytes; /* unformatted bytes per track */ 151fe8c2806Swdenk unsigned short sector_bytes; /* unformatted bytes per sector */ 152fe8c2806Swdenk unsigned short sectors; /* "physical" sectors per track */ 153fe8c2806Swdenk unsigned short vendor0; /* vendor unique */ 154fe8c2806Swdenk unsigned short vendor1; /* vendor unique */ 155fe8c2806Swdenk unsigned short vendor2; /* vendor unique */ 156fe8c2806Swdenk unsigned char serial_no[20]; /* 0 = not_specified */ 157fe8c2806Swdenk unsigned short buf_type; 158fe8c2806Swdenk unsigned short buf_size; /* 512 byte increments; 0 = not_specified */ 159fe8c2806Swdenk unsigned short ecc_bytes; /* for r/w long cmds; 0 = not_specified */ 160fe8c2806Swdenk unsigned char fw_rev[8]; /* 0 = not_specified */ 161fe8c2806Swdenk unsigned char model[40]; /* 0 = not_specified */ 162fe8c2806Swdenk unsigned char max_multsect; /* 0=not_implemented */ 163fe8c2806Swdenk unsigned char vendor3; /* vendor unique */ 164fe8c2806Swdenk unsigned short dword_io; /* 0=not_implemented; 1=implemented */ 165fe8c2806Swdenk unsigned char vendor4; /* vendor unique */ 166fe8c2806Swdenk unsigned char capability; /* bits 0:DMA 1:LBA 2:IORDYsw 3:IORDYsup*/ 167fe8c2806Swdenk unsigned short reserved50; /* reserved (word 50) */ 168fe8c2806Swdenk unsigned char vendor5; /* vendor unique */ 169fe8c2806Swdenk unsigned char tPIO; /* 0=slow, 1=medium, 2=fast */ 170fe8c2806Swdenk unsigned char vendor6; /* vendor unique */ 171fe8c2806Swdenk unsigned char tDMA; /* 0=slow, 1=medium, 2=fast */ 172fe8c2806Swdenk unsigned short field_valid; /* bits 0:cur_ok 1:eide_ok */ 173fe8c2806Swdenk unsigned short cur_cyls; /* logical cylinders */ 174fe8c2806Swdenk unsigned short cur_heads; /* logical heads */ 175fe8c2806Swdenk unsigned short cur_sectors; /* logical sectors per track */ 176fe8c2806Swdenk unsigned short cur_capacity0; /* logical total sectors on drive */ 177fe8c2806Swdenk unsigned short cur_capacity1; /* (2 words, misaligned int) */ 178fe8c2806Swdenk unsigned char multsect; /* current multiple sector count */ 179fe8c2806Swdenk unsigned char multsect_valid; /* when (bit0==1) multsect is ok */ 180fe8c2806Swdenk unsigned int lba_capacity; /* total number of sectors */ 181fe8c2806Swdenk unsigned short dma_1word; /* single-word dma info */ 182fe8c2806Swdenk unsigned short dma_mword; /* multiple-word dma info */ 183fe8c2806Swdenk unsigned short eide_pio_modes; /* bits 0:mode3 1:mode4 */ 184fe8c2806Swdenk unsigned short eide_dma_min; /* min mword dma cycle time (ns) */ 185fe8c2806Swdenk unsigned short eide_dma_time; /* recommended mword dma cycle time (ns) */ 186fe8c2806Swdenk unsigned short eide_pio; /* min cycle time (ns), no IORDY */ 187fe8c2806Swdenk unsigned short eide_pio_iordy; /* min cycle time (ns), with IORDY */ 188fe8c2806Swdenk unsigned short words69_70[2]; /* reserved words 69-70 */ 189fe8c2806Swdenk unsigned short words71_74[4]; /* reserved words 71-74 */ 190fe8c2806Swdenk unsigned short queue_depth; /* */ 191fe8c2806Swdenk unsigned short words76_79[4]; /* reserved words 76-79 */ 192fe8c2806Swdenk unsigned short major_rev_num; /* */ 193fe8c2806Swdenk unsigned short minor_rev_num; /* */ 194fe8c2806Swdenk unsigned short command_set_1; /* bits 0:Smart 1:Security 2:Removable 3:PM */ 195fe8c2806Swdenk unsigned short command_set_2; /* bits 14:Smart Enabled 13:0 zero */ 196fe8c2806Swdenk unsigned short cfsse; /* command set-feature supported extensions */ 197fe8c2806Swdenk unsigned short cfs_enable_1; /* command set-feature enabled */ 198fe8c2806Swdenk unsigned short cfs_enable_2; /* command set-feature enabled */ 199fe8c2806Swdenk unsigned short csf_default; /* command set-feature default */ 200fe8c2806Swdenk unsigned short dma_ultra; /* */ 201fe8c2806Swdenk unsigned short word89; /* reserved (word 89) */ 202fe8c2806Swdenk unsigned short word90; /* reserved (word 90) */ 203fe8c2806Swdenk unsigned short CurAPMvalues; /* current APM values */ 204fe8c2806Swdenk unsigned short word92; /* reserved (word 92) */ 205fe8c2806Swdenk unsigned short hw_config; /* hardware config */ 206fe8c2806Swdenk unsigned short words94_125[32];/* reserved words 94-125 */ 207fe8c2806Swdenk unsigned short last_lun; /* reserved (word 126) */ 208fe8c2806Swdenk unsigned short word127; /* reserved (word 127) */ 209fe8c2806Swdenk unsigned short dlf; /* device lock function 210fe8c2806Swdenk * 15:9 reserved 211fe8c2806Swdenk * 8 security level 1:max 0:high 212fe8c2806Swdenk * 7:6 reserved 213fe8c2806Swdenk * 5 enhanced erase 214fe8c2806Swdenk * 4 expire 215fe8c2806Swdenk * 3 frozen 216fe8c2806Swdenk * 2 locked 217fe8c2806Swdenk * 1 en/disabled 218fe8c2806Swdenk * 0 capability 219fe8c2806Swdenk */ 220fe8c2806Swdenk unsigned short csfo; /* current set features options 221fe8c2806Swdenk * 15:4 reserved 222fe8c2806Swdenk * 3 auto reassign 223fe8c2806Swdenk * 2 reverting 224fe8c2806Swdenk * 1 read-look-ahead 225fe8c2806Swdenk * 0 write cache 226fe8c2806Swdenk */ 227fe8c2806Swdenk unsigned short words130_155[26];/* reserved vendor words 130-155 */ 228fe8c2806Swdenk unsigned short word156; 229fe8c2806Swdenk unsigned short words157_159[3];/* reserved vendor words 157-159 */ 230fe8c2806Swdenk unsigned short words160_255[95];/* reserved words 160-255 */ 231fe8c2806Swdenk } hd_driveid_t; 232fe8c2806Swdenk 233fe8c2806Swdenk 234fe8c2806Swdenk /* 235fe8c2806Swdenk * PIO Mode Configuration 236fe8c2806Swdenk * 237fe8c2806Swdenk * See ATA-3 (AT Attachment-3 Interface) documentation, Figure 14 / Table 21 238fe8c2806Swdenk */ 239fe8c2806Swdenk 240fe8c2806Swdenk typedef struct { 241fe8c2806Swdenk unsigned int t_setup; /* Setup Time in [ns] or clocks */ 242fe8c2806Swdenk unsigned int t_length; /* Length Time in [ns] or clocks */ 243fe8c2806Swdenk unsigned int t_hold; /* Hold Time in [ns] or clocks */ 244fe8c2806Swdenk } 245fe8c2806Swdenk pio_config_t; 246fe8c2806Swdenk 247fe8c2806Swdenk #define IDE_MAX_PIO_MODE 4 /* max suppurted PIO mode */ 248fe8c2806Swdenk 249fe8c2806Swdenk /* ------------------------------------------------------------------------- */ 250fe8c2806Swdenk 251fe8c2806Swdenk #endif /* _ATA_H */ 252