1*c609719bSwdenk /* 2*c609719bSwdenk * (C) Copyright 2002 3*c609719bSwdenk * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4*c609719bSwdenk * 5*c609719bSwdenk * See file CREDITS for list of people who contributed to this 6*c609719bSwdenk * project. 7*c609719bSwdenk * 8*c609719bSwdenk * This program is free software; you can redistribute it and/or 9*c609719bSwdenk * modify it under the terms of the GNU General Public License as 10*c609719bSwdenk * published by the Free Software Foundation; either version 2 of 11*c609719bSwdenk * the License, or (at your option) any later version. 12*c609719bSwdenk * 13*c609719bSwdenk * This program is distributed in the hope that it will be useful, 14*c609719bSwdenk * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*c609719bSwdenk * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*c609719bSwdenk * GNU General Public License for more details. 17*c609719bSwdenk * 18*c609719bSwdenk * You should have received a copy of the GNU General Public License 19*c609719bSwdenk * along with this program; if not, write to the Free Software 20*c609719bSwdenk * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*c609719bSwdenk * MA 02111-1307 USA 22*c609719bSwdenk * 23*c609719bSwdenk */ 24*c609719bSwdenk 25*c609719bSwdenk #include <fpga.h> 26*c609719bSwdenk 27*c609719bSwdenk #ifndef _ALTERA_H_ 28*c609719bSwdenk #define _ALTERA_H_ 29*c609719bSwdenk 30*c609719bSwdenk /* 31*c609719bSwdenk * Note that this is just Altera FPGA interface boilerplate. 32*c609719bSwdenk * There is no support for Altera devices yet. 33*c609719bSwdenk * 34*c609719bSwdenk * See include/xilinx.h for a working example. 35*c609719bSwdenk */ 36*c609719bSwdenk 37*c609719bSwdenk /* In your board's config.h file you should define CONFIG_FPGA as such: 38*c609719bSwdenk * #define CONFIG_FPGA (CFG_ALTERA_xxx | CFG_ALTERA_IF_xxx ) 39*c609719bSwdenk */ 40*c609719bSwdenk 41*c609719bSwdenk /* Altera Model definitions */ 42*c609719bSwdenk #define CFG_ALTERA_xxxx ( CFG_FPGA_ALTERA | CFG_FPGA_DEV( 0x1 )) 43*c609719bSwdenk /* Add new models here */ 44*c609719bSwdenk 45*c609719bSwdenk /* Altera Interface definitions */ 46*c609719bSwdenk #define CFG_ALTERA_IF_xxx CFG_FPGA_IF( 0x1 ) 47*c609719bSwdenk /* Add new interfaces here */ 48*c609719bSwdenk 49*c609719bSwdenk typedef enum { /* typedef Altera_iface */ 50*c609719bSwdenk min_altera_iface_type, /* insert all new types after this */ 51*c609719bSwdenk /* Add new interfaces here */ 52*c609719bSwdenk max_altera_iface_type /* insert all new types before this */ 53*c609719bSwdenk } Altera_iface; /* end, typedef Altera_iface */ 54*c609719bSwdenk 55*c609719bSwdenk typedef enum { /* typedef Altera_Family */ 56*c609719bSwdenk min_altera_type, /* insert all new types after this */ 57*c609719bSwdenk /* Add new models here */ 58*c609719bSwdenk max_altera_type /* insert all new types before this */ 59*c609719bSwdenk } Altera_Family; /* end, typedef Altera_Family */ 60*c609719bSwdenk 61*c609719bSwdenk typedef struct { /* typedef Altera_desc */ 62*c609719bSwdenk Altera_Family family; /* part type */ 63*c609719bSwdenk Altera_iface iface; /* interface type */ 64*c609719bSwdenk size_t size; /* bytes of data part can accept */ 65*c609719bSwdenk void * base; /* base interface address */ 66*c609719bSwdenk } Altera_desc; /* end, typedef Altera_desc */ 67*c609719bSwdenk 68*c609719bSwdenk extern int altera_load( Altera_desc *desc, void *image, size_t size ); 69*c609719bSwdenk extern int altera_dump( Altera_desc *desc, void *buf, size_t bsize ); 70*c609719bSwdenk extern int altera_info( Altera_desc *desc ); 71*c609719bSwdenk extern int altera_reloc( Altera_desc *desc, ulong reloc_off ); 72*c609719bSwdenk 73*c609719bSwdenk #endif /* _ALTERA_H_ */ 74