10f21f98dSMichal Simek /* 20f21f98dSMichal Simek * Copyright (c) 2011-2013 Xilinx Inc. 30f21f98dSMichal Simek * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 50f21f98dSMichal Simek */ 60f21f98dSMichal Simek 70f21f98dSMichal Simek #include <common.h> 80f21f98dSMichal Simek #include <asm/io.h> 90f21f98dSMichal Simek #include <asm/microblaze_intc.h> 100f21f98dSMichal Simek #include <asm/processor.h> 110f21f98dSMichal Simek #include <watchdog.h> 120f21f98dSMichal Simek 130f21f98dSMichal Simek #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status Mask */ 140f21f98dSMichal Simek #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state Mask */ 150f21f98dSMichal Simek #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 Mask*/ 160f21f98dSMichal Simek #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 Mask */ 170f21f98dSMichal Simek 180f21f98dSMichal Simek struct watchdog_regs { 190f21f98dSMichal Simek u32 twcsr0; /* 0x0 */ 200f21f98dSMichal Simek u32 twcsr1; /* 0x4 */ 210f21f98dSMichal Simek u32 tbr; /* 0x8 */ 220f21f98dSMichal Simek }; 230f21f98dSMichal Simek 240f21f98dSMichal Simek static struct watchdog_regs *watchdog_base = 250f21f98dSMichal Simek (struct watchdog_regs *)CONFIG_WATCHDOG_BASEADDR; 260f21f98dSMichal Simek hw_watchdog_reset(void)270f21f98dSMichal Simekvoid hw_watchdog_reset(void) 280f21f98dSMichal Simek { 290f21f98dSMichal Simek u32 reg; 300f21f98dSMichal Simek 310f21f98dSMichal Simek /* Read the current contents of TCSR0 */ 320f21f98dSMichal Simek reg = readl(&watchdog_base->twcsr0); 330f21f98dSMichal Simek 340f21f98dSMichal Simek /* Clear the watchdog WDS bit */ 350f21f98dSMichal Simek if (reg & (XWT_CSR0_EWDT1_MASK | XWT_CSRX_EWDT2_MASK)) 360f21f98dSMichal Simek writel(reg | XWT_CSR0_WDS_MASK, &watchdog_base->twcsr0); 370f21f98dSMichal Simek } 380f21f98dSMichal Simek hw_watchdog_disable(void)390f21f98dSMichal Simekvoid hw_watchdog_disable(void) 400f21f98dSMichal Simek { 410f21f98dSMichal Simek u32 reg; 420f21f98dSMichal Simek 430f21f98dSMichal Simek /* Read the current contents of TCSR0 */ 440f21f98dSMichal Simek reg = readl(&watchdog_base->twcsr0); 450f21f98dSMichal Simek 460f21f98dSMichal Simek writel(reg & ~XWT_CSR0_EWDT1_MASK, &watchdog_base->twcsr0); 470f21f98dSMichal Simek writel(~XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1); 480f21f98dSMichal Simek 490f21f98dSMichal Simek puts("Watchdog disabled!\n"); 500f21f98dSMichal Simek } 510f21f98dSMichal Simek hw_watchdog_isr(void * arg)520f21f98dSMichal Simekstatic void hw_watchdog_isr(void *arg) 530f21f98dSMichal Simek { 540f21f98dSMichal Simek hw_watchdog_reset(); 550f21f98dSMichal Simek } 560f21f98dSMichal Simek hw_watchdog_init(void)57*8c4dba1aSMichal Simekvoid hw_watchdog_init(void) 580f21f98dSMichal Simek { 590f21f98dSMichal Simek int ret; 600f21f98dSMichal Simek 610f21f98dSMichal Simek writel((XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK | XWT_CSR0_EWDT1_MASK), 620f21f98dSMichal Simek &watchdog_base->twcsr0); 630f21f98dSMichal Simek writel(XWT_CSRX_EWDT2_MASK, &watchdog_base->twcsr1); 640f21f98dSMichal Simek 650f21f98dSMichal Simek ret = install_interrupt_handler(CONFIG_WATCHDOG_IRQ, 660f21f98dSMichal Simek hw_watchdog_isr, NULL); 670f21f98dSMichal Simek if (ret) 68*8c4dba1aSMichal Simek puts("Watchdog IRQ registration failed."); 690f21f98dSMichal Simek } 70