1 /* 2 * Copyright (c) 2014, NVIDIA Corporation. 3 * 4 * SPDX-License-Identifier: GPL-2.0 5 */ 6 7 #ifndef _TEGRA_DISPLAYPORT_H 8 #define _TEGRA_DISPLAYPORT_H 9 10 #include <linux/drm_dp_helper.h> 11 12 struct dpaux_ctlr { 13 u32 reserved0; 14 u32 intr_en_aux; 15 u32 reserved2_4; 16 u32 intr_aux; 17 }; 18 19 #define DPAUX_INTR_EN_AUX 0x1 20 #define DPAUX_INTR_AUX 0x5 21 #define DPAUX_DP_AUXDATA_WRITE_W(i) (0x9 + 4 * (i)) 22 #define DPAUX_DP_AUXDATA_READ_W(i) (0x19 + 4 * (i)) 23 #define DPAUX_DP_AUXADDR 0x29 24 #define DPAUX_DP_AUXCTL 0x2d 25 #define DPAUX_DP_AUXCTL_CMDLEN_SHIFT 0 26 #define DPAUX_DP_AUXCTL_CMDLEN_FIELD 0xff 27 #define DPAUX_DP_AUXCTL_CMD_SHIFT 12 28 #define DPAUX_DP_AUXCTL_CMD_MASK (0xf << 12) 29 #define DPAUX_DP_AUXCTL_CMD_I2CWR (0 << 12) 30 #define DPAUX_DP_AUXCTL_CMD_I2CRD (1 << 12) 31 #define DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT (2 << 12) 32 #define DPAUX_DP_AUXCTL_CMD_MOTWR (4 << 12) 33 #define DPAUX_DP_AUXCTL_CMD_MOTRD (5 << 12) 34 #define DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT (6 << 12) 35 #define DPAUX_DP_AUXCTL_CMD_AUXWR (8 << 12) 36 #define DPAUX_DP_AUXCTL_CMD_AUXRD (9 << 12) 37 #define DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT 16 38 #define DPAUX_DP_AUXCTL_TRANSACTREQ_MASK (0x1 << 16) 39 #define DPAUX_DP_AUXCTL_TRANSACTREQ_DONE (0 << 16) 40 #define DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING (1 << 16) 41 #define DPAUX_DP_AUXCTL_RST_SHIFT 31 42 #define DPAUX_DP_AUXCTL_RST_DEASSERT (0 << 31) 43 #define DPAUX_DP_AUXCTL_RST_ASSERT (1 << 31) 44 #define DPAUX_DP_AUXSTAT 0x31 45 #define DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT 28 46 #define DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG (0 << 28) 47 #define DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED (1 << 28) 48 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT 20 49 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_MASK (0xf << 20) 50 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE (0 << 20) 51 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC (1 << 20) 52 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1 (2 << 20) 53 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND (3 << 20) 54 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS (4 << 20) 55 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH (5 << 20) 56 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1 (6 << 20) 57 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1 (7 << 20) 58 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M (8 << 20) 59 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1 (9 << 20) 60 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2 (10 << 20) 61 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY (11 << 20) 62 #define DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP (12 << 20) 63 #define DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT 16 64 #define DPAUX_DP_AUXSTAT_REPLYTYPE_MASK (0xf << 16) 65 #define DPAUX_DP_AUXSTAT_REPLYTYPE_ACK (0 << 16) 66 #define DPAUX_DP_AUXSTAT_REPLYTYPE_NACK (1 << 16) 67 #define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER (2 << 16) 68 #define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK (4 << 16) 69 #define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER (8 << 16) 70 #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT 11 71 #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING (0 << 11) 72 #define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING (1 << 11) 73 #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT 10 74 #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING (0 << 10) 75 #define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING (1 << 10) 76 #define DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT 9 77 #define DPAUX_DP_AUXSTAT_RX_ERROR_NOT_PENDING (0 << 9) 78 #define DPAUX_DP_AUXSTAT_RX_ERROR_PENDING (1 << 9) 79 #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT 8 80 #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_NOT_PENDING (0 << 8) 81 #define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING (1 << 8) 82 #define DPAUX_DP_AUXSTAT_REPLY_M_SHIFT 0 83 #define DPAUX_DP_AUXSTAT_REPLY_M_MASK (0xff << 0) 84 #define DPAUX_HPD_CONFIG (0x3d) 85 #define DPAUX_HPD_IRQ_CONFIG 0x41 86 #define DPAUX_DP_AUX_CONFIG 0x45 87 #define DPAUX_HYBRID_PADCTL 0x49 88 #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT 15 89 #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE (0 << 15) 90 #define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE (1 << 15) 91 #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT 14 92 #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE (0 << 14) 93 #define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE (1 << 14) 94 #define DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT 12 95 #define DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT_MASK (0x3 << 12) 96 #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_60 (0 << 12) 97 #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_64 (1 << 12) 98 #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 (2 << 12) 99 #define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_56 (3 << 12) 100 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT 8 101 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT_MASK (0x7 << 8) 102 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_78 (0 << 8) 103 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_60 (1 << 8) 104 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_54 (2 << 8) 105 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_45 (3 << 8) 106 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 (4 << 8) 107 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42 (5 << 8) 108 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_39 (6 << 8) 109 #define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_34 (7 << 8) 110 #define DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT 2 111 #define DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT_MASK (0x3f << 2) 112 #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT 1 113 #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE (0 << 1) 114 #define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE (1 << 1) 115 #define DPAUX_HYBRID_PADCTL_MODE_SHIFT 0 116 #define DPAUX_HYBRID_PADCTL_MODE_AUX 0 117 #define DPAUX_HYBRID_PADCTL_MODE_I2C 1 118 #define DPAUX_HYBRID_SPARE 0x4d 119 #define DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP 0 120 #define DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN 1 121 122 #define DP_AUX_DEFER_MAX_TRIES 7 123 #define DP_AUX_TIMEOUT_MAX_TRIES 2 124 #define DP_POWER_ON_MAX_TRIES 3 125 126 #define DP_AUX_MAX_BYTES 16 127 128 #define DP_AUX_TIMEOUT_MS 40 129 #define DP_DPCP_RETRY_SLEEP_NS 400 130 131 /* DPCD definitions which are not defined in drm_dp_helper.h */ 132 #define DP_DPCD_REV_MAJOR_SHIFT 4 133 #define DP_DPCD_REV_MAJOR_MASK (0xf << 4) 134 #define DP_DPCD_REV_MINOR_SHIFT 0 135 #define DP_DPCD_REV_MINOR_MASK 0xf 136 137 #define DP_MAX_LINK_RATE_VAL_1_62_GPBS 0x6 138 #define DP_MAX_LINK_RATE_VAL_2_70_GPBS 0xa 139 #define DP_MAX_LINK_RATE_VAL_5_40_GPBS 0x4 140 141 #define DP_MAX_LANE_COUNT_LANE_1 0x1 142 #define DP_MAX_LANE_COUNT_LANE_2 0x2 143 #define DP_MAX_LANE_COUNT_LANE_4 0x4 144 #define DP_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (1 << 7) 145 146 #define DP_MAX_DOWNSPREAD_VAL_NONE 0 147 #define DP_MAX_DOWNSPREAD_VAL_0_5_PCT 1 148 #define DP_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T (1 << 6) 149 150 #define DP_EDP_CONFIGURATION_CAP_ASC_RESET_YES 1 151 #define DP_EDP_CONFIGURATION_CAP_FRAMING_CHANGE_YES (1 << 1) 152 153 #define DP_LANE_COUNT_SET_ENHANCEDFRAMING_T (1 << 7) 154 155 #define DP_TRAINING_PATTERN_SET_SC_DISABLED_T (1 << 5) 156 157 #define DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_DISABLE 0 158 #define DP_MAIN_LINK_CHANNEL_CODING_SET_ASC_RESET_ENABLE 1 159 160 #define NV_DPCD_TRAINING_LANE0_1_SET2 0x10f 161 #define NV_DPCD_TRAINING_LANE2_3_SET2 0x110 162 #define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T (1 << 2) 163 #define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T (1 << 6) 164 165 #define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0 166 #define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000) 167 #define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001) 168 #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1 169 #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1) 170 #define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1) 171 #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2 172 #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2) 173 #define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2) 174 #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4 175 #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4) 176 #define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4) 177 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5 178 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5) 179 #define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5) 180 #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6 181 #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6) 182 #define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6) 183 184 #endif 185