1 /* 2 * Copyright (c) 2011 The Chromium OS Authors. 3 * SPDX-License-Identifier: GPL-2.0+ 4 */ 5 6 #include <common.h> 7 #include <fdtdec.h> 8 #include <lcd.h> 9 10 #include <asm/system.h> 11 #include <asm/gpio.h> 12 #include <asm/io.h> 13 14 #include <asm/arch/clock.h> 15 #include <asm/arch/funcmux.h> 16 #include <asm/arch/pinmux.h> 17 #include <asm/arch/pwm.h> 18 #include <asm/arch/display.h> 19 #include <asm/arch-tegra/timer.h> 20 21 DECLARE_GLOBAL_DATA_PTR; 22 23 /* These are the stages we go throuh in enabling the LCD */ 24 enum stage_t { 25 STAGE_START, 26 STAGE_PANEL_VDD, 27 STAGE_LVDS, 28 STAGE_BACKLIGHT_VDD, 29 STAGE_PWM, 30 STAGE_BACKLIGHT_EN, 31 STAGE_DONE, 32 }; 33 34 static enum stage_t stage; /* Current stage we are at */ 35 static unsigned long timer_next; /* Time we can move onto next stage */ 36 37 /* Our LCD config, set up in handle_stage() */ 38 static struct fdt_panel_config config; 39 struct fdt_disp_config *disp_config; /* Display controller config */ 40 static struct fdt_disp_config dconfig; 41 42 enum { 43 /* Maximum LCD size we support */ 44 LCD_MAX_WIDTH = 1366, 45 LCD_MAX_HEIGHT = 768, 46 LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */ 47 }; 48 49 vidinfo_t panel_info = { 50 /* Insert a value here so that we don't end up in the BSS */ 51 .vl_col = -1, 52 }; 53 54 static void update_window(struct dc_ctlr *dc, struct disp_ctl_win *win) 55 { 56 unsigned h_dda, v_dda; 57 unsigned long val; 58 59 val = readl(&dc->cmd.disp_win_header); 60 val |= WINDOW_A_SELECT; 61 writel(val, &dc->cmd.disp_win_header); 62 63 writel(win->fmt, &dc->win.color_depth); 64 65 clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK, 66 BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT); 67 68 val = win->out_x << H_POSITION_SHIFT; 69 val |= win->out_y << V_POSITION_SHIFT; 70 writel(val, &dc->win.pos); 71 72 val = win->out_w << H_SIZE_SHIFT; 73 val |= win->out_h << V_SIZE_SHIFT; 74 writel(val, &dc->win.size); 75 76 val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT; 77 val |= win->h << V_PRESCALED_SIZE_SHIFT; 78 writel(val, &dc->win.prescaled_size); 79 80 writel(0, &dc->win.h_initial_dda); 81 writel(0, &dc->win.v_initial_dda); 82 83 h_dda = (win->w * 0x1000) / max(win->out_w - 1, 1U); 84 v_dda = (win->h * 0x1000) / max(win->out_h - 1, 1U); 85 86 val = h_dda << H_DDA_INC_SHIFT; 87 val |= v_dda << V_DDA_INC_SHIFT; 88 writel(val, &dc->win.dda_increment); 89 90 writel(win->stride, &dc->win.line_stride); 91 writel(0, &dc->win.buf_stride); 92 93 val = WIN_ENABLE; 94 if (win->bpp < 24) 95 val |= COLOR_EXPAND; 96 writel(val, &dc->win.win_opt); 97 98 writel((unsigned long)win->phys_addr, &dc->winbuf.start_addr); 99 writel(win->x, &dc->winbuf.addr_h_offset); 100 writel(win->y, &dc->winbuf.addr_v_offset); 101 102 writel(0xff00, &dc->win.blend_nokey); 103 writel(0xff00, &dc->win.blend_1win); 104 105 val = GENERAL_ACT_REQ | WIN_A_ACT_REQ; 106 val |= GENERAL_UPDATE | WIN_A_UPDATE; 107 writel(val, &dc->cmd.state_ctrl); 108 } 109 110 static void write_pair(struct fdt_disp_config *config, int item, u32 *reg) 111 { 112 writel(config->horiz_timing[item] | 113 (config->vert_timing[item] << 16), reg); 114 } 115 116 static int update_display_mode(struct dc_disp_reg *disp, 117 struct fdt_disp_config *config) 118 { 119 unsigned long val; 120 unsigned long rate; 121 unsigned long div; 122 123 writel(0x0, &disp->disp_timing_opt); 124 write_pair(config, FDT_LCD_TIMING_REF_TO_SYNC, &disp->ref_to_sync); 125 write_pair(config, FDT_LCD_TIMING_SYNC_WIDTH, &disp->sync_width); 126 write_pair(config, FDT_LCD_TIMING_BACK_PORCH, &disp->back_porch); 127 write_pair(config, FDT_LCD_TIMING_FRONT_PORCH, &disp->front_porch); 128 129 writel(config->width | (config->height << 16), &disp->disp_active); 130 131 val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT; 132 val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT; 133 writel(val, &disp->data_enable_opt); 134 135 val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT; 136 val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT; 137 val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT; 138 writel(val, &disp->disp_interface_ctrl); 139 140 /* 141 * The pixel clock divider is in 7.1 format (where the bottom bit 142 * represents 0.5). Here we calculate the divider needed to get from 143 * the display clock (typically 600MHz) to the pixel clock. We round 144 * up or down as requried. 145 */ 146 rate = clock_get_periph_rate(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL); 147 div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2; 148 debug("Display clock %lu, divider %lu\n", rate, div); 149 150 writel(0x00010001, &disp->shift_clk_opt); 151 152 val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT; 153 val |= div << SHIFT_CLK_DIVIDER_SHIFT; 154 writel(val, &disp->disp_clk_ctrl); 155 156 return 0; 157 } 158 159 /* Start up the display and turn on power to PWMs */ 160 static void basic_init(struct dc_cmd_reg *cmd) 161 { 162 u32 val; 163 164 writel(0x00000100, &cmd->gen_incr_syncpt_ctrl); 165 writel(0x0000011a, &cmd->cont_syncpt_vsync); 166 writel(0x00000000, &cmd->int_type); 167 writel(0x00000000, &cmd->int_polarity); 168 writel(0x00000000, &cmd->int_mask); 169 writel(0x00000000, &cmd->int_enb); 170 171 val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE; 172 val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE; 173 val |= PM1_ENABLE; 174 writel(val, &cmd->disp_pow_ctrl); 175 176 val = readl(&cmd->disp_cmd); 177 val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT; 178 writel(val, &cmd->disp_cmd); 179 } 180 181 static void basic_init_timer(struct dc_disp_reg *disp) 182 { 183 writel(0x00000020, &disp->mem_high_pri); 184 writel(0x00000001, &disp->mem_high_pri_timer); 185 } 186 187 static const u32 rgb_enb_tab[PIN_REG_COUNT] = { 188 0x00000000, 189 0x00000000, 190 0x00000000, 191 0x00000000, 192 }; 193 194 static const u32 rgb_polarity_tab[PIN_REG_COUNT] = { 195 0x00000000, 196 0x01000000, 197 0x00000000, 198 0x00000000, 199 }; 200 201 static const u32 rgb_data_tab[PIN_REG_COUNT] = { 202 0x00000000, 203 0x00000000, 204 0x00000000, 205 0x00000000, 206 }; 207 208 static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = { 209 0x00000000, 210 0x00000000, 211 0x00000000, 212 0x00000000, 213 0x00210222, 214 0x00002200, 215 0x00020000, 216 }; 217 218 static void rgb_enable(struct dc_com_reg *com) 219 { 220 int i; 221 222 for (i = 0; i < PIN_REG_COUNT; i++) { 223 writel(rgb_enb_tab[i], &com->pin_output_enb[i]); 224 writel(rgb_polarity_tab[i], &com->pin_output_polarity[i]); 225 writel(rgb_data_tab[i], &com->pin_output_data[i]); 226 } 227 228 for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++) 229 writel(rgb_sel_tab[i], &com->pin_output_sel[i]); 230 } 231 232 static int setup_window(struct disp_ctl_win *win, 233 struct fdt_disp_config *config) 234 { 235 win->x = 0; 236 win->y = 0; 237 win->w = config->width; 238 win->h = config->height; 239 win->out_x = 0; 240 win->out_y = 0; 241 win->out_w = config->width; 242 win->out_h = config->height; 243 win->phys_addr = config->frame_buffer; 244 win->stride = config->width * (1 << config->log2_bpp) / 8; 245 debug("%s: depth = %d\n", __func__, config->log2_bpp); 246 switch (config->log2_bpp) { 247 case 5: 248 case 24: 249 win->fmt = COLOR_DEPTH_R8G8B8A8; 250 win->bpp = 32; 251 break; 252 case 4: 253 win->fmt = COLOR_DEPTH_B5G6R5; 254 win->bpp = 16; 255 break; 256 257 default: 258 debug("Unsupported LCD bit depth"); 259 return -1; 260 } 261 262 return 0; 263 } 264 265 /** 266 * Return the current display configuration 267 * 268 * @return pointer to display configuration, or NULL if there is no valid 269 * config 270 */ 271 struct fdt_disp_config *tegra_display_get_config(void) 272 { 273 return dconfig.valid ? &dconfig : NULL; 274 } 275 276 static void debug_timing(const char *name, unsigned int timing[]) 277 { 278 #ifdef DEBUG 279 int i; 280 281 debug("%s timing: ", name); 282 for (i = 0; i < FDT_LCD_TIMING_COUNT; i++) 283 debug("%d ", timing[i]); 284 debug("\n"); 285 #endif 286 } 287 288 /** 289 * Decode panel information from the fdt, according to a standard binding 290 * 291 * @param blob fdt blob 292 * @param node offset of fdt node to read from 293 * @param config structure to store fdt config into 294 * @return 0 if ok, -ve on error 295 */ 296 static int tegra_decode_panel(const void *blob, int node, 297 struct fdt_disp_config *config) 298 { 299 int front, back, ref; 300 301 config->width = fdtdec_get_int(blob, node, "xres", -1); 302 config->height = fdtdec_get_int(blob, node, "yres", -1); 303 config->pixel_clock = fdtdec_get_int(blob, node, "clock", 0); 304 if (!config->pixel_clock || config->width == -1 || 305 config->height == -1) { 306 debug("%s: Pixel parameters missing\n", __func__); 307 return -FDT_ERR_NOTFOUND; 308 } 309 310 back = fdtdec_get_int(blob, node, "left-margin", -1); 311 front = fdtdec_get_int(blob, node, "right-margin", -1); 312 ref = fdtdec_get_int(blob, node, "hsync-len", -1); 313 if ((back | front | ref) == -1) { 314 debug("%s: Horizontal parameters missing\n", __func__); 315 return -FDT_ERR_NOTFOUND; 316 } 317 318 /* Use a ref-to-sync of 1 always, and take this from the front porch */ 319 config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1; 320 config->horiz_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref; 321 config->horiz_timing[FDT_LCD_TIMING_BACK_PORCH] = back; 322 config->horiz_timing[FDT_LCD_TIMING_FRONT_PORCH] = front - 323 config->horiz_timing[FDT_LCD_TIMING_REF_TO_SYNC]; 324 debug_timing("horiz", config->horiz_timing); 325 326 back = fdtdec_get_int(blob, node, "upper-margin", -1); 327 front = fdtdec_get_int(blob, node, "lower-margin", -1); 328 ref = fdtdec_get_int(blob, node, "vsync-len", -1); 329 if ((back | front | ref) == -1) { 330 debug("%s: Vertical parameters missing\n", __func__); 331 return -FDT_ERR_NOTFOUND; 332 } 333 334 config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC] = 1; 335 config->vert_timing[FDT_LCD_TIMING_SYNC_WIDTH] = ref; 336 config->vert_timing[FDT_LCD_TIMING_BACK_PORCH] = back; 337 config->vert_timing[FDT_LCD_TIMING_FRONT_PORCH] = front - 338 config->vert_timing[FDT_LCD_TIMING_REF_TO_SYNC]; 339 debug_timing("vert", config->vert_timing); 340 341 return 0; 342 } 343 344 /** 345 * Decode the display controller information from the fdt. 346 * 347 * @param blob fdt blob 348 * @param config structure to store fdt config into 349 * @return 0 if ok, -ve on error 350 */ 351 static int tegra_display_decode_config(const void *blob, 352 struct fdt_disp_config *config) 353 { 354 int node, rgb; 355 int bpp, bit; 356 357 /* TODO: Support multiple controllers */ 358 node = fdtdec_next_compatible(blob, 0, COMPAT_NVIDIA_TEGRA20_DC); 359 if (node < 0) { 360 debug("%s: Cannot find display controller node in fdt\n", 361 __func__); 362 return node; 363 } 364 config->disp = (struct disp_ctlr *)fdtdec_get_addr(blob, node, "reg"); 365 if (!config->disp) { 366 debug("%s: No display controller address\n", __func__); 367 return -1; 368 } 369 370 rgb = fdt_subnode_offset(blob, node, "rgb"); 371 372 config->panel_node = fdtdec_lookup_phandle(blob, rgb, "nvidia,panel"); 373 if (config->panel_node < 0) { 374 debug("%s: Cannot find panel information\n", __func__); 375 return -1; 376 } 377 378 if (tegra_decode_panel(blob, config->panel_node, config)) { 379 debug("%s: Failed to decode panel information\n", __func__); 380 return -1; 381 } 382 383 bpp = fdtdec_get_int(blob, config->panel_node, "nvidia,bits-per-pixel", 384 -1); 385 bit = ffs(bpp) - 1; 386 if (bpp == (1 << bit)) 387 config->log2_bpp = bit; 388 else 389 config->log2_bpp = bpp; 390 if (bpp == -1) { 391 debug("%s: Pixel bpp parameters missing\n", __func__); 392 return -FDT_ERR_NOTFOUND; 393 } 394 config->bpp = bpp; 395 396 config->valid = 1; /* we have a valid configuration */ 397 398 return 0; 399 } 400 401 /** 402 * Register a new display based on device tree configuration. 403 * 404 * The frame buffer can be positioned by U-Boot or overriden by the fdt. 405 * You should pass in the U-Boot address here, and check the contents of 406 * struct fdt_disp_config to see what was actually chosen. 407 * 408 * @param blob Device tree blob 409 * @param default_lcd_base Default address of LCD frame buffer 410 * @return 0 if ok, -1 on error (unsupported bits per pixel) 411 */ 412 static int tegra_display_probe(const void *blob, void *default_lcd_base) 413 { 414 struct disp_ctl_win window; 415 struct dc_ctlr *dc; 416 417 if (tegra_display_decode_config(blob, &dconfig)) 418 return -1; 419 420 dconfig.frame_buffer = (u32)default_lcd_base; 421 422 dc = (struct dc_ctlr *)dconfig.disp; 423 424 /* 425 * A header file for clock constants was NAKed upstream. 426 * TODO: Put this into the FDT and fdt_lcd struct when we have clock 427 * support there 428 */ 429 clock_start_periph_pll(PERIPH_ID_HOST1X, CLOCK_ID_PERIPH, 430 144 * 1000000); 431 clock_start_periph_pll(PERIPH_ID_DISP1, CLOCK_ID_CGENERAL, 432 600 * 1000000); 433 basic_init(&dc->cmd); 434 basic_init_timer(&dc->disp); 435 rgb_enable(&dc->com); 436 437 if (dconfig.pixel_clock) 438 update_display_mode(&dc->disp, &dconfig); 439 440 if (setup_window(&window, &dconfig)) 441 return -1; 442 443 update_window(dc, &window); 444 445 return 0; 446 } 447 448 static void update_panel_size(struct fdt_disp_config *config) 449 { 450 panel_info.vl_col = config->width; 451 panel_info.vl_row = config->height; 452 panel_info.vl_bpix = config->log2_bpp; 453 } 454 455 /* 456 * Main init function called by lcd driver. 457 * Inits and then prints test pattern if required. 458 */ 459 460 void lcd_ctrl_init(void *lcdbase) 461 { 462 int type = DCACHE_OFF; 463 int size; 464 465 assert(disp_config); 466 467 /* Make sure that we can acommodate the selected LCD */ 468 assert(disp_config->width <= LCD_MAX_WIDTH); 469 assert(disp_config->height <= LCD_MAX_HEIGHT); 470 assert(disp_config->log2_bpp <= LCD_MAX_LOG2_BPP); 471 if (disp_config->width <= LCD_MAX_WIDTH 472 && disp_config->height <= LCD_MAX_HEIGHT 473 && disp_config->log2_bpp <= LCD_MAX_LOG2_BPP) 474 update_panel_size(disp_config); 475 size = lcd_get_size(&lcd_line_length); 476 477 /* Set up the LCD caching as requested */ 478 if (config.cache_type & FDT_LCD_CACHE_WRITE_THROUGH) 479 type = DCACHE_WRITETHROUGH; 480 else if (config.cache_type & FDT_LCD_CACHE_WRITE_BACK) 481 type = DCACHE_WRITEBACK; 482 mmu_set_region_dcache_behaviour(disp_config->frame_buffer, size, type); 483 484 /* Enable flushing after LCD writes if requested */ 485 lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH); 486 487 debug("LCD frame buffer at %pa\n", &disp_config->frame_buffer); 488 } 489 490 ulong calc_fbsize(void) 491 { 492 return (panel_info.vl_col * panel_info.vl_row * 493 NBITS(panel_info.vl_bpix)) / 8; 494 } 495 496 void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) 497 { 498 } 499 500 void tegra_lcd_early_init(const void *blob) 501 { 502 /* 503 * Go with the maximum size for now. We will fix this up after 504 * relocation. These values are only used for memory alocation. 505 */ 506 panel_info.vl_col = LCD_MAX_WIDTH; 507 panel_info.vl_row = LCD_MAX_HEIGHT; 508 panel_info.vl_bpix = LCD_MAX_LOG2_BPP; 509 } 510 511 /** 512 * Decode the panel information from the fdt. 513 * 514 * @param blob fdt blob 515 * @param config structure to store fdt config into 516 * @return 0 if ok, -ve on error 517 */ 518 static int fdt_decode_lcd(const void *blob, struct fdt_panel_config *config) 519 { 520 int display_node; 521 522 disp_config = tegra_display_get_config(); 523 if (!disp_config) { 524 debug("%s: Display controller is not configured\n", __func__); 525 return -1; 526 } 527 display_node = disp_config->panel_node; 528 if (display_node < 0) { 529 debug("%s: No panel configuration available\n", __func__); 530 return -1; 531 } 532 533 config->pwm_channel = pwm_request(blob, display_node, "nvidia,pwm"); 534 if (config->pwm_channel < 0) { 535 debug("%s: Unable to request PWM channel\n", __func__); 536 return -1; 537 } 538 539 config->cache_type = fdtdec_get_int(blob, display_node, 540 "nvidia,cache-type", 541 FDT_LCD_CACHE_WRITE_BACK_FLUSH); 542 543 /* These GPIOs are all optional */ 544 gpio_request_by_name_nodev(blob, display_node, 545 "nvidia,backlight-enable-gpios", 0, 546 &config->backlight_en, GPIOD_IS_OUT); 547 gpio_request_by_name_nodev(blob, display_node, 548 "nvidia,lvds-shutdown-gpios", 0, 549 &config->lvds_shutdown, GPIOD_IS_OUT); 550 gpio_request_by_name_nodev(blob, display_node, 551 "nvidia,backlight-vdd-gpios", 0, 552 &config->backlight_vdd, GPIOD_IS_OUT); 553 gpio_request_by_name_nodev(blob, display_node, 554 "nvidia,panel-vdd-gpios", 0, 555 &config->panel_vdd, GPIOD_IS_OUT); 556 557 return fdtdec_get_int_array(blob, display_node, "nvidia,panel-timings", 558 config->panel_timings, FDT_LCD_TIMINGS); 559 } 560 561 /** 562 * Handle the next stage of device init 563 */ 564 static int handle_stage(const void *blob) 565 { 566 debug("%s: stage %d\n", __func__, stage); 567 568 /* do the things for this stage */ 569 switch (stage) { 570 case STAGE_START: 571 /* Initialize the Tegra display controller */ 572 if (tegra_display_probe(gd->fdt_blob, (void *)gd->fb_base)) { 573 printf("%s: Failed to probe display driver\n", 574 __func__); 575 return -1; 576 } 577 578 /* get panel details */ 579 if (fdt_decode_lcd(blob, &config)) { 580 printf("No valid LCD information in device tree\n"); 581 return -1; 582 } 583 584 /* 585 * It is possible that the FDT has requested that the LCD be 586 * disabled. We currently don't support this. It would require 587 * changes to U-Boot LCD subsystem to have LCD support 588 * compiled in but not used. An easier option might be to 589 * still have a frame buffer, but leave the backlight off and 590 * remove all mention of lcd in the stdout environment 591 * variable. 592 */ 593 594 funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT); 595 break; 596 case STAGE_PANEL_VDD: 597 if (dm_gpio_is_valid(&config.panel_vdd)) 598 dm_gpio_set_value(&config.panel_vdd, 1); 599 break; 600 case STAGE_LVDS: 601 if (dm_gpio_is_valid(&config.lvds_shutdown)) 602 dm_gpio_set_value(&config.lvds_shutdown, 1); 603 break; 604 case STAGE_BACKLIGHT_VDD: 605 if (dm_gpio_is_valid(&config.backlight_vdd)) 606 dm_gpio_set_value(&config.backlight_vdd, 1); 607 break; 608 case STAGE_PWM: 609 /* Enable PWM at 15/16 high, 32768 Hz with divider 1 */ 610 pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM); 611 pinmux_tristate_disable(PMUX_PINGRP_GPU); 612 613 pwm_enable(config.pwm_channel, 32768, 0xdf, 1); 614 break; 615 case STAGE_BACKLIGHT_EN: 616 if (dm_gpio_is_valid(&config.backlight_en)) 617 dm_gpio_set_value(&config.backlight_en, 1); 618 break; 619 case STAGE_DONE: 620 break; 621 } 622 623 /* set up timer for next stage */ 624 timer_next = timer_get_us(); 625 if (stage < FDT_LCD_TIMINGS) 626 timer_next += config.panel_timings[stage] * 1000; 627 628 /* move to next stage */ 629 stage++; 630 return 0; 631 } 632 633 int tegra_lcd_check_next_stage(const void *blob, int wait) 634 { 635 if (stage == STAGE_DONE) 636 return 0; 637 638 do { 639 /* wait if we need to */ 640 debug("%s: stage %d\n", __func__, stage); 641 if (stage != STAGE_START) { 642 int delay = timer_next - timer_get_us(); 643 644 if (delay > 0) { 645 if (wait) 646 udelay(delay); 647 else 648 return 0; 649 } 650 } 651 652 if (handle_stage(blob)) 653 return -1; 654 } while (wait && stage != STAGE_DONE); 655 if (stage == STAGE_DONE) 656 debug("%s: LCD init complete\n", __func__); 657 658 return 0; 659 } 660 661 void lcd_enable(void) 662 { 663 /* 664 * Backlight and power init will be done separately in 665 * tegra_lcd_check_next_stage(), which should be called in 666 * board_late_init(). 667 * 668 * U-Boot code supports only colour depth, selected at compile time. 669 * The device tree setting should match this. Otherwise the display 670 * will not look right, and U-Boot may crash. 671 */ 672 if (disp_config->log2_bpp != LCD_BPP) { 673 printf("%s: Error: LCD depth configured in FDT (%d = %dbpp)" 674 " must match setting of LCD_BPP (%d)\n", __func__, 675 disp_config->log2_bpp, disp_config->bpp, LCD_BPP); 676 } 677 } 678