1 /* 2 * Timing controller driver for Allwinner SoCs. 3 * 4 * (C) Copyright 2013-2014 Luc Verhaegen <libv@skynet.be> 5 * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> 6 * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <common.h> 12 13 #include <asm/arch/lcdc.h> 14 #include <asm/io.h> 15 16 #include "../videomodes.h" 17 18 static int lcdc_get_clk_delay(const struct ctfb_res_modes *mode, int tcon) 19 { 20 int delay; 21 22 delay = mode->lower_margin + mode->vsync_len + 23 mode->upper_margin; 24 if (mode->vmode == FB_VMODE_INTERLACED) 25 delay /= 2; 26 if (tcon == 1) 27 delay -= 2; 28 29 return (delay > 30) ? 30 : delay; 30 } 31 32 void lcdc_init(struct sunxi_lcdc_reg * const lcdc) 33 { 34 /* Init lcdc */ 35 writel(0, &lcdc->ctrl); /* Disable tcon */ 36 writel(0, &lcdc->int0); /* Disable all interrupts */ 37 38 /* Disable tcon0 dot clock */ 39 clrbits_le32(&lcdc->tcon0_dclk, SUNXI_LCDC_TCON0_DCLK_ENABLE); 40 41 /* Set all io lines to tristate */ 42 writel(0xffffffff, &lcdc->tcon0_io_tristate); 43 writel(0xffffffff, &lcdc->tcon1_io_tristate); 44 } 45 46 void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth) 47 { 48 setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE); 49 #ifdef CONFIG_VIDEO_LCD_IF_LVDS 50 setbits_le32(&lcdc->tcon0_lvds_intf, SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE); 51 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0); 52 #ifdef CONFIG_SUNXI_GEN_SUN6I 53 udelay(2); /* delay at least 1200 ns */ 54 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB); 55 udelay(2); /* delay at least 1200 ns */ 56 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC); 57 if (depth == 18) 58 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7)); 59 else 60 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf)); 61 #else 62 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); 63 udelay(2); /* delay at least 1200 ns */ 64 setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1); 65 udelay(1); /* delay at least 120 ns */ 66 setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2); 67 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); 68 #endif 69 #endif 70 } 71 72 void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc, 73 const struct ctfb_res_modes *mode, 74 int clk_div, bool for_ext_vga_dac, 75 int depth, int dclk_phase) 76 { 77 int bp, clk_delay, total, val; 78 79 /* Use tcon0 */ 80 clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK, 81 SUNXI_LCDC_CTRL_IO_MAP_TCON0); 82 83 clk_delay = lcdc_get_clk_delay(mode, 0); 84 writel(SUNXI_LCDC_TCON0_CTRL_ENABLE | 85 SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon0_ctrl); 86 87 writel(SUNXI_LCDC_TCON0_DCLK_ENABLE | 88 SUNXI_LCDC_TCON0_DCLK_DIV(clk_div), &lcdc->tcon0_dclk); 89 90 writel(SUNXI_LCDC_X(mode->xres) | 91 SUNXI_LCDC_Y(mode->yres), &lcdc->tcon0_timing_active); 92 93 bp = mode->hsync_len + mode->left_margin; 94 total = mode->xres + mode->right_margin + bp; 95 writel(SUNXI_LCDC_TCON0_TIMING_H_TOTAL(total) | 96 SUNXI_LCDC_TCON0_TIMING_H_BP(bp), &lcdc->tcon0_timing_h); 97 98 bp = mode->vsync_len + mode->upper_margin; 99 total = mode->yres + mode->lower_margin + bp; 100 writel(SUNXI_LCDC_TCON0_TIMING_V_TOTAL(total) | 101 SUNXI_LCDC_TCON0_TIMING_V_BP(bp), &lcdc->tcon0_timing_v); 102 103 #ifdef CONFIG_VIDEO_LCD_IF_PARALLEL 104 writel(SUNXI_LCDC_X(mode->hsync_len) | 105 SUNXI_LCDC_Y(mode->vsync_len), &lcdc->tcon0_timing_sync); 106 107 writel(0, &lcdc->tcon0_hv_intf); 108 writel(0, &lcdc->tcon0_cpu_intf); 109 #endif 110 #ifdef CONFIG_VIDEO_LCD_IF_LVDS 111 val = (depth == 18) ? 1 : 0; 112 writel(SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(val) | 113 SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0, &lcdc->tcon0_lvds_intf); 114 #endif 115 116 if (depth == 18 || depth == 16) { 117 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[0]); 118 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[1]); 119 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[2]); 120 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[3]); 121 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[4]); 122 writel(SUNXI_LCDC_TCON0_FRM_SEED, &lcdc->tcon0_frm_seed[5]); 123 writel(SUNXI_LCDC_TCON0_FRM_TAB0, &lcdc->tcon0_frm_table[0]); 124 writel(SUNXI_LCDC_TCON0_FRM_TAB1, &lcdc->tcon0_frm_table[1]); 125 writel(SUNXI_LCDC_TCON0_FRM_TAB2, &lcdc->tcon0_frm_table[2]); 126 writel(SUNXI_LCDC_TCON0_FRM_TAB3, &lcdc->tcon0_frm_table[3]); 127 writel(((depth == 18) ? 128 SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 : 129 SUNXI_LCDC_TCON0_FRM_CTRL_RGB565), 130 &lcdc->tcon0_frm_ctrl); 131 } 132 133 val = SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(dclk_phase); 134 if (!(mode->sync & FB_SYNC_HOR_HIGH_ACT)) 135 val |= SUNXI_LCDC_TCON_HSYNC_MASK; 136 if (!(mode->sync & FB_SYNC_VERT_HIGH_ACT)) 137 val |= SUNXI_LCDC_TCON_VSYNC_MASK; 138 139 #ifdef CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH 140 if (for_ext_vga_dac) 141 val = 0; 142 #endif 143 writel(val, &lcdc->tcon0_io_polarity); 144 145 writel(0, &lcdc->tcon0_io_tristate); 146 } 147 148 void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc, 149 const struct ctfb_res_modes *mode, 150 bool ext_hvsync, bool is_composite) 151 { 152 int bp, clk_delay, total, val, yres; 153 154 /* Use tcon1 */ 155 clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK, 156 SUNXI_LCDC_CTRL_IO_MAP_TCON1); 157 158 clk_delay = lcdc_get_clk_delay(mode, 1); 159 writel(SUNXI_LCDC_TCON1_CTRL_ENABLE | 160 ((mode->vmode == FB_VMODE_INTERLACED) ? 161 SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) | 162 SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl); 163 164 yres = mode->yres; 165 if (mode->vmode == FB_VMODE_INTERLACED) 166 yres /= 2; 167 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres), 168 &lcdc->tcon1_timing_source); 169 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres), 170 &lcdc->tcon1_timing_scale); 171 writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres), 172 &lcdc->tcon1_timing_out); 173 174 bp = mode->hsync_len + mode->left_margin; 175 total = mode->xres + mode->right_margin + bp; 176 writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) | 177 SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h); 178 179 bp = mode->vsync_len + mode->upper_margin; 180 total = mode->yres + mode->lower_margin + bp; 181 if (mode->vmode == FB_VMODE_NONINTERLACED) 182 total *= 2; 183 writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) | 184 SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v); 185 186 writel(SUNXI_LCDC_X(mode->hsync_len) | 187 SUNXI_LCDC_Y(mode->vsync_len), &lcdc->tcon1_timing_sync); 188 189 if (ext_hvsync) { 190 val = 0; 191 if (mode->sync & FB_SYNC_HOR_HIGH_ACT) 192 val |= SUNXI_LCDC_TCON_HSYNC_MASK; 193 if (mode->sync & FB_SYNC_VERT_HIGH_ACT) 194 val |= SUNXI_LCDC_TCON_VSYNC_MASK; 195 writel(val, &lcdc->tcon1_io_polarity); 196 197 clrbits_le32(&lcdc->tcon1_io_tristate, 198 SUNXI_LCDC_TCON_VSYNC_MASK | 199 SUNXI_LCDC_TCON_HSYNC_MASK); 200 } 201 202 #ifdef CONFIG_MACH_SUN5I 203 if (is_composite) 204 clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK, 205 SUNXI_LCDC_MUX_CTRL_SRC0(1)); 206 #endif 207 } 208