1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Wenping Zhang <wenping.zhang@rock-chips.com> 6 */ 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <dm/pinctrl.h> 11 #include <pwm.h> 12 #include <regmap.h> 13 #include <syscon.h> 14 #include <asm/arch/clock.h> 15 #include <asm/io.h> 16 #include <syscon.h> 17 #include <linux/io.h> 18 #include "rk_ebc.h" 19 #ifdef CONFIG_IRQ 20 #include <irq-generic.h> 21 #endif 22 23 struct ebc_tcon_priv { 24 struct udevice *dev; 25 void __iomem *reg; 26 u32 *regcache; 27 u32 reg_len; 28 void *grf; 29 void *pmugrf; 30 }; 31 32 #define msleep(a) udelay((a) * 1000) 33 #define HIWORD_UPDATE(x, l, h) (((x) << (l)) | (GENMASK(h, l) << 16)) 34 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) 35 36 #define REG_LOAD_GLOBAL_EN 0x1 37 38 /* ebc register define */ 39 #define EBC_DSP_START 0x0000 //Frame statrt register 40 #define EBC_EPD_CTRL 0x0004 //EPD control register 41 #define EBC_DSP_CTRL 0x0008 //Display control register 42 #define EBC_DSP_HTIMING0 0x000c //H-Timing setting register0 43 #define EBC_DSP_HTIMING1 0x0010 //H-Timing setting register1 44 #define EBC_DSP_VTIMING0 0x0014 //V-Timing setting register0 45 #define EBC_DSP_VTIMING1 0x0018 //V-Timing setting register1 46 #define EBC_DSP_ACT_INFO 0x001c //ACTIVE width/height 47 #define EBC_WIN_CTRL 0x0020 //Window ctrl 48 #define EBC_WIN_MST0 0x0024 //Current win memory start 49 #define EBC_WIN_MST1 0x0028 //Next win memory start 50 #define EBC_WIN_VIR 0x002c //Window vir width/height 51 #define EBC_WIN_ACT 0x0030 //Window act width/height 52 #define EBC_WIN_DSP 0x0034 //Window dsp width/height 53 #define EBC_WIN_DSP_ST 0x0038 //Window display start point 54 #define EBC_INT_STATUS 0x003c //Interrupt register 55 #define EBC_VCOM0 0x0040 //VCOM setting register0 56 #define EBC_VCOM1 0x0044 //VCOM setting register1 57 #define EBC_VCOM2 0x0048 //VCOM setting register2 58 #define EBC_VCOM3 0x004c //VCOM setting register3 59 #define EBC_CONFIG_DONE 0x0050 //Config done register 60 #define EBC_VNUM 0x0054 //Line flag num 61 #define EBC_WIN_MST2 0x0058 //Framecount memory start 62 #define EBC_LUT_DATA_ADDR 0x1000 //lut data address 63 64 #define DSP_HTOTAL(x) UPDATE(x, 27, 16) 65 #define DSP_HS_END(x) UPDATE(x, 7, 0) 66 #define DSP_HACT_END(x) UPDATE(x, 26, 16) 67 #define DSP_HACT_ST(x) UPDATE(x, 7, 0) 68 #define DSP_VTOTAL(x) UPDATE(x, 26, 16) 69 #define DSP_VS_END(x) UPDATE(x, 7, 0) 70 #define DSP_VACT_END(x) UPDATE(x, 26, 16) 71 #define DSP_VACT_ST(x) UPDATE(x, 7, 0) 72 #define DSP_HEIGHT(x) UPDATE(x, 26, 16) 73 #define DSP_WIDTH(x) UPDATE(x, 11, 0) 74 75 #define WIN2_FIFO_ALMOST_FULL_LEVEL(x) UPDATE(x, 27, 19) 76 #define WIN_EN(x) UPDATE(x, 18, 18) 77 #define BURST_REG(x) UPDATE(x, 12, 10) 78 #define WIN_FIFO_ALMOST_FULL_LEVEL(x) UPDATE(x, 9, 2) 79 #define WIN_FMT(x) UPDATE(x, 1, 0) 80 81 #define WIN_VIR_HEIGHT(x) UPDATE(x, 31, 16) 82 #define WIN_VIR_WIDTH(x) UPDATE(x, 15, 0) 83 #define WIN_ACT_HEIGHT(x) UPDATE(x, 26, 16) 84 #define WIN_ACT_WIDTH(x) UPDATE(x, 11, 0) 85 #define WIN_DSP_HEIGHT(x) UPDATE(x, 26, 16) 86 #define WIN_DSP_WIDTH(x) UPDATE(x, 11, 0) 87 #define WIN_DSP_YST(x) UPDATE(x, 26, 16) 88 #define WIN_DSP_XST(x) UPDATE(x, 11, 0) 89 90 #define DSP_OUT_LOW BIT(31) 91 #define DSP_EINK_MODE(x) UPDATE(x, 13, 13) 92 #define DSP_EINK_MODE_MASK BIT(13) 93 #define DSP_SDCE_WIDTH(x) UPDATE(x, 25, 16) 94 #define DSP_FRM_TOTAL(x) UPDATE(x, 9, 2) 95 #define DSP_FRM_TOTAL_MASK GENMASK(9, 2) 96 #define DSP_FRM_START BIT(0) 97 #define DSP_FRM_START_MASK BIT(0) 98 #define SW_BURST_CTRL BIT(12) 99 100 #define EINK_MODE_SWAP(x) UPDATE(x, 31, 31) 101 #define EINK_MODE_FRM_SEL(x) UPDATE(x, 30, 30) 102 #define DSP_GD_END(x) UPDATE(x, 26, 16) 103 #define DSP_GD_ST(x) UPDATE(x, 15, 8) 104 #define DSP_THREE_WIN_MODE(x) UPDATE(x, 7, 7) 105 #define THREE_WIN_MODE_MASK BIT(7) 106 #define DSP_SDDW_MODE(x) UPDATE(x, 6, 6) 107 #define EPD_AUO(x) UPDATE(x, 5, 5) 108 #define EPD_PWR(x) UPDATE(x, 4, 2) 109 #define EPD_GDRL(x) UPDATE(x, 1, 1) 110 #define EPD_SDSHR(x) UPDATE(x, 0, 0) 111 112 #define DSP_SWAP_MODE(x) UPDATE(x, 31, 30) 113 #define DSP_SWAP_MODE_MASK GENMASK(31, 30) 114 #define DSP_SDCLK_DIV(x) UPDATE(x, 19, 16) 115 #define DSP_SDCLK_DIV_MASK GENMASK(19, 16) 116 #define DSP_VCOM_MODE(x) UPDATE(x, 27, 27) 117 #define DSP_VCOM_MODE_MASK BIT(27) 118 119 #define DSP_UPDATE_MODE(x) UPDATE(x, 29, 29) 120 #define DSP_DISPLAY_MODE(x) UPDATE(x, 28, 28) 121 #define UPDATE_MODE_MASK BIT(29) 122 #define DISPLAY_MODE_MASK BIT(28) 123 124 #define DSP_FRM_INT_NUM(x) UPDATE(x, 19, 12) 125 #define FRM_END_INT BIT(0) 126 #define DSP_END_INT BIT(1) 127 #define DSP_FRM_INT BIT(2) 128 #define LINE_FLAG_INT BIT(3) 129 #define FRM_END_INT_MASK BIT(4) 130 #define DSP_END_INT_MASK BIT(5) 131 #define DSP_FRM_INT_MASK BIT(6) 132 #define LINE_FLAG_INT_MASK BIT(7) 133 #define FRM_END_INT_CLR BIT(8) 134 #define DSP_END_INT_CLR BIT(9) 135 #define DSP_FRM_INT_CLR BIT(10) 136 #define LINE_FLAG_INT_CLR BIT(11) 137 138 #define PMU_BASE_ADDR 0xfdd90000 139 #define PMU_PWR_GATE_SFTCON 0xA0 140 #define PMU_PWR_DWN_ST 0x98 141 #define RGA_PD_OFF BIT(5) 142 #define RGA_PD_STAT BIT(5) 143 enum ebc_win_data_fmt { 144 Y_DATA_4BPP = 0, 145 Y_DATA_8BPP = 1, 146 RGB888 = 2, 147 RGB565 = 3, 148 }; 149 150 #ifdef CONFIG_IRQ 151 #define IRQ_EBC 49 152 #endif 153 static volatile int last_frame_done = -1; 154 static inline void regs_dump(struct ebc_tcon_priv *tcon) 155 { 156 int i; 157 158 printf("dump registers:\n"); 159 for (i = 0; i <= EBC_WIN_MST2; i = i + 4) { 160 if (!(i % 16)) 161 printf("\n 0x%p:\t", tcon->reg + i); 162 printf("0x%x\t", readl(tcon->reg + i)); 163 } 164 printf("\nlut data:\n"); 165 for (i = 0x1000; i <= 0x1100; i = i + 4) { 166 if (!(i % 16)) 167 printf("\n 0x%p:\t", tcon->reg + i); 168 printf("0x%x\t", readl(tcon->reg + i)); 169 } 170 printf("\n"); 171 } 172 173 static int ebc_power_domain(int on) 174 { 175 u32 pd_reg; 176 u32 pd_stat; 177 int delay = 0; 178 179 if (on) { 180 pd_reg = RGA_PD_OFF << 16; 181 pd_stat = RGA_PD_STAT; 182 } else { 183 pd_reg = RGA_PD_OFF | (RGA_PD_OFF << 16); 184 pd_stat = ~((u32)RGA_PD_STAT); 185 } 186 187 /* enable rga pd for ebc tcon*/ 188 writel(pd_reg, PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON); 189 delay = 1000; 190 do { 191 udelay(1); 192 delay--; 193 if (delay == 0) { 194 printf("Enable rga pd for ebc failed !\n"); 195 return -1; 196 } 197 } while (readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST) & pd_stat); 198 199 return 0; 200 } 201 202 static inline void tcon_write(struct ebc_tcon_priv *tcon, unsigned int reg, 203 unsigned int value) 204 { 205 unsigned int *cache = tcon->regcache + (reg >> 2); 206 207 writel(value, tcon->reg + reg); 208 *cache = value; 209 } 210 211 static inline unsigned int tcon_read(struct ebc_tcon_priv *tcon, 212 unsigned int reg) 213 { 214 return readl(tcon->reg + reg); 215 } 216 217 static inline void tcon_update_bits(struct ebc_tcon_priv *tcon, 218 unsigned int reg, unsigned int mask, 219 unsigned int val) 220 { 221 unsigned int tmp; 222 unsigned int *cache = tcon->regcache + (reg >> 2); 223 224 tmp = *cache & ~mask; 225 tmp |= val & mask; 226 227 writel(tmp, tcon->reg + reg); 228 *cache = tmp; 229 } 230 231 #ifdef CONFIG_IRQ 232 static void ebc_irq_handler(int irq, void *data) 233 { 234 u32 intr_status; 235 struct udevice *dev = data; 236 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 237 238 intr_status = readl(tcon->reg + EBC_INT_STATUS); 239 240 if (intr_status & DSP_END_INT) { 241 tcon_update_bits(tcon, EBC_INT_STATUS, 242 DSP_END_INT_CLR, DSP_END_INT_CLR); 243 last_frame_done = 1; 244 } 245 } 246 #endif 247 248 static inline void tcon_cfg_done(struct ebc_tcon_priv *tcon) 249 { 250 writel(REG_LOAD_GLOBAL_EN, tcon->reg + EBC_CONFIG_DONE); 251 } 252 253 static int ebc_tcon_enable(struct udevice *dev, struct ebc_panel *panel) 254 { 255 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 256 257 /* panel timing and win info config */ 258 tcon_write(tcon, EBC_DSP_HTIMING0, 259 DSP_HTOTAL(panel->lsl + panel->lbl + panel->ldl + 260 panel->lel) | DSP_HS_END(panel->lsl + 2)); 261 tcon_write(tcon, EBC_DSP_HTIMING1, 262 DSP_HACT_END(panel->lsl + panel->lbl + panel->ldl) | 263 DSP_HACT_ST(panel->lsl + panel->lbl - 1)); 264 tcon_write(tcon, EBC_DSP_VTIMING0, 265 DSP_VTOTAL(panel->fsl + panel->fbl + panel->fdl + 266 panel->fel) | DSP_VS_END(panel->fsl)); 267 tcon_write(tcon, EBC_DSP_VTIMING1, 268 DSP_VACT_END(panel->fsl + panel->fbl + panel->fdl) | 269 DSP_VACT_ST(panel->fsl + panel->fbl)); 270 tcon_write(tcon, EBC_DSP_ACT_INFO, 271 DSP_HEIGHT(panel->height) | 272 DSP_WIDTH(panel->width)); 273 tcon_write(tcon, EBC_WIN_VIR, 274 WIN_VIR_HEIGHT(panel->vir_height) | 275 WIN_VIR_WIDTH(panel->vir_width)); 276 tcon_write(tcon, EBC_WIN_ACT, 277 WIN_ACT_HEIGHT(panel->height) | 278 WIN_ACT_WIDTH(panel->width)); 279 tcon_write(tcon, EBC_WIN_DSP, 280 WIN_DSP_HEIGHT(panel->height) | 281 WIN_DSP_WIDTH(panel->width)); 282 tcon_write(tcon, EBC_WIN_DSP_ST, 283 WIN_DSP_YST(panel->fsl + panel->fbl) | 284 WIN_DSP_XST(panel->lsl + panel->lbl)); 285 286 /* win2 fifo is 512x128, win fifo is 256x128, 287 * we set fifo almost value (fifo_size - 16) 288 * burst_reg = 7 mean ahb burst is incr16 289 */ 290 tcon_write(tcon, EBC_WIN_CTRL, 291 WIN2_FIFO_ALMOST_FULL_LEVEL(496) | WIN_EN(1) | 292 BURST_REG(7) | WIN_FIFO_ALMOST_FULL_LEVEL(240) | 293 WIN_FMT(Y_DATA_4BPP)); 294 295 /* 296 * EBC_EPD_CTRL info: 297 * DSP_GD_ST: GCLK rising edge point(SCLK), which count from 298 * the rasing edge of hsync(spec is wrong, count 299 * from rasing edge of hsync, not falling edge of hsync) 300 * DSP_GD_END : GCLK falling edge point(SCLK), which count from 301 * the rasing edge of hsync 302 * DSP_THREE_WIN_MODE: 0: lut mode or direct mode; 1: three win mode 303 * DSP_SDDW_MODE: 0: 8 bit data output; 1: 16 bit data output 304 * EPD_AUO: 0: EINK; 1:AUO 305 * EPD_GDRL: gate scanning direction: 1:button to top 0:top to button 306 * EPD_SDSHR: source scanning direction 1:right to left 0:left to right 307 */ 308 tcon_write(tcon, EBC_EPD_CTRL, 309 EINK_MODE_SWAP(1) | 310 DSP_GD_ST(panel->lsl + panel->gdck_sta) | 311 DSP_GD_END(panel->lsl + panel->gdck_sta + panel->lgonl) | 312 DSP_THREE_WIN_MODE(0) | 313 DSP_SDDW_MODE(!!panel->panel_16bit) | 314 EPD_AUO(0) | 315 EPD_GDRL(1) | 316 EPD_SDSHR(1)); 317 tcon_write(tcon, EBC_DSP_START, 318 DSP_SDCE_WIDTH(panel->ldl) | SW_BURST_CTRL); 319 320 tcon_write(tcon, EBC_DSP_CTRL, 321 DSP_SWAP_MODE(panel->panel_16bit ? 2 : 3) | 322 DSP_VCOM_MODE(1) | 323 DSP_SDCLK_DIV(panel->panel_16bit ? 7 : 3)); 324 325 tcon_cfg_done(tcon); 326 327 return 0; 328 } 329 330 static int ebc_tcon_disable(struct udevice *dev) 331 { 332 return 0; 333 } 334 335 static int ebc_tcon_dsp_mode_set(struct udevice *dev, int update_mode, 336 int display_mode, int three_win_mode, 337 int eink_mode) 338 { 339 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 340 341 tcon_update_bits(tcon, EBC_DSP_CTRL, 342 UPDATE_MODE_MASK | DISPLAY_MODE_MASK, 343 DSP_UPDATE_MODE(!!update_mode) | 344 DSP_DISPLAY_MODE(!!display_mode)); 345 346 tcon_update_bits(tcon, EBC_EPD_CTRL, THREE_WIN_MODE_MASK, 347 DSP_THREE_WIN_MODE(!!three_win_mode)); 348 /* always set frm start bit 0 before real frame start */ 349 tcon_update_bits(tcon, EBC_DSP_START, 350 DSP_EINK_MODE_MASK | DSP_FRM_START_MASK, 351 DSP_EINK_MODE(!!eink_mode)); 352 tcon_cfg_done(tcon); 353 354 return 0; 355 } 356 357 static int ebc_tcon_image_addr_set(struct udevice *dev, u32 pre_image_addr, 358 u32 cur_image_addr) 359 { 360 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 361 362 tcon_write(tcon, EBC_WIN_MST0, pre_image_addr); 363 tcon_write(tcon, EBC_WIN_MST1, cur_image_addr); 364 tcon_cfg_done(tcon); 365 366 return 0; 367 } 368 369 static int ebc_tcon_frame_addr_set(struct udevice *dev, u32 frame_addr) 370 { 371 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 372 373 tcon_write(tcon, EBC_WIN_MST2, frame_addr); 374 tcon_cfg_done(tcon); 375 376 return 0; 377 } 378 379 static int ebc_tcon_lut_data_set(struct udevice *dev, unsigned int *lut_data, 380 int frame_count, int lut_32) 381 { 382 int i, lut_size; 383 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 384 385 if ((!lut_32 && frame_count > 256) || (lut_32 && frame_count > 64)) { 386 dev_err(tcon->dev, "frame count over flow\n"); 387 return -1; 388 } 389 390 if (lut_32) 391 lut_size = frame_count * 64; 392 else 393 lut_size = frame_count * 16; 394 395 for (i = 0; i < lut_size; i++) 396 tcon_write(tcon, EBC_LUT_DATA_ADDR + (i * 4), lut_data[i]); 397 398 tcon_cfg_done(tcon); 399 400 return 0; 401 } 402 403 static int wait_for_last_frame_complete(struct udevice *dev) 404 { 405 #ifndef CONFIG_IRQ 406 u32 intr_status; 407 #endif 408 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 409 410 #ifdef CONFIG_IRQ 411 while (1) { 412 if ((last_frame_done == -1) || (last_frame_done == 1)) 413 break; 414 msleep(1); 415 } 416 #else 417 /* wait for frame display end*/ 418 while (1) { 419 /* first frame don't need to wait*/ 420 if (last_frame_done == -1) 421 break; 422 intr_status = readl(tcon->reg + EBC_INT_STATUS); 423 if (intr_status & DSP_END_INT) 424 break; 425 msleep(1); 426 } 427 #endif 428 tcon_update_bits(tcon, EBC_INT_STATUS, 429 DSP_END_INT_CLR, DSP_END_INT_CLR); 430 431 return 0; 432 } 433 434 static int ebc_tcon_frame_start(struct udevice *dev, int frame_total) 435 { 436 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 437 438 tcon_write(tcon, EBC_INT_STATUS, 439 LINE_FLAG_INT_MASK | DSP_FRM_INT_MASK | FRM_END_INT_MASK); 440 tcon_update_bits(tcon, EBC_DSP_START, 441 DSP_FRM_TOTAL_MASK, DSP_FRM_TOTAL(frame_total - 1)); 442 tcon_cfg_done(tcon); 443 444 tcon_update_bits(tcon, EBC_DSP_START, 445 DSP_FRM_START_MASK, DSP_FRM_START); 446 last_frame_done = 0; 447 return 0; 448 } 449 450 static int rk_ebc_tcon_probe(struct udevice *dev) 451 { 452 int ret; 453 struct ebc_tcon_priv *priv = dev_get_priv(dev); 454 455 /*Enable PD first*/ 456 ret = ebc_power_domain(1); 457 if (ret) { 458 printf("%s, enable pd failed\n", __func__); 459 return -1; 460 } 461 462 priv->dev = dev; 463 ret = clk_set_defaults(dev); 464 if (ret) 465 printf("%s clk_set_defaults failed %d\n", __func__, ret); 466 467 #ifdef CONFIG_IRQ 468 irq_install_handler(IRQ_EBC, ebc_irq_handler, dev); 469 irq_handler_enable(IRQ_EBC); 470 #endif 471 return 0; 472 } 473 474 const struct rk_ebc_tcon_ops ebc_tcon_funcs = { 475 .enable = ebc_tcon_enable, 476 .disable = ebc_tcon_disable, 477 .dsp_mode_set = ebc_tcon_dsp_mode_set, 478 .image_addr_set = ebc_tcon_image_addr_set, 479 .frame_addr_set = ebc_tcon_frame_addr_set, 480 .lut_data_set = ebc_tcon_lut_data_set, 481 .frame_start = ebc_tcon_frame_start, 482 .wait_for_last_frame_complete = wait_for_last_frame_complete, 483 }; 484 485 static int rk_ebc_tcon_ofdata_to_platdata(struct udevice *dev) 486 { 487 fdt_size_t size; 488 fdt_addr_t addr; 489 struct ebc_tcon_priv *priv = dev_get_priv(dev); 490 491 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 492 if (priv->grf <= 0) { 493 debug("%s: Get syscon grf failed (ret=%p)\n", 494 __func__, priv->grf); 495 return -ENXIO; 496 } 497 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); 498 if (priv->pmugrf <= 0) { 499 debug("%s: Get syscon pmugrf failed (ret=%p)\n", 500 __func__, priv->grf); 501 return -ENXIO; 502 } 503 addr = dev_read_addr_size(dev, "reg", &size); 504 if (addr == FDT_ADDR_T_NONE) { 505 debug("%s: Get ebc_tcon address failed\n", __func__); 506 return -ENXIO; 507 } 508 509 priv->reg = ioremap(addr, size); 510 priv->reg_len = size; 511 priv->regcache = malloc(size); 512 memset(priv->regcache, 0, size); 513 return 0; 514 } 515 516 static const struct udevice_id ebc_tcon_ids[] = { 517 { .compatible = "rockchip,rk3568-ebc-tcon" }, 518 { } 519 }; 520 521 U_BOOT_DRIVER(rk_ebc_tcon) = { 522 .name = "rk_ebc_tcon", 523 .id = UCLASS_EBC, 524 .of_match = ebc_tcon_ids, 525 .ofdata_to_platdata = rk_ebc_tcon_ofdata_to_platdata, 526 .probe = rk_ebc_tcon_probe, 527 .ops = &ebc_tcon_funcs, 528 .priv_auto_alloc_size = sizeof(struct ebc_tcon_priv), 529 }; 530 531 UCLASS_DRIVER(ebc_tcon) = { 532 .id = UCLASS_EBC, 533 .name = "ebc_tcon", 534 }; 535 536