1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Wenping Zhang <wenping.zhang@rock-chips.com> 6 */ 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <dm/pinctrl.h> 11 #include <pwm.h> 12 #include <regmap.h> 13 #include <syscon.h> 14 #include <asm/arch/clock.h> 15 #include <asm/io.h> 16 #include <syscon.h> 17 #include <linux/io.h> 18 #include "rk_ebc.h" 19 #ifdef CONFIG_IRQ 20 #include <irq-generic.h> 21 #endif 22 23 struct ebc_tcon_priv { 24 struct udevice *dev; 25 void __iomem *reg; 26 u32 *regcache; 27 u32 reg_len; 28 void *grf; 29 void *pmugrf; 30 struct clk dclk; 31 }; 32 33 #define msleep(a) udelay((a) * 1000) 34 #define HIWORD_UPDATE(x, l, h) (((x) << (l)) | (GENMASK(h, l) << 16)) 35 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) 36 37 #define REG_LOAD_GLOBAL_EN 0x1 38 39 /* ebc register define */ 40 #define EBC_DSP_START 0x0000 //Frame statrt register 41 #define EBC_EPD_CTRL 0x0004 //EPD control register 42 #define EBC_DSP_CTRL 0x0008 //Display control register 43 #define EBC_DSP_HTIMING0 0x000c //H-Timing setting register0 44 #define EBC_DSP_HTIMING1 0x0010 //H-Timing setting register1 45 #define EBC_DSP_VTIMING0 0x0014 //V-Timing setting register0 46 #define EBC_DSP_VTIMING1 0x0018 //V-Timing setting register1 47 #define EBC_DSP_ACT_INFO 0x001c //ACTIVE width/height 48 #define EBC_WIN_CTRL 0x0020 //Window ctrl 49 #define EBC_WIN_MST0 0x0024 //Current win memory start 50 #define EBC_WIN_MST1 0x0028 //Next win memory start 51 #define EBC_WIN_VIR 0x002c //Window vir width/height 52 #define EBC_WIN_ACT 0x0030 //Window act width/height 53 #define EBC_WIN_DSP 0x0034 //Window dsp width/height 54 #define EBC_WIN_DSP_ST 0x0038 //Window display start point 55 #define EBC_INT_STATUS 0x003c //Interrupt register 56 #define EBC_VCOM0 0x0040 //VCOM setting register0 57 #define EBC_VCOM1 0x0044 //VCOM setting register1 58 #define EBC_VCOM2 0x0048 //VCOM setting register2 59 #define EBC_VCOM3 0x004c //VCOM setting register3 60 #define EBC_CONFIG_DONE 0x0050 //Config done register 61 #define EBC_VNUM 0x0054 //Line flag num 62 #define EBC_WIN_MST2 0x0058 //Framecount memory start 63 #define EBC_LUT_DATA_ADDR 0x1000 //lut data address 64 65 #define DSP_HTOTAL(x) UPDATE(x, 27, 16) 66 #define DSP_HS_END(x) UPDATE(x, 7, 0) 67 #define DSP_HACT_END(x) UPDATE(x, 26, 16) 68 #define DSP_HACT_ST(x) UPDATE(x, 7, 0) 69 #define DSP_VTOTAL(x) UPDATE(x, 26, 16) 70 #define DSP_VS_END(x) UPDATE(x, 7, 0) 71 #define DSP_VACT_END(x) UPDATE(x, 26, 16) 72 #define DSP_VACT_ST(x) UPDATE(x, 7, 0) 73 #define DSP_HEIGHT(x) UPDATE(x, 26, 16) 74 #define DSP_WIDTH(x) UPDATE(x, 11, 0) 75 76 #define WIN2_FIFO_ALMOST_FULL_LEVEL(x) UPDATE(x, 27, 19) 77 #define WIN_EN(x) UPDATE(x, 18, 18) 78 #define BURST_REG(x) UPDATE(x, 12, 10) 79 #define WIN_FIFO_ALMOST_FULL_LEVEL(x) UPDATE(x, 9, 2) 80 #define WIN_FMT(x) UPDATE(x, 1, 0) 81 82 #define WIN_VIR_HEIGHT(x) UPDATE(x, 31, 16) 83 #define WIN_VIR_WIDTH(x) UPDATE(x, 15, 0) 84 #define WIN_ACT_HEIGHT(x) UPDATE(x, 26, 16) 85 #define WIN_ACT_WIDTH(x) UPDATE(x, 11, 0) 86 #define WIN_DSP_HEIGHT(x) UPDATE(x, 26, 16) 87 #define WIN_DSP_WIDTH(x) UPDATE(x, 11, 0) 88 #define WIN_DSP_YST(x) UPDATE(x, 26, 16) 89 #define WIN_DSP_XST(x) UPDATE(x, 11, 0) 90 91 #define DSP_OUT_LOW BIT(31) 92 #define DSP_EINK_MODE(x) UPDATE(x, 13, 13) 93 #define DSP_EINK_MODE_MASK BIT(13) 94 #define DSP_SDCE_WIDTH(x) UPDATE(x, 25, 16) 95 #define DSP_FRM_TOTAL(x) UPDATE(x, 9, 2) 96 #define DSP_FRM_TOTAL_MASK GENMASK(9, 2) 97 #define DSP_FRM_START BIT(0) 98 #define DSP_FRM_START_MASK BIT(0) 99 #define SW_BURST_CTRL BIT(12) 100 101 #define EINK_MODE_SWAP(x) UPDATE(x, 31, 31) 102 #define EINK_MODE_FRM_SEL(x) UPDATE(x, 30, 30) 103 #define DSP_GD_END(x) UPDATE(x, 26, 16) 104 #define DSP_GD_ST(x) UPDATE(x, 15, 8) 105 #define DSP_THREE_WIN_MODE(x) UPDATE(x, 7, 7) 106 #define THREE_WIN_MODE_MASK BIT(7) 107 #define DSP_SDDW_MODE(x) UPDATE(x, 6, 6) 108 #define EPD_AUO(x) UPDATE(x, 5, 5) 109 #define EPD_PWR(x) UPDATE(x, 4, 2) 110 #define EPD_GDRL(x) UPDATE(x, 1, 1) 111 #define EPD_SDSHR(x) UPDATE(x, 0, 0) 112 113 #define DSP_SWAP_MODE(x) UPDATE(x, 31, 30) 114 #define DSP_SWAP_MODE_MASK GENMASK(31, 30) 115 #define DSP_SDCLK_DIV(x) UPDATE(x, 19, 16) 116 #define DSP_SDCLK_DIV_MASK GENMASK(19, 16) 117 #define DSP_VCOM_MODE(x) UPDATE(x, 27, 27) 118 #define DSP_VCOM_MODE_MASK BIT(27) 119 120 #define DSP_UPDATE_MODE(x) UPDATE(x, 29, 29) 121 #define DSP_DISPLAY_MODE(x) UPDATE(x, 28, 28) 122 #define UPDATE_MODE_MASK BIT(29) 123 #define DISPLAY_MODE_MASK BIT(28) 124 125 #define DSP_FRM_INT_NUM(x) UPDATE(x, 19, 12) 126 #define FRM_END_INT BIT(0) 127 #define DSP_END_INT BIT(1) 128 #define DSP_FRM_INT BIT(2) 129 #define LINE_FLAG_INT BIT(3) 130 #define FRM_END_INT_MASK BIT(4) 131 #define DSP_END_INT_MASK BIT(5) 132 #define DSP_FRM_INT_MASK BIT(6) 133 #define LINE_FLAG_INT_MASK BIT(7) 134 #define FRM_END_INT_CLR BIT(8) 135 #define DSP_END_INT_CLR BIT(9) 136 #define DSP_FRM_INT_CLR BIT(10) 137 #define LINE_FLAG_INT_CLR BIT(11) 138 139 #define RK3576_EBC_DSP_START 0x0000 140 #define RK3576_EBC_EPD_CTRL 0x0004 141 #define RK3576_EBC_DSP_CTRL 0x0008 142 #define RK3576_EBC_DSP_HTIMING0 0x000C 143 #define RK3576_EBC_DSP_HTIMING1 0x0010 144 #define RK3576_EBC_DSP_VTIMING0 0x0014 145 #define RK3576_EBC_DSP_VTIMING1 0x0018 146 #define RK3576_EBC_DSP_ACT_INFO 0x001C 147 #define RK3576_EBC_WIN_CTRL 0x0020 148 #define RK3576_EBC_WIN_MST0 0x0024 149 #define RK3576_EBC_WIN_MST1 0x0028 150 #define RK3576_EBC_WIN_VIR 0x002C 151 #define RK3576_EBC_WIN_ACT 0x0030 152 #define RK3576_EBC_WIN_DSP 0x0034 153 #define RK3576_EBC_WIN_DSP_ST 0x0038 154 #define RK3576_EBC_INT_STATUS 0x003C 155 #define RK3576_EBC_VCOM0 0x0040 156 #define RK3576_EBC_VCOM1 0x0044 157 #define RK3576_EBC_VCOM2 0x0048 158 #define RK3576_EBC_VCOM3 0x004C 159 #define RK3576_EBC_CONFIG_DONE 0x0050 160 #define RK3576_EBC_VNUM 0x0054 161 #define RK3576_EBC_WIN_MST2 0x0058 162 #define RK3576_EBC_DSP_CTRL2 0x005C 163 #define RK3576_EBC_DSP_CTRL3 0x0060 164 #define RK3576_EBC_WIN0_CTRL 0x0064 165 #define RK3576_EBC_WIN1_CTRL 0x0068 166 #define RK3576_EBC_WIN2_CTRL 0x006C 167 #define RK3576_EBC_SYS_CTRL 0x0070 168 #define RK3576_EBC_LUT_ADDRESS_MAP_0 0x1000 169 170 #define RK3576_DSP_FRM_START BIT(0) 171 #define RK3576_DSP_FRM_START_MASK BIT(0) 172 173 #define RK3576_EINK_MODE_SWAP(x) UPDATE(x, 31, 31) 174 #define RK3576_EINK_MODE_FRM_SEL(x) UPDATE(x, 30, 30) 175 #define RK3576_DSP_THREE_WIN_MODE(x) UPDATE(x, 29, 29) 176 #define RK3576_THREE_WIN_MODE_MASK BIT(29) 177 #define RK3576_DSP_GD_END(x) UPDATE(x, 26, 16) 178 #define RK3576_DSP_GD_ST(x) UPDATE(x, 15, 8) 179 #define RK3576_DSP_SDDW_MODE(x) UPDATE(x, 7, 6) 180 #define RK3576_EPD_AUO(x) UPDATE(x, 5, 5) 181 #define RK3576_EPD_PWR(x) UPDATE(x, 4, 2) 182 #define RK3576_EPD_GDRL(x) UPDATE(x, 1, 1) 183 #define RK3576_EPD_SDSHR(x) UPDATE(x, 0, 0) 184 185 #define RK3576_DSP_SWAP_MODE(x) UPDATE(x, 31, 30) 186 #define RK3576_DSP_UPDATE_MODE(x) UPDATE(x, 29, 29) 187 #define RK3576_DSP_DISPLAY_MODE(x) UPDATE(x, 28, 28) 188 #define RK3576_UPDATE_MODE_MASK BIT(29) 189 #define RK3576_DISPLAY_MODE_MASK BIT(28) 190 #define RK3576_DSP_VCOM_MODE(x) UPDATE(x, 27, 27) 191 #define RK3576_DSP_SDCLK_DIV(x) UPDATE(x, 19, 16) 192 #define RK3576_DSP_SDCLK_DIV_MASK GENMASK(19, 16) 193 194 #define RK3576_DSP_HTOTAL(x) UPDATE(x, 31, 16) 195 #define RK3576_DSP_HS_END(x) UPDATE(x, 15, 0) 196 #define RK3576_DSP_HACT_END(x) UPDATE(x, 31, 16) 197 #define RK3576_DSP_HACT_ST(x) UPDATE(x, 15, 0) 198 #define RK3576_DSP_VTOTAL(x) UPDATE(x, 31, 16) 199 #define RK3576_DSP_VS_END(x) UPDATE(x, 15, 0) 200 #define RK3576_DSP_VACT_END(x) UPDATE(x, 31, 16) 201 #define RK3576_DSP_VACT_ST(x) UPDATE(x, 15, 0) 202 #define RK3576_DSP_HEIGHT(x) UPDATE(x, 31, 16) 203 #define RK3576_DSP_WIDTH(x) UPDATE(x, 15, 0) 204 205 #define RK3576_WIN_VIR_HEIGHT(x) UPDATE(x, 31, 16) 206 #define RK3576_WIN_VIR_WIDTH(x) UPDATE(x, 15, 0) 207 #define RK3576_WIN_ACT_HEIGHT(x) UPDATE(x, 31, 16) 208 #define RK3576_WIN_ACT_WIDTH(x) UPDATE(x, 15, 0) 209 #define RK3576_WIN_DSP_HEIGHT(x) UPDATE(x, 31, 16) 210 #define RK3576_WIN_DSP_WIDTH(x) UPDATE(x, 15, 0) 211 #define RK3576_WIN_DSP_YST(x) UPDATE(x, 31, 16) 212 #define RK3576_WIN_DSP_XST(x) UPDATE(x, 15, 0) 213 214 #define RK3576_DMA_BURST_LENGTH(x) UPDATE(x, 25, 24) 215 #define RK3576_WIN2_FIFO_ALMOST_FULL_LEVEL(x) UPDATE(x, 20, 12) 216 #define RK3576_WIN_FIFO_ALMOST_FULL_LEVEL(x) UPDATE(x, 11, 4) 217 #define RK3576_WIN_FMT(x) UPDATE(x, 2, 0) 218 #define RK3576_WIN_FMT_MASK GENMASK(2, 0) 219 220 #define RK3576_WIN_RID(x) UPDATE(x, 7, 4) 221 #define RK3576_WIN_AXI_GATHER_NUM(x) UPDATE(x, 11, 8) 222 #define RK3576_WIN_AXI_GATHER_EN BIT(1) 223 #define RK3576_WIN_EN BIT(0) 224 225 #define RK3576_WIN2_EMPTY_INT_MASK BIT(26) 226 #define RK3576_WIN1_EMPTY_INT_MASK BIT(25) 227 #define RK3576_WIN0_EMPTY_INT_MASK BIT(24) 228 #define RK3576_FRM_END_INT_MASK BIT(4) 229 #define RK3576_DSP_FRM_INT_MASK BIT(6) 230 #define RK3576_LINE_FLAG_INT_MASK BIT(7) 231 232 #define RK3576_DSP_SDCE_WIDTH(x) UPDATE(x, 23, 12) 233 #define RK3576_DSP_SDCE_WIDTH_MASK(x) GENMASK(x, 23, 12) 234 #define RK3576_DSP_FRM_TOTAL(x) UPDATE(x, 11, 4) 235 #define RK3576_DSP_FRM_TOTAL_MASK GENMASK(11, 4) 236 #define RK3576_DSP_EINK_MODE(x) UPDATE(x, 2, 2) 237 #define RK3576_DSP_EINK_MODE_MASK BIT(2) 238 #define RK3576_SW_BURST_CTRL BIT(1) 239 #define RK3576_DSP_OUT_LOW BIT(0) 240 241 #define RK3576_SW_AXI_RD_URGENCY_EN BIT(24) 242 #define RK3576_SW_AXI_MAX_OUTSTAND_NUM(x) UPDATE(x, 20, 16) 243 #define RK3576_SW_AXI_MAX_OUTSTAND_EN BIT(12) 244 #define RK3576_SW_NOC_HURRY_THRESHOLD(x) UPDATE(x, 11, 8) 245 #define RK3576_SW_NOC_HURRY_VALUE(x) UPDATE(x, 6, 5) 246 #define RK3576_SW_NOC_HURRY_EN BIT(4) 247 #define RK3576_SW_NOC_QOS_VALUE(x) UPDATE(x, 2, 1) 248 #define RK3576_SW_NOC_QOS_EN BIT(0) 249 250 #define PMU_BASE_ADDR 0xfdd90000 251 #define PMU_PWR_GATE_SFTCON 0xA0 252 #define PMU_PWR_DWN_ST 0x98 253 #define RGA_PD_OFF BIT(5) 254 #define RGA_PD_STAT BIT(5) 255 enum ebc_win_data_fmt { 256 Y_DATA_4BPP = 0, 257 Y_DATA_8BPP = 1, 258 RGB888 = 2, 259 RGB565 = 3, 260 }; 261 262 static volatile int last_frame_done = -1; 263 static inline void regs_dump(struct ebc_tcon_priv *tcon) 264 { 265 int i; 266 267 printf("dump registers:\n"); 268 for (i = 0; i <= EBC_WIN_MST2; i = i + 4) { 269 if (!(i % 16)) 270 printf("\n 0x%p:\t", tcon->reg + i); 271 printf("0x%x\t", readl(tcon->reg + i)); 272 } 273 printf("\nlut data:\n"); 274 for (i = 0x1000; i <= 0x1100; i = i + 4) { 275 if (!(i % 16)) 276 printf("\n 0x%p:\t", tcon->reg + i); 277 printf("0x%x\t", readl(tcon->reg + i)); 278 } 279 printf("\n"); 280 } 281 282 /* RK356X ebc power domain is enabled by default when power up */ 283 static int __maybe_unused ebc_power_domain(int on) 284 { 285 u32 pd_reg; 286 u32 pd_stat; 287 int delay = 0; 288 289 if (on) { 290 pd_reg = RGA_PD_OFF << 16; 291 pd_stat = RGA_PD_STAT; 292 } else { 293 pd_reg = RGA_PD_OFF | (RGA_PD_OFF << 16); 294 pd_stat = ~((u32)RGA_PD_STAT); 295 } 296 297 /* enable rga pd for ebc tcon*/ 298 writel(pd_reg, PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON); 299 delay = 1000; 300 do { 301 udelay(1); 302 delay--; 303 if (delay == 0) { 304 printf("Enable rga pd for ebc failed !\n"); 305 return -1; 306 } 307 } while (readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST) & pd_stat); 308 309 return 0; 310 } 311 312 static inline void tcon_write(struct ebc_tcon_priv *tcon, unsigned int reg, 313 unsigned int value) 314 { 315 unsigned int *cache = tcon->regcache + (reg >> 2); 316 317 writel(value, tcon->reg + reg); 318 *cache = value; 319 } 320 321 static inline unsigned int tcon_read(struct ebc_tcon_priv *tcon, 322 unsigned int reg) 323 { 324 return readl(tcon->reg + reg); 325 } 326 327 static inline void tcon_update_bits(struct ebc_tcon_priv *tcon, 328 unsigned int reg, unsigned int mask, 329 unsigned int val) 330 { 331 unsigned int tmp; 332 unsigned int *cache = tcon->regcache + (reg >> 2); 333 334 tmp = *cache & ~mask; 335 tmp |= val & mask; 336 337 writel(tmp, tcon->reg + reg); 338 *cache = tmp; 339 } 340 341 #ifdef CONFIG_IRQ 342 static void ebc_irq_handler(int irq, void *data) 343 { 344 u32 intr_status; 345 struct udevice *dev = data; 346 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 347 348 intr_status = readl(tcon->reg + EBC_INT_STATUS); 349 350 if (intr_status & DSP_END_INT) { 351 tcon_update_bits(tcon, EBC_INT_STATUS, 352 DSP_END_INT_CLR, DSP_END_INT_CLR); 353 last_frame_done = 1; 354 } 355 } 356 #endif 357 358 static inline void tcon_cfg_done(struct ebc_tcon_priv *tcon) 359 { 360 writel(REG_LOAD_GLOBAL_EN, tcon->reg + EBC_CONFIG_DONE); 361 } 362 363 #ifdef CONFIG_ROCKCHIP_RK3568 364 static int ebc_tcon_enable(struct udevice *dev, struct ebc_panel *panel) 365 { 366 int ret; 367 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 368 u32 width, height, vir_width, vir_height; 369 370 if (panel->rearrange) { 371 width = panel->width * 2; 372 height = panel->height / 2; 373 vir_width = panel->vir_width * 2; 374 vir_height = panel->vir_height / 2; 375 } else { 376 width = panel->width; 377 height = panel->height; 378 vir_width = panel->vir_width; 379 vir_height = panel->vir_height; 380 } 381 382 /* panel timing and win info config */ 383 tcon_write(tcon, EBC_DSP_HTIMING0, 384 DSP_HTOTAL(panel->lsl + panel->lbl + panel->ldl + 385 panel->lel) | DSP_HS_END(panel->lsl)); 386 tcon_write(tcon, EBC_DSP_HTIMING1, 387 DSP_HACT_END(panel->lsl + panel->lbl + panel->ldl) | 388 DSP_HACT_ST(panel->lsl + panel->lbl - 1)); 389 tcon_write(tcon, EBC_DSP_VTIMING0, 390 DSP_VTOTAL(panel->fsl + panel->fbl + panel->fdl + 391 panel->fel) | DSP_VS_END(panel->fsl)); 392 tcon_write(tcon, EBC_DSP_VTIMING1, 393 DSP_VACT_END(panel->fsl + panel->fbl + panel->fdl) | 394 DSP_VACT_ST(panel->fsl + panel->fbl)); 395 tcon_write(tcon, EBC_DSP_ACT_INFO, 396 DSP_HEIGHT(height) | 397 DSP_WIDTH(width)); 398 tcon_write(tcon, EBC_WIN_VIR, 399 WIN_VIR_HEIGHT(vir_height) | 400 WIN_VIR_WIDTH(vir_width)); 401 tcon_write(tcon, EBC_WIN_ACT, 402 WIN_ACT_HEIGHT(height) | 403 WIN_ACT_WIDTH(width)); 404 tcon_write(tcon, EBC_WIN_DSP, 405 WIN_DSP_HEIGHT(height) | 406 WIN_DSP_WIDTH(width)); 407 tcon_write(tcon, EBC_WIN_DSP_ST, 408 WIN_DSP_YST(panel->fsl + panel->fbl) | 409 WIN_DSP_XST(panel->lsl + panel->lbl)); 410 411 /* win2 fifo is 512x128, win fifo is 256x128, 412 * we set fifo almost value (fifo_size - 16) 413 * burst_reg = 7 mean ahb burst is incr16 414 */ 415 tcon_write(tcon, EBC_WIN_CTRL, 416 WIN2_FIFO_ALMOST_FULL_LEVEL(496) | WIN_EN(1) | 417 BURST_REG(7) | WIN_FIFO_ALMOST_FULL_LEVEL(240) | 418 WIN_FMT(Y_DATA_4BPP)); 419 420 /* 421 * EBC_EPD_CTRL info: 422 * DSP_GD_ST: GCLK rising edge point(SCLK), which count from 423 * the rasing edge of hsync(spec is wrong, count 424 * from rasing edge of hsync, not falling edge of hsync) 425 * DSP_GD_END : GCLK falling edge point(SCLK), which count from 426 * the rasing edge of hsync 427 * DSP_THREE_WIN_MODE: 0: lut mode or direct mode; 1: three win mode 428 * DSP_SDDW_MODE: 0: 8 bit data output; 1: 16 bit data output 429 * EPD_AUO: 0: EINK; 1:AUO 430 * EPD_GDRL: gate scanning direction: 1:button to top 0:top to button 431 * EPD_SDSHR: source scanning direction 1:right to left 0:left to right 432 */ 433 tcon_write(tcon, EBC_EPD_CTRL, 434 EINK_MODE_SWAP(1) | 435 DSP_GD_ST(panel->lsl + panel->gdck_sta) | 436 DSP_GD_END(panel->lsl + panel->gdck_sta + panel->lgonl) | 437 DSP_THREE_WIN_MODE(0) | 438 DSP_SDDW_MODE(!!panel->panel_16bit) | 439 EPD_AUO(0) | 440 EPD_GDRL(1) | 441 EPD_SDSHR(1)); 442 tcon_write(tcon, EBC_DSP_START, 443 DSP_SDCE_WIDTH(panel->ldl) | SW_BURST_CTRL); 444 445 tcon_write(tcon, EBC_DSP_CTRL, 446 DSP_SWAP_MODE(panel->panel_16bit ? 2 : 3) | 447 DSP_VCOM_MODE(1) | 448 DSP_SDCLK_DIV(panel->panel_16bit ? 7 : 3)); 449 450 tcon_cfg_done(tcon); 451 452 ret = clk_set_rate(&tcon->dclk, panel->sdck * ((panel->panel_16bit ? 7 : 3) + 1)); 453 if (ret < 0) { 454 printf("%s: set clock rate failed, %d\n", __func__, ret); 455 return ret; 456 } 457 458 return 0; 459 } 460 #endif 461 462 static int ebc_tcon_disable(struct udevice *dev) 463 { 464 return 0; 465 } 466 467 #ifdef CONFIG_ROCKCHIP_RK3568 468 static int ebc_tcon_dsp_mode_set(struct udevice *dev, int update_mode, 469 int display_mode, int three_win_mode, 470 int eink_mode) 471 { 472 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 473 474 tcon_update_bits(tcon, EBC_DSP_CTRL, 475 UPDATE_MODE_MASK | DISPLAY_MODE_MASK, 476 DSP_UPDATE_MODE(!!update_mode) | 477 DSP_DISPLAY_MODE(!!display_mode)); 478 479 tcon_update_bits(tcon, EBC_EPD_CTRL, THREE_WIN_MODE_MASK, 480 DSP_THREE_WIN_MODE(!!three_win_mode)); 481 /* always set frm start bit 0 before real frame start */ 482 tcon_update_bits(tcon, EBC_DSP_START, 483 DSP_EINK_MODE_MASK | DSP_FRM_START_MASK, 484 DSP_EINK_MODE(!!eink_mode)); 485 tcon_cfg_done(tcon); 486 487 return 0; 488 } 489 #endif 490 491 static int ebc_tcon_image_addr_set(struct udevice *dev, u32 pre_image_addr, 492 u32 cur_image_addr) 493 { 494 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 495 496 tcon_write(tcon, EBC_WIN_MST0, pre_image_addr); 497 tcon_write(tcon, EBC_WIN_MST1, cur_image_addr); 498 tcon_cfg_done(tcon); 499 500 return 0; 501 } 502 503 static int ebc_tcon_frame_addr_set(struct udevice *dev, u32 frame_addr) 504 { 505 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 506 507 tcon_write(tcon, EBC_WIN_MST2, frame_addr); 508 tcon_cfg_done(tcon); 509 510 return 0; 511 } 512 513 static int ebc_tcon_lut_data_set(struct udevice *dev, unsigned int *lut_data, 514 int frame_count, int lut_32) 515 { 516 int i, lut_size; 517 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 518 519 if ((!lut_32 && frame_count > 256) || (lut_32 && frame_count > 64)) { 520 dev_err(tcon->dev, "frame count over flow\n"); 521 return -1; 522 } 523 524 if (lut_32) 525 lut_size = frame_count * 64; 526 else 527 lut_size = frame_count * 16; 528 529 for (i = 0; i < lut_size; i++) 530 tcon_write(tcon, EBC_LUT_DATA_ADDR + (i * 4), lut_data[i]); 531 532 tcon_cfg_done(tcon); 533 534 return 0; 535 } 536 537 static int wait_for_last_frame_complete(struct udevice *dev) 538 { 539 #ifndef CONFIG_IRQ 540 u32 intr_status; 541 #endif 542 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 543 544 #ifdef CONFIG_IRQ 545 while (1) { 546 if ((last_frame_done == -1) || (last_frame_done == 1)) 547 break; 548 msleep(1); 549 } 550 #else 551 /* wait for frame display end*/ 552 while (1) { 553 /* first frame don't need to wait*/ 554 if (last_frame_done == -1) 555 break; 556 intr_status = readl(tcon->reg + EBC_INT_STATUS); 557 if (intr_status & DSP_END_INT) 558 break; 559 msleep(1); 560 } 561 #endif 562 tcon_update_bits(tcon, EBC_INT_STATUS, 563 DSP_END_INT_CLR, DSP_END_INT_CLR); 564 565 return 0; 566 } 567 568 #ifdef CONFIG_ROCKCHIP_RK3568 569 static int ebc_tcon_frame_start(struct udevice *dev, int frame_total) 570 { 571 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 572 573 tcon_write(tcon, EBC_INT_STATUS, 574 LINE_FLAG_INT_MASK | DSP_FRM_INT_MASK | FRM_END_INT_MASK); 575 tcon_update_bits(tcon, EBC_DSP_START, 576 DSP_FRM_TOTAL_MASK, DSP_FRM_TOTAL(frame_total - 1)); 577 tcon_cfg_done(tcon); 578 579 tcon_update_bits(tcon, EBC_DSP_START, 580 DSP_FRM_START_MASK, DSP_FRM_START); 581 last_frame_done = 0; 582 return 0; 583 } 584 #endif 585 586 #ifdef CONFIG_ROCKCHIP_RK3576 587 static int rk3576_ebc_tcon_enable(struct udevice *dev, struct ebc_panel *panel) 588 { 589 int ret; 590 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 591 u32 width, height, vir_width, vir_height; 592 593 if (panel->rearrange) { 594 width = panel->width * 2; 595 height = panel->height / 2; 596 vir_width = panel->vir_width * 2; 597 vir_height = panel->vir_height / 2; 598 } else { 599 width = panel->width; 600 height = panel->height; 601 vir_width = panel->vir_width; 602 vir_height = panel->vir_height; 603 } 604 605 /* panel timing and win info config */ 606 tcon_write(tcon, RK3576_EBC_DSP_HTIMING0, 607 RK3576_DSP_HTOTAL(panel->lsl + panel->lbl + panel->ldl + panel->lel) | 608 RK3576_DSP_HS_END(panel->lsl)); 609 tcon_write(tcon, RK3576_EBC_DSP_HTIMING1, 610 RK3576_DSP_HACT_END(panel->lsl + panel->lbl + panel->ldl) | 611 RK3576_DSP_HACT_ST(panel->lsl + panel->lbl - 1)); 612 tcon_write(tcon, RK3576_EBC_DSP_VTIMING0, 613 RK3576_DSP_VTOTAL(panel->fsl + panel->fbl + panel->fdl + panel->fel) | 614 RK3576_DSP_VS_END(panel->fsl)); 615 tcon_write(tcon, RK3576_EBC_DSP_VTIMING1, 616 RK3576_DSP_VACT_END(panel->fsl + panel->fbl + panel->fdl) | 617 RK3576_DSP_VACT_ST(panel->fsl + panel->fbl)); 618 tcon_write(tcon, RK3576_EBC_DSP_ACT_INFO, 619 RK3576_DSP_HEIGHT(height) | 620 RK3576_DSP_WIDTH(width)); 621 tcon_write(tcon, RK3576_EBC_WIN_VIR, 622 RK3576_WIN_VIR_HEIGHT(vir_height) | 623 RK3576_WIN_VIR_WIDTH(vir_width)); 624 tcon_write(tcon, RK3576_EBC_WIN_ACT, 625 RK3576_WIN_ACT_HEIGHT(height) | 626 RK3576_WIN_ACT_WIDTH(width)); 627 tcon_write(tcon, RK3576_EBC_WIN_DSP, 628 RK3576_WIN_DSP_HEIGHT(height) | 629 RK3576_WIN_DSP_WIDTH(width)); 630 tcon_write(tcon, RK3576_EBC_WIN_DSP_ST, 631 RK3576_WIN_DSP_YST(panel->fsl + panel->fbl) | 632 RK3576_WIN_DSP_XST(panel->lsl + panel->lbl)); 633 634 /* 635 * win2 fifo is 512x64, win fifo is 256x64, 636 * we set fifo almost value (fifo_size - 16(brust_length)) 637 * 638 * dma_burst_length mean axi burst length = 16 639 */ 640 tcon_write(tcon, RK3576_EBC_WIN_CTRL, 641 RK3576_WIN2_FIFO_ALMOST_FULL_LEVEL(496) | 642 RK3576_DMA_BURST_LENGTH(0) | 643 RK3576_WIN_FIFO_ALMOST_FULL_LEVEL(240) | 644 RK3576_WIN_FMT(Y_DATA_4BPP)); 645 646 /* win0 always enable */ 647 tcon_write(tcon, RK3576_EBC_WIN0_CTRL, RK3576_WIN_AXI_GATHER_NUM(8) | 648 RK3576_WIN_AXI_GATHER_EN | RK3576_WIN_RID(1) | 649 RK3576_WIN_EN); 650 tcon_write(tcon, RK3576_EBC_WIN1_CTRL, RK3576_WIN_RID(2)); 651 tcon_write(tcon, RK3576_EBC_WIN2_CTRL, RK3576_WIN_RID(3)); 652 653 /* 654 * RK3576_EBC_EPD_CTRL info: 655 * DSP_GD_END : GCLK falling edge point(SCLK), which count from the rising edge of hsync 656 * DSP_GD_ST: GCLK rising edge point(SCLK), which count from the rising edge of hsync 657 * DSP_THREE_WIN_MODE: 0: lut mode or direct mode; 1: three win mode 658 * DSP_SDDW_MODE: 0: 8 bit data output; 1: 16 bit data output 659 * EPD_AUO: 0: EINK; 1:AUO 660 * EPD_GDRL: gate scanning direction: 1: button to top 0: top to button 661 * EPD_SDSHR: source scanning direction 1: right to left 0: left to right 662 */ 663 tcon_write(tcon, RK3576_EBC_EPD_CTRL, RK3576_EINK_MODE_SWAP(1) | 664 RK3576_DSP_GD_ST(panel->lsl + panel->gdck_sta) | 665 RK3576_DSP_GD_END(panel->lsl + panel->gdck_sta + panel->lgonl) | 666 RK3576_DSP_THREE_WIN_MODE(0) | 667 RK3576_DSP_SDDW_MODE(!!panel->panel_16bit) | 668 RK3576_EPD_AUO(0) | 669 RK3576_EPD_GDRL(1) | 670 RK3576_EPD_SDSHR(1)); 671 672 tcon_write(tcon, RK3576_EBC_DSP_START, 0); 673 tcon_write(tcon, RK3576_EBC_DSP_CTRL2, 674 RK3576_SW_BURST_CTRL | RK3576_DSP_SDCE_WIDTH(panel->ldl)); 675 676 tcon_write(tcon, RK3576_EBC_DSP_CTRL, 677 RK3576_DSP_SWAP_MODE(panel->panel_16bit ? 2 : 3) | 678 RK3576_DSP_VCOM_MODE(1) | 679 RK3576_DSP_SDCLK_DIV(panel->panel_16bit ? 7 : 3)); 680 681 tcon_cfg_done(tcon); 682 683 ret = clk_set_rate(&tcon->dclk, 684 panel->sdck * ((panel->panel_16bit ? 7 : 3) + 1)); 685 if (ret < 0) { 686 printf("%s: set clock rate failed, %d\n", __func__, ret); 687 return ret; 688 } 689 690 return 0; 691 } 692 693 static int rk3576_ebc_tcon_dsp_mode_set(struct udevice *dev, int update_mode, 694 int display_mode, int three_win_mode, 695 int eink_mode) 696 { 697 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 698 699 tcon_write(tcon, RK3576_EBC_WIN1_CTRL, RK3576_WIN_AXI_GATHER_NUM(8) | 700 RK3576_WIN_AXI_GATHER_EN | 701 RK3576_WIN_RID(2) | 702 ((!!display_mode) | (!!three_win_mode))); 703 tcon_write(tcon, RK3576_EBC_WIN2_CTRL, RK3576_WIN_AXI_GATHER_NUM(8) | 704 RK3576_WIN_AXI_GATHER_EN | 705 RK3576_WIN_RID(3) | 706 (!!three_win_mode)); 707 708 tcon_update_bits(tcon, RK3576_EBC_DSP_CTRL, 709 RK3576_UPDATE_MODE_MASK | RK3576_DISPLAY_MODE_MASK, 710 RK3576_DSP_UPDATE_MODE(!!update_mode) | 711 RK3576_DSP_DISPLAY_MODE(!!display_mode)); 712 tcon_update_bits(tcon, RK3576_EBC_EPD_CTRL, RK3576_THREE_WIN_MODE_MASK, 713 RK3576_DSP_THREE_WIN_MODE(!!three_win_mode)); 714 /* always set frm start bit 0 before real frame start */ 715 tcon_update_bits(tcon, RK3576_EBC_DSP_CTRL2, RK3576_DSP_EINK_MODE_MASK, 716 RK3576_DSP_EINK_MODE(!!eink_mode)); 717 tcon_cfg_done(tcon); 718 719 return 0; 720 } 721 722 static int rk3576_ebc_tcon_frame_start(struct udevice *dev, int frame_total) 723 { 724 struct ebc_tcon_priv *tcon = dev_get_priv(dev); 725 726 tcon_write(tcon, RK3576_EBC_INT_STATUS, RK3576_LINE_FLAG_INT_MASK | 727 RK3576_DSP_FRM_INT_MASK | RK3576_FRM_END_INT_MASK | 728 RK3576_WIN2_EMPTY_INT_MASK | RK3576_WIN1_EMPTY_INT_MASK | 729 RK3576_WIN0_EMPTY_INT_MASK); 730 /* always set frm start bit 0 before real frame start */ 731 tcon_update_bits(tcon, RK3576_EBC_DSP_CTRL2, RK3576_DSP_FRM_TOTAL_MASK, 732 RK3576_DSP_FRM_TOTAL(frame_total - 1)); 733 tcon_cfg_done(tcon); 734 735 last_frame_done = 0; 736 tcon_write(tcon, RK3576_EBC_DSP_START, 1); 737 738 return 0; 739 } 740 #endif 741 742 static int rk_ebc_tcon_probe(struct udevice *dev) 743 { 744 int ret; 745 struct ebc_tcon_priv *priv = dev_get_priv(dev); 746 struct driver *driver = (struct driver *)dev->driver; 747 const struct rk_ebc_tcon_ops *tcon_ops; 748 #ifdef CONFIG_IRQ 749 u32 interrupt[2]; 750 int irq; 751 #endif 752 753 tcon_ops = (const struct rk_ebc_tcon_ops *)dev_get_driver_data(dev); 754 driver->ops = tcon_ops; 755 756 priv->dev = dev; 757 ret = clk_get_by_name(dev, "dclk", &priv->dclk); 758 if (ret < 0) { 759 printf("%s get clock fail! %d\n", __func__, ret); 760 return -EINVAL; 761 } 762 763 #ifdef CONFIG_IRQ 764 ret = dev_read_u32_array(dev, "interrupts", interrupt, 2); 765 if (ret) { 766 printf("read ebc irq failed:%d\n", ret); 767 return ret; 768 } 769 770 /* convert to Shared Peripheral Interrupt */ 771 irq = interrupt[1] + 32; 772 irq_install_handler(irq, ebc_irq_handler, dev); 773 irq_handler_enable(irq); 774 #endif 775 return 0; 776 } 777 778 #ifdef CONFIG_ROCKCHIP_RK3568 779 const struct rk_ebc_tcon_ops rk3568_ebc_tcon_funcs = { 780 .enable = ebc_tcon_enable, 781 .disable = ebc_tcon_disable, 782 .dsp_mode_set = ebc_tcon_dsp_mode_set, 783 .image_addr_set = ebc_tcon_image_addr_set, 784 .frame_addr_set = ebc_tcon_frame_addr_set, 785 .lut_data_set = ebc_tcon_lut_data_set, 786 .frame_start = ebc_tcon_frame_start, 787 .wait_for_last_frame_complete = wait_for_last_frame_complete, 788 }; 789 #endif 790 791 #ifdef CONFIG_ROCKCHIP_RK3576 792 const struct rk_ebc_tcon_ops rk3576_ebc_tcon_funcs = { 793 .enable = rk3576_ebc_tcon_enable, 794 .disable = ebc_tcon_disable, 795 .dsp_mode_set = rk3576_ebc_tcon_dsp_mode_set, 796 .image_addr_set = ebc_tcon_image_addr_set, 797 .frame_addr_set = ebc_tcon_frame_addr_set, 798 .lut_data_set = ebc_tcon_lut_data_set, 799 .frame_start = rk3576_ebc_tcon_frame_start, 800 .wait_for_last_frame_complete = wait_for_last_frame_complete, 801 }; 802 #endif 803 804 static int rk_ebc_tcon_ofdata_to_platdata(struct udevice *dev) 805 { 806 fdt_size_t size; 807 fdt_addr_t addr; 808 struct ebc_tcon_priv *priv = dev_get_priv(dev); 809 810 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 811 if (priv->grf <= 0) { 812 debug("%s: Get syscon grf failed (ret=%p)\n", 813 __func__, priv->grf); 814 return -ENXIO; 815 } 816 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); 817 if (priv->pmugrf <= 0) { 818 debug("%s: Get syscon pmugrf failed (ret=%p)\n", 819 __func__, priv->grf); 820 return -ENXIO; 821 } 822 addr = dev_read_addr_size(dev, "reg", &size); 823 if (addr == FDT_ADDR_T_NONE) { 824 debug("%s: Get ebc_tcon address failed\n", __func__); 825 return -ENXIO; 826 } 827 828 priv->reg = ioremap(addr, size); 829 priv->reg_len = size; 830 priv->regcache = malloc(size); 831 memset(priv->regcache, 0, size); 832 return 0; 833 } 834 835 static const struct udevice_id ebc_tcon_ids[] = { 836 #ifdef CONFIG_ROCKCHIP_RK3568 837 { 838 .compatible = "rockchip,rk3568-ebc-tcon", 839 .data = (ulong)&rk3568_ebc_tcon_funcs, 840 }, 841 #endif 842 #ifdef CONFIG_ROCKCHIP_RK3576 843 { 844 .compatible = "rockchip,rk3576-ebc-tcon", 845 .data = (ulong)&rk3576_ebc_tcon_funcs, 846 }, 847 #endif 848 {} 849 }; 850 851 U_BOOT_DRIVER(rk_ebc_tcon) = { 852 .name = "rk_ebc_tcon", 853 .id = UCLASS_EBC, 854 .of_match = ebc_tcon_ids, 855 .ofdata_to_platdata = rk_ebc_tcon_ofdata_to_platdata, 856 .probe = rk_ebc_tcon_probe, 857 .priv_auto_alloc_size = sizeof(struct ebc_tcon_priv), 858 }; 859 860 UCLASS_DRIVER(ebc_tcon) = { 861 .id = UCLASS_EBC, 862 .name = "ebc_tcon", 863 }; 864 865