193a7515aSWenping Zhang /* 293a7515aSWenping Zhang * (C) Copyright 2020 Rockchip Electronics Co., Ltd 393a7515aSWenping Zhang * 493a7515aSWenping Zhang * SPDX-License-Identifier: GPL-2.0+ 593a7515aSWenping Zhang * Author: Wenping Zhang <wenping.zhang@rock-chips.com> 693a7515aSWenping Zhang */ 793a7515aSWenping Zhang 893a7515aSWenping Zhang #ifndef RK_EBC_H 993a7515aSWenping Zhang #define RK_EBC_H 1093a7515aSWenping Zhang 1193a7515aSWenping Zhang #include "epdlut/epd_lut.h" 1293a7515aSWenping Zhang 1393a7515aSWenping Zhang struct ebc_panel { 1493a7515aSWenping Zhang u32 width; 1593a7515aSWenping Zhang u32 height; 169876686dSWenping Zhang u32 vir_width; 179876686dSWenping Zhang u32 vir_height; 1893a7515aSWenping Zhang u32 width_mm; 1993a7515aSWenping Zhang u32 height_mm; 2093a7515aSWenping Zhang 2193a7515aSWenping Zhang u32 sdck; 2293a7515aSWenping Zhang u32 lsl; 2393a7515aSWenping Zhang u32 lbl; 2493a7515aSWenping Zhang u32 ldl; 2593a7515aSWenping Zhang u32 lel; 2693a7515aSWenping Zhang u32 gdck_sta; 2793a7515aSWenping Zhang u32 lgonl; 2893a7515aSWenping Zhang u32 fsl; 2993a7515aSWenping Zhang u32 fbl; 3093a7515aSWenping Zhang u32 fdl; 3193a7515aSWenping Zhang u32 fel; 3293a7515aSWenping Zhang u32 panel_16bit; 3393a7515aSWenping Zhang u32 panel_color; 3493a7515aSWenping Zhang u32 mirror; 35dfc47936SZorro Liu u32 rearrange; 36*1020d760SChaoyi Chen u32 sdoe_mode; 37*1020d760SChaoyi Chen u32 sdce_width; 3893a7515aSWenping Zhang u32 disp_pbuf; 3993a7515aSWenping Zhang u32 disp_pbuf_size; 4093a7515aSWenping Zhang u32 *lut_pbuf; 4193a7515aSWenping Zhang u32 lut_pbuf_size; 4293a7515aSWenping Zhang struct epd_lut_data lut_data; 4393a7515aSWenping Zhang }; 4493a7515aSWenping Zhang 4593a7515aSWenping Zhang struct rk_ebc_tcon_ops { 4693a7515aSWenping Zhang int (*enable)(struct udevice *dev, struct ebc_panel *panel); 4793a7515aSWenping Zhang int (*disable)(struct udevice *dev); 4893a7515aSWenping Zhang int (*dsp_mode_set)(struct udevice *dev, int update_mode, 4993a7515aSWenping Zhang int display_mode, int three_win_mode, 5093a7515aSWenping Zhang int eink_mode); 5193a7515aSWenping Zhang int (*image_addr_set)(struct udevice *dev, u32 pre_image_addr, 5293a7515aSWenping Zhang u32 cur_image_addr); 5393a7515aSWenping Zhang int (*frame_addr_set)(struct udevice *dev, u32 frame_addr); 5493a7515aSWenping Zhang int (*lut_data_set)(struct udevice *dev, unsigned int *lut_data, 5593a7515aSWenping Zhang int frame_count, int lut_32); 5693a7515aSWenping Zhang int (*frame_start)(struct udevice *dev, int frame_total); 5793a7515aSWenping Zhang int (*wait_for_last_frame_complete)(struct udevice *dev); 5893a7515aSWenping Zhang }; 5993a7515aSWenping Zhang 6093a7515aSWenping Zhang #define ebc_tcon_get_ops(dev) ((struct rk_ebc_tcon_ops *)(dev)->driver->ops) 6193a7515aSWenping Zhang 6293a7515aSWenping Zhang /* 6393a7515aSWenping Zhang *interface for ebc power control 6493a7515aSWenping Zhang */ 6593a7515aSWenping Zhang struct rk_ebc_pwr_ops { 6693a7515aSWenping Zhang int (*power_on)(struct udevice *dev); 6793a7515aSWenping Zhang int (*power_down)(struct udevice *dev); 6893a7515aSWenping Zhang int (*temp_get)(struct udevice *dev, u32 *temp); 6993a7515aSWenping Zhang int (*vcom_set)(struct udevice *dev, u32 vcom); 7093a7515aSWenping Zhang }; 7193a7515aSWenping Zhang 7293a7515aSWenping Zhang #define ebc_pwr_get_ops(dev) ((struct rk_ebc_pwr_ops *)(dev)->driver->ops) 7393a7515aSWenping Zhang 7493a7515aSWenping Zhang //display mode define 7593a7515aSWenping Zhang #define DIRECT_MODE 0 7693a7515aSWenping Zhang #define LUT_MODE 1 7793a7515aSWenping Zhang #define THREE_WIN_MODE 1 7893a7515aSWenping Zhang #define EINK_MODE 1 7993a7515aSWenping Zhang 8093a7515aSWenping Zhang #endif 81