1 /* 2 * PXA LCD Controller 3 * 4 * (C) Copyright 2001-2002 5 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 /************************************************************************/ 11 /* ** HEADER FILES */ 12 /************************************************************************/ 13 14 #include <common.h> 15 #include <asm/arch/pxa-regs.h> 16 #include <asm/io.h> 17 #include <lcd.h> 18 #include <linux/types.h> 19 #include <stdarg.h> 20 #include <stdio_dev.h> 21 22 /* #define DEBUG */ 23 24 #ifdef CONFIG_LCD 25 26 /*----------------------------------------------------------------------*/ 27 /* 28 * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for 29 * your display. 30 */ 31 32 #ifdef CONFIG_PXA_VGA 33 /* LCD outputs connected to a video DAC */ 34 # define LCD_BPP LCD_COLOR8 35 36 /* you have to set lccr0 and lccr3 (including pcd) */ 37 # define REG_LCCR0 0x003008f8 38 # define REG_LCCR3 0x0300FF01 39 40 /* 640x480x16 @ 61 Hz */ 41 vidinfo_t panel_info = { 42 .vl_col = 640, 43 .vl_row = 480, 44 .vl_width = 640, 45 .vl_height = 480, 46 .vl_clkp = CONFIG_SYS_HIGH, 47 .vl_oep = CONFIG_SYS_HIGH, 48 .vl_hsp = CONFIG_SYS_HIGH, 49 .vl_vsp = CONFIG_SYS_HIGH, 50 .vl_dp = CONFIG_SYS_HIGH, 51 .vl_bpix = LCD_BPP, 52 .vl_lbw = 0, 53 .vl_splt = 0, 54 .vl_clor = 0, 55 .vl_tft = 1, 56 .vl_hpw = 40, 57 .vl_blw = 56, 58 .vl_elw = 56, 59 .vl_vpw = 20, 60 .vl_bfw = 8, 61 .vl_efw = 8, 62 }; 63 #endif /* CONFIG_PXA_VIDEO */ 64 65 /*----------------------------------------------------------------------*/ 66 #ifdef CONFIG_SHARP_LM8V31 67 68 # define LCD_BPP LCD_COLOR8 69 # define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */ 70 71 /* you have to set lccr0 and lccr3 (including pcd) */ 72 # define REG_LCCR0 0x0030087C 73 # define REG_LCCR3 0x0340FF08 74 75 vidinfo_t panel_info = { 76 .vl_col = 640, 77 .vl_row = 480, 78 .vl_width = 157, 79 .vl_height = 118, 80 .vl_clkp = CONFIG_SYS_HIGH, 81 .vl_oep = CONFIG_SYS_HIGH, 82 .vl_hsp = CONFIG_SYS_HIGH, 83 .vl_vsp = CONFIG_SYS_HIGH, 84 .vl_dp = CONFIG_SYS_HIGH, 85 .vl_bpix = LCD_BPP, 86 .vl_lbw = 0, 87 .vl_splt = 1, 88 .vl_clor = 1, 89 .vl_tft = 0, 90 .vl_hpw = 1, 91 .vl_blw = 3, 92 .vl_elw = 3, 93 .vl_vpw = 1, 94 .vl_bfw = 0, 95 .vl_efw = 0, 96 }; 97 #endif /* CONFIG_SHARP_LM8V31 */ 98 /*----------------------------------------------------------------------*/ 99 #ifdef CONFIG_VOIPAC_LCD 100 101 # define LCD_BPP LCD_COLOR8 102 # define LCD_INVERT_COLORS 103 104 /* you have to set lccr0 and lccr3 (including pcd) */ 105 # define REG_LCCR0 0x043008f8 106 # define REG_LCCR3 0x0340FF08 107 108 vidinfo_t panel_info = { 109 .vl_col = 640, 110 .vl_row = 480, 111 .vl_width = 157, 112 .vl_height = 118, 113 .vl_clkp = CONFIG_SYS_HIGH, 114 .vl_oep = CONFIG_SYS_HIGH, 115 .vl_hsp = CONFIG_SYS_HIGH, 116 .vl_vsp = CONFIG_SYS_HIGH, 117 .vl_dp = CONFIG_SYS_HIGH, 118 .vl_bpix = LCD_BPP, 119 .vl_lbw = 0, 120 .vl_splt = 1, 121 .vl_clor = 1, 122 .vl_tft = 1, 123 .vl_hpw = 32, 124 .vl_blw = 144, 125 .vl_elw = 32, 126 .vl_vpw = 2, 127 .vl_bfw = 13, 128 .vl_efw = 30, 129 }; 130 #endif /* CONFIG_VOIPAC_LCD */ 131 132 /*----------------------------------------------------------------------*/ 133 #ifdef CONFIG_HITACHI_SX14 134 /* Hitachi SX14Q004-ZZA color STN LCD */ 135 #define LCD_BPP LCD_COLOR8 136 137 /* you have to set lccr0 and lccr3 (including pcd) */ 138 #define REG_LCCR0 0x00301079 139 #define REG_LCCR3 0x0340FF20 140 141 vidinfo_t panel_info = { 142 .vl_col = 320, 143 .vl_row = 240, 144 .vl_width = 167, 145 .vl_height = 109, 146 .vl_clkp = CONFIG_SYS_HIGH, 147 .vl_oep = CONFIG_SYS_HIGH, 148 .vl_hsp = CONFIG_SYS_HIGH, 149 .vl_vsp = CONFIG_SYS_HIGH, 150 .vl_dp = CONFIG_SYS_HIGH, 151 .vl_bpix = LCD_BPP, 152 .vl_lbw = 1, 153 .vl_splt = 0, 154 .vl_clor = 1, 155 .vl_tft = 0, 156 .vl_hpw = 1, 157 .vl_blw = 1, 158 .vl_elw = 1, 159 .vl_vpw = 7, 160 .vl_bfw = 0, 161 .vl_efw = 0, 162 }; 163 #endif /* CONFIG_HITACHI_SX14 */ 164 165 /*----------------------------------------------------------------------*/ 166 #ifdef CONFIG_LMS283GF05 167 168 # define LCD_BPP LCD_COLOR8 169 # define LCD_INVERT_COLORS 170 171 /* you have to set lccr0 and lccr3 (including pcd) */ 172 # define REG_LCCR0 0x043008f8 173 # define REG_LCCR3 0x03b00009 174 175 vidinfo_t panel_info = { 176 .vl_col = 240, 177 .vl_row = 320, 178 .vl_rot = 3, 179 .vl_width = 240, 180 .vl_height = 320, 181 .vl_clkp = CONFIG_SYS_HIGH, 182 .vl_oep = CONFIG_SYS_LOW, 183 .vl_hsp = CONFIG_SYS_LOW, 184 .vl_vsp = CONFIG_SYS_LOW, 185 .vl_dp = CONFIG_SYS_HIGH, 186 .vl_bpix = LCD_BPP, 187 .vl_lbw = 0, 188 .vl_splt = 1, 189 .vl_clor = 1, 190 .vl_tft = 1, 191 .vl_hpw = 4, 192 .vl_blw = 4, 193 .vl_elw = 8, 194 .vl_vpw = 4, 195 .vl_bfw = 4, 196 .vl_efw = 8, 197 }; 198 #endif /* CONFIG_LMS283GF05 */ 199 200 /*----------------------------------------------------------------------*/ 201 202 #ifdef CONFIG_ACX517AKN 203 204 # define LCD_BPP LCD_COLOR8 205 206 /* you have to set lccr0 and lccr3 (including pcd) */ 207 # define REG_LCCR0 0x003008f9 208 # define REG_LCCR3 0x03700006 209 210 vidinfo_t panel_info = { 211 .vl_col = 320, 212 .vl_row = 320, 213 .vl_width = 320, 214 .vl_height = 320, 215 .vl_clkp = CONFIG_SYS_HIGH, 216 .vl_oep = CONFIG_SYS_LOW, 217 .vl_hsp = CONFIG_SYS_LOW, 218 .vl_vsp = CONFIG_SYS_LOW, 219 .vl_dp = CONFIG_SYS_HIGH, 220 .vl_bpix = LCD_BPP, 221 .vl_lbw = 0, 222 .vl_splt = 1, 223 .vl_clor = 1, 224 .vl_tft = 1, 225 .vl_hpw = 0x04, 226 .vl_blw = 0x1c, 227 .vl_elw = 0x08, 228 .vl_vpw = 0x01, 229 .vl_bfw = 0x07, 230 .vl_efw = 0x08, 231 }; 232 #endif /* CONFIG_ACX517AKN */ 233 234 #ifdef CONFIG_ACX544AKN 235 236 # define LCD_BPP LCD_COLOR16 237 238 /* you have to set lccr0 and lccr3 (including pcd) */ 239 # define REG_LCCR0 0x003008f9 240 # define REG_LCCR3 0x04700007 /* 16bpp */ 241 242 vidinfo_t panel_info = { 243 .vl_col = 320, 244 .vl_row = 320, 245 .vl_width = 320, 246 .vl_height = 320, 247 .vl_clkp = CONFIG_SYS_LOW, 248 .vl_oep = CONFIG_SYS_LOW, 249 .vl_hsp = CONFIG_SYS_LOW, 250 .vl_vsp = CONFIG_SYS_LOW, 251 .vl_dp = CONFIG_SYS_LOW, 252 .vl_bpix = LCD_BPP, 253 .vl_lbw = 0, 254 .vl_splt = 0, 255 .vl_clor = 1, 256 .vl_tft = 1, 257 .vl_hpw = 0x05, 258 .vl_blw = 0x13, 259 .vl_elw = 0x08, 260 .vl_vpw = 0x02, 261 .vl_bfw = 0x07, 262 .vl_efw = 0x05, 263 }; 264 #endif /* CONFIG_ACX544AKN */ 265 266 /*----------------------------------------------------------------------*/ 267 268 #ifdef CONFIG_LQ038J7DH53 269 270 # define LCD_BPP LCD_COLOR8 271 272 /* you have to set lccr0 and lccr3 (including pcd) */ 273 # define REG_LCCR0 0x003008f9 274 # define REG_LCCR3 0x03700004 275 276 vidinfo_t panel_info = { 277 .vl_col = 320, 278 .vl_row = 480, 279 .vl_width = 320, 280 .vl_height = 480, 281 .vl_clkp = CONFIG_SYS_HIGH, 282 .vl_oep = CONFIG_SYS_LOW, 283 .vl_hsp = CONFIG_SYS_LOW, 284 .vl_vsp = CONFIG_SYS_LOW, 285 .vl_dp = CONFIG_SYS_HIGH, 286 .vl_bpix = LCD_BPP, 287 .vl_lbw = 0, 288 .vl_splt = 1, 289 .vl_clor = 1, 290 .vl_tft = 1, 291 .vl_hpw = 0x04, 292 .vl_blw = 0x20, 293 .vl_elw = 0x01, 294 .vl_vpw = 0x01, 295 .vl_bfw = 0x04, 296 .vl_efw = 0x01, 297 }; 298 #endif /* CONFIG_ACX517AKN */ 299 300 /*----------------------------------------------------------------------*/ 301 302 #ifdef CONFIG_LITTLETON_LCD 303 # define LCD_BPP LCD_COLOR8 304 305 /* you have to set lccr0 and lccr3 (including pcd) */ 306 # define REG_LCCR0 0x003008f8 307 # define REG_LCCR3 0x0300FF04 308 309 vidinfo_t panel_info = { 310 .vl_col = 480, 311 .vl_row = 640, 312 .vl_width = 480, 313 .vl_height = 640, 314 .vl_clkp = CONFIG_SYS_HIGH, 315 .vl_oep = CONFIG_SYS_HIGH, 316 .vl_hsp = CONFIG_SYS_HIGH, 317 .vl_vsp = CONFIG_SYS_HIGH, 318 .vl_dp = CONFIG_SYS_HIGH, 319 .vl_bpix = LCD_BPP, 320 .vl_lbw = 0, 321 .vl_splt = 0, 322 .vl_clor = 0, 323 .vl_tft = 1, 324 .vl_hpw = 9, 325 .vl_blw = 8, 326 .vl_elw = 24, 327 .vl_vpw = 2, 328 .vl_bfw = 2, 329 .vl_efw = 4, 330 }; 331 #endif /* CONFIG_LITTLETON_LCD */ 332 333 /*----------------------------------------------------------------------*/ 334 335 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid); 336 static void pxafb_setup_gpio (vidinfo_t *vid); 337 static void pxafb_enable_controller (vidinfo_t *vid); 338 static int pxafb_init (vidinfo_t *vid); 339 340 /************************************************************************/ 341 /* --------------- PXA chipset specific functions ------------------- */ 342 /************************************************************************/ 343 344 ushort *configuration_get_cmap(void) 345 { 346 struct pxafb_info *fbi = &panel_info.pxa; 347 return (ushort *)fbi->palette; 348 } 349 350 void lcd_ctrl_init (void *lcdbase) 351 { 352 pxafb_init_mem(lcdbase, &panel_info); 353 pxafb_init(&panel_info); 354 pxafb_setup_gpio(&panel_info); 355 pxafb_enable_controller(&panel_info); 356 357 /* Enable flushing if we enabled dcache */ 358 lcd_set_flush_dcache(1); 359 } 360 361 /*----------------------------------------------------------------------*/ 362 #if LCD_BPP == LCD_COLOR8 363 void 364 lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue) 365 { 366 struct pxafb_info *fbi = &panel_info.pxa; 367 unsigned short *palette = (unsigned short *)fbi->palette; 368 u_int val; 369 370 if (regno < fbi->palette_size) { 371 val = ((red << 8) & 0xf800); 372 val |= ((green << 4) & 0x07e0); 373 val |= (blue & 0x001f); 374 375 #ifdef LCD_INVERT_COLORS 376 palette[regno] = ~val; 377 #else 378 palette[regno] = val; 379 #endif 380 } 381 382 debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n", 383 regno, &palette[regno], 384 red, green, blue, 385 palette[regno]); 386 } 387 #endif /* LCD_COLOR8 */ 388 389 /*----------------------------------------------------------------------*/ 390 __weak void lcd_enable(void) 391 { 392 } 393 394 /************************************************************************/ 395 /* ** PXA255 specific routines */ 396 /************************************************************************/ 397 398 /* 399 * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb, 400 * descriptors and palette areas. 401 */ 402 ulong calc_fbsize (void) 403 { 404 ulong size; 405 int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8; 406 407 size = line_length * panel_info.vl_row; 408 size += PAGE_SIZE; 409 410 return size; 411 } 412 413 static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid) 414 { 415 u_long palette_mem_size; 416 struct pxafb_info *fbi = &vid->pxa; 417 int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8; 418 419 fbi->screen = (u_long)lcdbase; 420 421 fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16; 422 palette_mem_size = fbi->palette_size * sizeof(u16); 423 424 debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size); 425 /* locate palette and descs at end of page following fb */ 426 fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size; 427 428 return 0; 429 } 430 #ifdef CONFIG_CPU_MONAHANS 431 static inline void pxafb_setup_gpio (vidinfo_t *vid) {} 432 #else 433 static void pxafb_setup_gpio (vidinfo_t *vid) 434 { 435 u_long lccr0; 436 437 /* 438 * setup is based on type of panel supported 439 */ 440 441 lccr0 = vid->pxa.reg_lccr0; 442 443 /* 4 bit interface */ 444 if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD)) 445 { 446 debug("Setting GPIO for 4 bit data\n"); 447 /* bits 58-61 */ 448 writel(readl(GPDR1) | (0xf << 26), GPDR1); 449 writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20), 450 GAFR1_U); 451 452 /* bits 74-77 */ 453 writel(readl(GPDR2) | (0xf << 10), GPDR2); 454 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20), 455 GAFR2_L); 456 } 457 458 /* 8 bit interface */ 459 else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) || 460 (!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS))) 461 { 462 debug("Setting GPIO for 8 bit data\n"); 463 /* bits 58-65 */ 464 writel(readl(GPDR1) | (0x3f << 26), GPDR1); 465 writel(readl(GPDR2) | (0x3), GPDR2); 466 467 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20), 468 GAFR1_U); 469 writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L); 470 471 /* bits 74-77 */ 472 writel(readl(GPDR2) | (0xf << 10), GPDR2); 473 writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20), 474 GAFR2_L); 475 } 476 477 /* 16 bit interface */ 478 else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS))) 479 { 480 debug("Setting GPIO for 16 bit data\n"); 481 /* bits 58-77 */ 482 writel(readl(GPDR1) | (0x3f << 26), GPDR1); 483 writel(readl(GPDR2) | 0x00003fff, GPDR2); 484 485 writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20), 486 GAFR1_U); 487 writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L); 488 } 489 else 490 { 491 printf("pxafb_setup_gpio: unable to determine bits per pixel\n"); 492 } 493 } 494 #endif 495 496 static void pxafb_enable_controller (vidinfo_t *vid) 497 { 498 debug("Enabling LCD controller\n"); 499 500 /* Sequence from 11.7.10 */ 501 writel(vid->pxa.reg_lccr3, LCCR3); 502 writel(vid->pxa.reg_lccr2, LCCR2); 503 writel(vid->pxa.reg_lccr1, LCCR1); 504 writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0); 505 writel(vid->pxa.fdadr0, FDADR0); 506 writel(vid->pxa.fdadr1, FDADR1); 507 writel(readl(LCCR0) | LCCR0_ENB, LCCR0); 508 509 #ifdef CONFIG_CPU_MONAHANS 510 writel(readl(CKENA) | CKENA_1_LCD, CKENA); 511 #else 512 writel(readl(CKEN) | CKEN16_LCD, CKEN); 513 #endif 514 515 debug("FDADR0 = 0x%08x\n", readl(FDADR0)); 516 debug("FDADR1 = 0x%08x\n", readl(FDADR1)); 517 debug("LCCR0 = 0x%08x\n", readl(LCCR0)); 518 debug("LCCR1 = 0x%08x\n", readl(LCCR1)); 519 debug("LCCR2 = 0x%08x\n", readl(LCCR2)); 520 debug("LCCR3 = 0x%08x\n", readl(LCCR3)); 521 } 522 523 static int pxafb_init (vidinfo_t *vid) 524 { 525 struct pxafb_info *fbi = &vid->pxa; 526 527 debug("Configuring PXA LCD\n"); 528 529 fbi->reg_lccr0 = REG_LCCR0; 530 fbi->reg_lccr3 = REG_LCCR3; 531 532 debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n", 533 vid->vl_col, vid->vl_hpw, 534 vid->vl_blw, vid->vl_elw); 535 debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n", 536 vid->vl_row, vid->vl_vpw, 537 vid->vl_bfw, vid->vl_efw); 538 539 fbi->reg_lccr1 = 540 LCCR1_DisWdth(vid->vl_col) + 541 LCCR1_HorSnchWdth(vid->vl_hpw) + 542 LCCR1_BegLnDel(vid->vl_blw) + 543 LCCR1_EndLnDel(vid->vl_elw); 544 545 fbi->reg_lccr2 = 546 LCCR2_DisHght(vid->vl_row) + 547 LCCR2_VrtSnchWdth(vid->vl_vpw) + 548 LCCR2_BegFrmDel(vid->vl_bfw) + 549 LCCR2_EndFrmDel(vid->vl_efw); 550 551 fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP); 552 fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH) 553 | (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH); 554 555 556 /* setup dma descriptors */ 557 fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16); 558 fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16); 559 fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16); 560 561 #define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \ 562 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \ 563 (vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8)) 564 565 /* populate descriptors */ 566 fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow; 567 fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL; 568 fbi->dmadesc_fblow->fidr = 0; 569 fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL; 570 571 flush_dcache_range((u32)fbi->dmadesc_fblow, 572 (u32)fbi->dmadesc_fblow + 573 sizeof(*fbi->dmadesc_fblow)); 574 575 fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */ 576 577 fbi->dmadesc_fbhigh->fsadr = fbi->screen; 578 fbi->dmadesc_fbhigh->fidr = 0; 579 fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL; 580 581 fbi->dmadesc_palette->fsadr = fbi->palette; 582 fbi->dmadesc_palette->fidr = 0; 583 fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL; 584 585 if( NBITS(vid->vl_bpix) < 12) 586 { 587 /* assume any mode with <12 bpp is palette driven */ 588 fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh; 589 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette; 590 flush_dcache_range((u32)fbi->dmadesc_fbhigh, 591 (u32)fbi->dmadesc_fbhigh + 592 sizeof(*fbi->dmadesc_fbhigh)); 593 flush_dcache_range((u32)fbi->dmadesc_palette, 594 (u32)fbi->dmadesc_palette + 595 sizeof(*fbi->dmadesc_palette)); 596 /* flips back and forth between pal and fbhigh */ 597 fbi->fdadr0 = (u_long)fbi->dmadesc_palette; 598 } 599 else 600 { 601 flush_dcache_range((u32)fbi->dmadesc_fbhigh, 602 (u32)fbi->dmadesc_fbhigh + 603 sizeof(*fbi->dmadesc_fbhigh)); 604 /* palette shouldn't be loaded in true-color mode */ 605 fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh; 606 fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */ 607 } 608 609 debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow); 610 debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh); 611 debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette); 612 613 debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr); 614 debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr); 615 debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr); 616 617 debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr); 618 debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr); 619 debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr); 620 621 debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd); 622 debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd); 623 debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd); 624 625 return 0; 626 } 627 628 /************************************************************************/ 629 /************************************************************************/ 630 631 #endif /* CONFIG_LCD */ 632