1 /* 2 * Copyright 2014 Freescale Semiconductor, Inc. 3 * 4 * FSL DCU Framebuffer driver 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/io.h> 10 #include <common.h> 11 #include <fdt_support.h> 12 #include <fsl_dcu_fb.h> 13 #include <linux/fb.h> 14 #include <malloc.h> 15 #include <video_fb.h> 16 #include "videomodes.h" 17 18 /* Convert the X,Y resolution pair into a single number */ 19 #define RESOLUTION(x, y) (((u32)(x) << 16) | (y)) 20 21 #ifdef CONFIG_SYS_FSL_DCU_LE 22 #define dcu_read32 in_le32 23 #define dcu_write32 out_le32 24 #elif defined(CONFIG_SYS_FSL_DCU_BE) 25 #define dcu_read32 in_be32 26 #define dcu_write32 out_be32 27 #endif 28 29 #define DCU_MODE_BLEND_ITER(x) ((x) << 20) 30 #define DCU_MODE_RASTER_EN (1 << 14) 31 #define DCU_MODE_NORMAL 1 32 #define DCU_MODE_COLORBAR 3 33 #define DCU_BGND_R(x) ((x) << 16) 34 #define DCU_BGND_G(x) ((x) << 8) 35 #define DCU_BGND_B(x) (x) 36 #define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16) 37 #define DCU_DISP_SIZE_DELTA_X(x) (x) 38 #define DCU_HSYN_PARA_BP(x) ((x) << 22) 39 #define DCU_HSYN_PARA_PW(x) ((x) << 11) 40 #define DCU_HSYN_PARA_FP(x) (x) 41 #define DCU_VSYN_PARA_BP(x) ((x) << 22) 42 #define DCU_VSYN_PARA_PW(x) ((x) << 11) 43 #define DCU_VSYN_PARA_FP(x) (x) 44 #define DCU_SYN_POL_INV_PXCK_FALL (1 << 6) 45 #define DCU_SYN_POL_NEG_REMAIN (0 << 5) 46 #define DCU_SYN_POL_INV_VS_LOW (1 << 1) 47 #define DCU_SYN_POL_INV_HS_LOW (1) 48 #define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16) 49 #define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8) 50 #define DCU_THRESHOLD_OUT_BUF_LOW(x) (x) 51 #define DCU_UPDATE_MODE_MODE (1 << 31) 52 #define DCU_UPDATE_MODE_READREG (1 << 30) 53 54 #define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16) 55 #define DCU_CTRLDESCLN_1_WIDTH(x) (x) 56 #define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16) 57 #define DCU_CTRLDESCLN_2_POSX(x) (x) 58 #define DCU_CTRLDESCLN_4_EN (1 << 31) 59 #define DCU_CTRLDESCLN_4_TILE_EN (1 << 30) 60 #define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29) 61 #define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28) 62 #define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20) 63 #define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16) 64 #define DCU_CTRLDESCLN_4_RLE_EN (1 << 15) 65 #define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4) 66 #define DCU_CTRLDESCLN_4_BB_ON (1 << 2) 67 #define DCU_CTRLDESCLN_4_AB(x) (x) 68 #define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16) 69 #define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8) 70 #define DCU_CTRLDESCLN_5_CKMAX_B(x) (x) 71 #define DCU_CTRLDESCLN_6_CKMIN_R(x) ((x) << 16) 72 #define DCU_CTRLDESCLN_6_CKMIN_G(x) ((x) << 8) 73 #define DCU_CTRLDESCLN_6_CKMIN_B(x) (x) 74 #define DCU_CTRLDESCLN_7_TILE_VER(x) ((x) << 16) 75 #define DCU_CTRLDESCLN_7_TILE_HOR(x) (x) 76 #define DCU_CTRLDESCLN_8_FG_FCOLOR(x) (x) 77 #define DCU_CTRLDESCLN_9_BG_BCOLOR(x) (x) 78 79 #define BPP_16_RGB565 4 80 #define BPP_24_RGB888 5 81 #define BPP_32_ARGB8888 6 82 83 DECLARE_GLOBAL_DATA_PTR; 84 85 /* 86 * This setting is used for the TWR_LCD_RGB card 87 */ 88 static struct fb_videomode fsl_dcu_mode_480_272 = { 89 .name = "480x272-60", 90 .refresh = 60, 91 .xres = 480, 92 .yres = 272, 93 .pixclock = 91996, 94 .left_margin = 2, 95 .right_margin = 2, 96 .upper_margin = 1, 97 .lower_margin = 1, 98 .hsync_len = 41, 99 .vsync_len = 2, 100 .sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, 101 .vmode = FB_VMODE_NONINTERLACED 102 }; 103 104 /* 105 * This setting is used for Siliconimage SiI9022A HDMI 106 */ 107 static struct fb_videomode fsl_dcu_mode_640_480 = { 108 .name = "640x480-60", 109 .refresh = 60, 110 .xres = 640, 111 .yres = 480, 112 .pixclock = 39722, 113 .left_margin = 48, 114 .right_margin = 16, 115 .upper_margin = 33, 116 .lower_margin = 10, 117 .hsync_len = 96, 118 .vsync_len = 2, 119 .sync = 0, 120 .vmode = FB_VMODE_NONINTERLACED, 121 }; 122 123 /* 124 * DCU register map 125 */ 126 struct dcu_reg { 127 u32 desc_cursor[4]; 128 u32 mode; 129 u32 bgnd; 130 u32 disp_size; 131 u32 hsyn_para; 132 u32 vsyn_para; 133 u32 synpol; 134 u32 threshold; 135 u32 int_status; 136 u32 int_mask; 137 u32 colbar[8]; 138 u32 div_ratio; 139 u32 sign_calc[2]; 140 u32 crc_val; 141 u8 res_064[0x6c-0x64]; 142 u32 parr_err_status1; 143 u8 res_070[0x7c-0x70]; 144 u32 parr_err_status3; 145 u32 mparr_err_status1; 146 u8 res_084[0x90-0x84]; 147 u32 mparr_err_status3; 148 u32 threshold_inp_buf[2]; 149 u8 res_09c[0xa0-0x9c]; 150 u32 luma_comp; 151 u32 chroma_red; 152 u32 chroma_green; 153 u32 chroma_blue; 154 u32 crc_pos; 155 u32 lyr_intpol_en; 156 u32 lyr_luma_comp; 157 u32 lyr_chrm_red; 158 u32 lyr_chrm_grn; 159 u32 lyr_chrm_blue; 160 u8 res_0c4[0xcc-0xc8]; 161 u32 update_mode; 162 u32 underrun; 163 u8 res_0d4[0x100-0xd4]; 164 u32 gpr; 165 u32 slr_l[2]; 166 u32 slr_disp_size; 167 u32 slr_hvsync_para; 168 u32 slr_pol; 169 u32 slr_l_transp[2]; 170 u8 res_120[0x200-0x120]; 171 u32 ctrldescl[DCU_LAYER_MAX_NUM][16]; 172 }; 173 174 static struct fb_info info; 175 176 static void reset_total_layers(void) 177 { 178 struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; 179 int i; 180 181 for (i = 0; i < DCU_LAYER_MAX_NUM; i++) { 182 dcu_write32(®s->ctrldescl[i][0], 0); 183 dcu_write32(®s->ctrldescl[i][1], 0); 184 dcu_write32(®s->ctrldescl[i][2], 0); 185 dcu_write32(®s->ctrldescl[i][3], 0); 186 dcu_write32(®s->ctrldescl[i][4], 0); 187 dcu_write32(®s->ctrldescl[i][5], 0); 188 dcu_write32(®s->ctrldescl[i][6], 0); 189 dcu_write32(®s->ctrldescl[i][7], 0); 190 dcu_write32(®s->ctrldescl[i][8], 0); 191 dcu_write32(®s->ctrldescl[i][9], 0); 192 dcu_write32(®s->ctrldescl[i][10], 0); 193 } 194 } 195 196 static int layer_ctrldesc_init(int index, u32 pixel_format) 197 { 198 struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; 199 unsigned int bpp = BPP_24_RGB888; 200 201 dcu_write32(®s->ctrldescl[index][0], 202 DCU_CTRLDESCLN_1_HEIGHT(info.var.yres) | 203 DCU_CTRLDESCLN_1_WIDTH(info.var.xres)); 204 205 dcu_write32(®s->ctrldescl[index][1], 206 DCU_CTRLDESCLN_2_POSY(0) | 207 DCU_CTRLDESCLN_2_POSX(0)); 208 209 dcu_write32(®s->ctrldescl[index][2], (unsigned int)info.screen_base); 210 211 switch (pixel_format) { 212 case 16: 213 bpp = BPP_16_RGB565; 214 break; 215 case 24: 216 bpp = BPP_24_RGB888; 217 break; 218 case 32: 219 bpp = BPP_32_ARGB8888; 220 break; 221 default: 222 printf("unsupported color depth: %u\n", pixel_format); 223 } 224 225 dcu_write32(®s->ctrldescl[index][3], 226 DCU_CTRLDESCLN_4_EN | 227 DCU_CTRLDESCLN_4_TRANS(0xff) | 228 DCU_CTRLDESCLN_4_BPP(bpp) | 229 DCU_CTRLDESCLN_4_AB(0)); 230 231 dcu_write32(®s->ctrldescl[index][4], 232 DCU_CTRLDESCLN_5_CKMAX_R(0xff) | 233 DCU_CTRLDESCLN_5_CKMAX_G(0xff) | 234 DCU_CTRLDESCLN_5_CKMAX_B(0xff)); 235 dcu_write32(®s->ctrldescl[index][5], 236 DCU_CTRLDESCLN_6_CKMIN_R(0) | 237 DCU_CTRLDESCLN_6_CKMIN_G(0) | 238 DCU_CTRLDESCLN_6_CKMIN_B(0)); 239 240 dcu_write32(®s->ctrldescl[index][6], 241 DCU_CTRLDESCLN_7_TILE_VER(0) | 242 DCU_CTRLDESCLN_7_TILE_HOR(0)); 243 244 dcu_write32(®s->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0)); 245 dcu_write32(®s->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0)); 246 247 return 0; 248 } 249 250 int fsl_dcu_init(unsigned int xres, unsigned int yres, 251 unsigned int pixel_format) 252 { 253 struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR; 254 unsigned int div, mode; 255 256 info.screen_size = 257 info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8); 258 259 if (info.screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) { 260 info.screen_size = 0; 261 return -ENOMEM; 262 } 263 264 /* Reserve framebuffer at the end of memory */ 265 gd->fb_base = gd->bd->bi_dram[0].start + 266 gd->bd->bi_dram[0].size - info.screen_size; 267 info.screen_base = (char *)gd->fb_base; 268 269 memset(info.screen_base, 0, info.screen_size); 270 271 reset_total_layers(); 272 273 dcu_write32(®s->disp_size, 274 DCU_DISP_SIZE_DELTA_Y(info.var.yres) | 275 DCU_DISP_SIZE_DELTA_X(info.var.xres / 16)); 276 277 dcu_write32(®s->hsyn_para, 278 DCU_HSYN_PARA_BP(info.var.left_margin) | 279 DCU_HSYN_PARA_PW(info.var.hsync_len) | 280 DCU_HSYN_PARA_FP(info.var.right_margin)); 281 282 dcu_write32(®s->vsyn_para, 283 DCU_VSYN_PARA_BP(info.var.upper_margin) | 284 DCU_VSYN_PARA_PW(info.var.vsync_len) | 285 DCU_VSYN_PARA_FP(info.var.lower_margin)); 286 287 dcu_write32(®s->synpol, 288 DCU_SYN_POL_INV_PXCK_FALL | 289 DCU_SYN_POL_NEG_REMAIN | 290 DCU_SYN_POL_INV_VS_LOW | 291 DCU_SYN_POL_INV_HS_LOW); 292 293 dcu_write32(®s->bgnd, 294 DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0)); 295 296 dcu_write32(®s->mode, 297 DCU_MODE_BLEND_ITER(2) | 298 DCU_MODE_RASTER_EN); 299 300 dcu_write32(®s->threshold, 301 DCU_THRESHOLD_LS_BF_VS(0x3) | 302 DCU_THRESHOLD_OUT_BUF_HIGH(0x78) | 303 DCU_THRESHOLD_OUT_BUF_LOW(0)); 304 305 mode = dcu_read32(®s->mode); 306 dcu_write32(®s->mode, mode | DCU_MODE_NORMAL); 307 308 layer_ctrldesc_init(0, pixel_format); 309 310 div = dcu_set_pixel_clock(info.var.pixclock); 311 dcu_write32(®s->div_ratio, (div - 1)); 312 313 dcu_write32(®s->update_mode, DCU_UPDATE_MODE_READREG); 314 315 return 0; 316 } 317 318 ulong board_get_usable_ram_top(ulong total_size) 319 { 320 return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB; 321 } 322 323 void *video_hw_init(void) 324 { 325 static GraphicDevice ctfb; 326 const char *options; 327 unsigned int depth = 0, freq = 0; 328 struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272; 329 330 if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq, 331 &options)) 332 return NULL; 333 334 /* Find the monitor port, which is a required option */ 335 if (!options) 336 return NULL; 337 if (strncmp(options, "monitor=", 8) != 0) 338 return NULL; 339 340 switch (RESOLUTION(ctfb.winSizeX, ctfb.winSizeY)) { 341 case RESOLUTION(480, 272): 342 fsl_dcu_mode_db = &fsl_dcu_mode_480_272; 343 break; 344 case RESOLUTION(640, 480): 345 fsl_dcu_mode_db = &fsl_dcu_mode_640_480; 346 break; 347 default: 348 printf("unsupported resolution %ux%u\n", 349 ctfb.winSizeX, ctfb.winSizeY); 350 } 351 352 info.var.xres = fsl_dcu_mode_db->xres; 353 info.var.yres = fsl_dcu_mode_db->yres; 354 info.var.bits_per_pixel = 32; 355 info.var.pixclock = fsl_dcu_mode_db->pixclock; 356 info.var.left_margin = fsl_dcu_mode_db->left_margin; 357 info.var.right_margin = fsl_dcu_mode_db->right_margin; 358 info.var.upper_margin = fsl_dcu_mode_db->upper_margin; 359 info.var.lower_margin = fsl_dcu_mode_db->lower_margin; 360 info.var.hsync_len = fsl_dcu_mode_db->hsync_len; 361 info.var.vsync_len = fsl_dcu_mode_db->vsync_len; 362 info.var.sync = fsl_dcu_mode_db->sync; 363 info.var.vmode = fsl_dcu_mode_db->vmode; 364 info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8; 365 366 if (platform_dcu_init(ctfb.winSizeX, ctfb.winSizeY, 367 options + 8, fsl_dcu_mode_db) < 0) 368 return NULL; 369 370 ctfb.frameAdrs = (unsigned int)info.screen_base; 371 ctfb.plnSizeX = ctfb.winSizeX; 372 ctfb.plnSizeY = ctfb.winSizeY; 373 374 ctfb.gdfBytesPP = 4; 375 ctfb.gdfIndex = GDF_32BIT_X888RGB; 376 377 ctfb.memSize = info.screen_size; 378 379 return &ctfb; 380 } 381 382 #if defined(CONFIG_OF_BOARD_SETUP) 383 int fsl_dcu_fixedfb_setup(void *blob) 384 { 385 u64 start, size; 386 int ret; 387 388 start = gd->bd->bi_dram[0].start; 389 size = gd->bd->bi_dram[0].size - info.screen_size; 390 391 /* 392 * Align size on section size (1 MiB). 393 */ 394 size &= 0xfff00000; 395 ret = fdt_fixup_memory_banks(blob, &start, &size, 1); 396 if (ret) { 397 eprintf("Cannot setup fb: Error reserving memory\n"); 398 return ret; 399 } 400 401 return 0; 402 } 403 #endif 404