108a7aa1eSSimon Glass /* 208a7aa1eSSimon Glass * Copyright (C) 2012 Samsung Electronics 308a7aa1eSSimon Glass * 408a7aa1eSSimon Glass * Author: Donghwa Lee <dh09.lee@samsung.com> 508a7aa1eSSimon Glass * 608a7aa1eSSimon Glass * SPDX-License-Identifier: GPL-2.0+ 708a7aa1eSSimon Glass */ 808a7aa1eSSimon Glass 908a7aa1eSSimon Glass #ifndef _EXYNOS_EDP_LOWLEVEL_H 1008a7aa1eSSimon Glass #define _EXYNOS_EDP_LOWLEVEL_H 1108a7aa1eSSimon Glass 12*8c9b8dc0SSimon Glass void exynos_dp_enable_video_bist(struct exynos_dp *dp_regs, 13*8c9b8dc0SSimon Glass unsigned int enable); 14*8c9b8dc0SSimon Glass void exynos_dp_enable_video_mute(struct exynos_dp *dp_regs, 15*8c9b8dc0SSimon Glass unsigned int enable); 16*8c9b8dc0SSimon Glass void exynos_dp_reset(struct exynos_dp *dp_regs); 17*8c9b8dc0SSimon Glass void exynos_dp_enable_sw_func(struct exynos_dp *dp_regs, unsigned int enable); 18*8c9b8dc0SSimon Glass unsigned int exynos_dp_set_analog_power_down(struct exynos_dp *dp_regs, 19*8c9b8dc0SSimon Glass unsigned int block, u32 enable); 20*8c9b8dc0SSimon Glass unsigned int exynos_dp_get_pll_lock_status(struct exynos_dp *dp_regs); 21*8c9b8dc0SSimon Glass int exynos_dp_init_analog_func(struct exynos_dp *dp_regs); 22*8c9b8dc0SSimon Glass void exynos_dp_init_hpd(struct exynos_dp *dp_regs); 23*8c9b8dc0SSimon Glass void exynos_dp_init_aux(struct exynos_dp *dp_regs); 24*8c9b8dc0SSimon Glass void exynos_dp_config_interrupt(struct exynos_dp *dp_regs); 25*8c9b8dc0SSimon Glass unsigned int exynos_dp_get_plug_in_status(struct exynos_dp *dp_regs); 26*8c9b8dc0SSimon Glass unsigned int exynos_dp_detect_hpd(struct exynos_dp *dp_regs); 27*8c9b8dc0SSimon Glass unsigned int exynos_dp_start_aux_transaction(struct exynos_dp *dp_regs); 28*8c9b8dc0SSimon Glass unsigned int exynos_dp_write_byte_to_dpcd(struct exynos_dp *dp_regs, 29*8c9b8dc0SSimon Glass unsigned int reg_addr, 3008a7aa1eSSimon Glass unsigned char data); 31*8c9b8dc0SSimon Glass unsigned int exynos_dp_read_byte_from_dpcd(struct exynos_dp *dp_regs, 32*8c9b8dc0SSimon Glass unsigned int reg_addr, 3308a7aa1eSSimon Glass unsigned char *data); 34*8c9b8dc0SSimon Glass unsigned int exynos_dp_write_bytes_to_dpcd(struct exynos_dp *dp_regs, 35*8c9b8dc0SSimon Glass unsigned int reg_addr, 3608a7aa1eSSimon Glass unsigned int count, 3708a7aa1eSSimon Glass unsigned char data[]); 38*8c9b8dc0SSimon Glass unsigned int exynos_dp_read_bytes_from_dpcd(struct exynos_dp *dp_regs, 39*8c9b8dc0SSimon Glass unsigned int reg_addr, 4008a7aa1eSSimon Glass unsigned int count, 4108a7aa1eSSimon Glass unsigned char data[]); 42*8c9b8dc0SSimon Glass int exynos_dp_select_i2c_device(struct exynos_dp *dp_regs, 43*8c9b8dc0SSimon Glass unsigned int device_addr, 4408a7aa1eSSimon Glass unsigned int reg_addr); 45*8c9b8dc0SSimon Glass int exynos_dp_read_byte_from_i2c(struct exynos_dp *dp_regs, 46*8c9b8dc0SSimon Glass unsigned int device_addr, 4708a7aa1eSSimon Glass unsigned int reg_addr, unsigned int *data); 48*8c9b8dc0SSimon Glass int exynos_dp_read_bytes_from_i2c(struct exynos_dp *dp_regs, 49*8c9b8dc0SSimon Glass unsigned int device_addr, 5008a7aa1eSSimon Glass unsigned int reg_addr, unsigned int count, 5108a7aa1eSSimon Glass unsigned char edid[]); 52*8c9b8dc0SSimon Glass void exynos_dp_reset_macro(struct exynos_dp *dp_regs); 53*8c9b8dc0SSimon Glass void exynos_dp_set_link_bandwidth(struct exynos_dp *dp_regs, 54*8c9b8dc0SSimon Glass unsigned char bwtype); 55*8c9b8dc0SSimon Glass unsigned char exynos_dp_get_link_bandwidth(struct exynos_dp *dp_regs); 56*8c9b8dc0SSimon Glass void exynos_dp_set_lane_count(struct exynos_dp *dp_regs, unsigned char count); 57*8c9b8dc0SSimon Glass unsigned int exynos_dp_get_lane_count(struct exynos_dp *dp_regs); 58*8c9b8dc0SSimon Glass unsigned char exynos_dp_get_lanex_pre_emphasis(struct exynos_dp *dp_regs, 5908a7aa1eSSimon Glass unsigned char lanecnt); 60*8c9b8dc0SSimon Glass void exynos_dp_set_lane_pre_emphasis(struct exynos_dp *dp_regs, 61*8c9b8dc0SSimon Glass unsigned int level, unsigned char lanecnt); 62*8c9b8dc0SSimon Glass void exynos_dp_set_lanex_pre_emphasis(struct exynos_dp *dp_regs, 63*8c9b8dc0SSimon Glass unsigned char request_val, 6408a7aa1eSSimon Glass unsigned char lanecnt); 65*8c9b8dc0SSimon Glass void exynos_dp_set_training_pattern(struct exynos_dp *dp_regs, 66*8c9b8dc0SSimon Glass unsigned int pattern); 67*8c9b8dc0SSimon Glass void exynos_dp_enable_enhanced_mode(struct exynos_dp *dp_regs, 68*8c9b8dc0SSimon Glass unsigned char enable); 69*8c9b8dc0SSimon Glass void exynos_dp_enable_scrambling(struct exynos_dp *dp_regs, 70*8c9b8dc0SSimon Glass unsigned int enable); 71*8c9b8dc0SSimon Glass int exynos_dp_init_video(struct exynos_dp *dp_regs); 72*8c9b8dc0SSimon Glass void exynos_dp_config_video_slave_mode(struct exynos_dp *dp_regs, 73*8c9b8dc0SSimon Glass struct edp_video_info *video_info); 74*8c9b8dc0SSimon Glass void exynos_dp_set_video_color_format(struct exynos_dp *dp_regs, 75*8c9b8dc0SSimon Glass struct edp_video_info *video_info); 76*8c9b8dc0SSimon Glass int exynos_dp_config_video_bist(struct exynos_dp *dp_regs, 77*8c9b8dc0SSimon Glass struct edp_device_info *edp_info); 78*8c9b8dc0SSimon Glass unsigned int exynos_dp_is_slave_video_stream_clock_on( 79*8c9b8dc0SSimon Glass struct exynos_dp *dp_regs); 80*8c9b8dc0SSimon Glass void exynos_dp_set_video_cr_mn(struct exynos_dp *dp_regs, unsigned int type, 81*8c9b8dc0SSimon Glass unsigned int m_value, unsigned int n_value); 82*8c9b8dc0SSimon Glass void exynos_dp_set_video_timing_mode(struct exynos_dp *dp_regs, 83*8c9b8dc0SSimon Glass unsigned int type); 84*8c9b8dc0SSimon Glass void exynos_dp_enable_video_master(struct exynos_dp *dp_regs, 85*8c9b8dc0SSimon Glass unsigned int enable); 86*8c9b8dc0SSimon Glass void exynos_dp_start_video(struct exynos_dp *dp_regs); 87*8c9b8dc0SSimon Glass unsigned int exynos_dp_is_video_stream_on(struct exynos_dp *dp_regs); 8808a7aa1eSSimon Glass 8908a7aa1eSSimon Glass #endif /* _EXYNOS_DP_LOWLEVEL_H */ 90