1 /* 2 * Copyright (C) 2012 Samsung Electronics 3 * 4 * Author: Donghwa Lee <dh09.lee@samsung.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <config.h> 10 #include <common.h> 11 #include <linux/err.h> 12 #include <asm/arch/cpu.h> 13 #include <asm/arch/dp_info.h> 14 #include <asm/arch/dp.h> 15 #include <fdtdec.h> 16 #include <libfdt.h> 17 18 /* Declare global data pointer */ 19 DECLARE_GLOBAL_DATA_PTR; 20 21 struct exynos_dp *dp_regs; 22 23 void exynos_dp_set_base_addr(void) 24 { 25 unsigned int node = fdtdec_next_compatible(gd->fdt_blob, 26 0, COMPAT_SAMSUNG_EXYNOS5_DP); 27 if (node <= 0) 28 debug("exynos_dp: Can't get device node for dp\n"); 29 30 dp_regs = (struct exynos_dp *)fdtdec_get_addr(gd->fdt_blob, 31 node, "reg"); 32 if (dp_regs == NULL) 33 debug("Can't get the DP base address\n"); 34 } 35 36 static void exynos_dp_enable_video_input(unsigned int enable) 37 { 38 unsigned int reg; 39 40 reg = readl(&dp_regs->video_ctl1); 41 reg &= ~VIDEO_EN_MASK; 42 43 /* enable video input */ 44 if (enable) 45 reg |= VIDEO_EN_MASK; 46 47 writel(reg, &dp_regs->video_ctl1); 48 49 return; 50 } 51 52 void exynos_dp_enable_video_bist(unsigned int enable) 53 { 54 /* enable video bist */ 55 unsigned int reg; 56 57 reg = readl(&dp_regs->video_ctl4); 58 reg &= ~VIDEO_BIST_MASK; 59 60 /* enable video bist */ 61 if (enable) 62 reg |= VIDEO_BIST_MASK; 63 64 writel(reg, &dp_regs->video_ctl4); 65 66 return; 67 } 68 69 void exynos_dp_enable_video_mute(unsigned int enable) 70 { 71 unsigned int reg; 72 73 reg = readl(&dp_regs->video_ctl1); 74 reg &= ~(VIDEO_MUTE_MASK); 75 if (enable) 76 reg |= VIDEO_MUTE_MASK; 77 78 writel(reg, &dp_regs->video_ctl1); 79 80 return; 81 } 82 83 84 static void exynos_dp_init_analog_param(void) 85 { 86 unsigned int reg; 87 88 /* 89 * Set termination 90 * Normal bandgap, Normal swing, Tx terminal registor 61 ohm 91 * 24M Phy clock, TX digital logic power is 100:1.0625V 92 */ 93 reg = SEL_BG_NEW_BANDGAP | TX_TERMINAL_CTRL_61_OHM | 94 SWING_A_30PER_G_NORMAL; 95 writel(reg, &dp_regs->analog_ctl1); 96 97 reg = SEL_24M | TX_DVDD_BIT_1_0625V; 98 writel(reg, &dp_regs->analog_ctl2); 99 100 /* 101 * Set power source for internal clk driver to 1.0625v. 102 * Select current reference of TX driver current to 00:Ipp/2+Ic/2. 103 * Set VCO range of PLL +- 0uA 104 */ 105 reg = DRIVE_DVDD_BIT_1_0625V | SEL_CURRENT_DEFAULT | VCO_BIT_000_MICRO; 106 writel(reg, &dp_regs->analog_ctl3); 107 108 /* 109 * Set AUX TX terminal resistor to 102 ohm 110 * Set AUX channel amplitude control 111 */ 112 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_52_OHM | TX_CUR1_2X | TX_CUR_4_MA; 113 writel(reg, &dp_regs->pll_filter_ctl1); 114 115 /* 116 * PLL loop filter bandwidth 117 * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz 118 * PLL digital power select: 1.2500V 119 */ 120 reg = CH3_AMP_0_MV | CH2_AMP_0_MV | CH1_AMP_0_MV | CH0_AMP_0_MV; 121 122 writel(reg, &dp_regs->amp_tuning_ctl); 123 124 /* 125 * PLL loop filter bandwidth 126 * For 2.7Gbps: 175KHz, For 1.62Gbps: 234KHz 127 * PLL digital power select: 1.1250V 128 */ 129 reg = DP_PLL_LOOP_BIT_DEFAULT | DP_PLL_REF_BIT_1_1250V; 130 writel(reg, &dp_regs->pll_ctl); 131 } 132 133 static void exynos_dp_init_interrupt(void) 134 { 135 /* Set interrupt registers to initial states */ 136 137 /* 138 * Disable interrupt 139 * INT pin assertion polarity. It must be configured 140 * correctly according to ICU setting. 141 * 1 = assert high, 0 = assert low 142 */ 143 writel(INT_POL, &dp_regs->int_ctl); 144 145 /* Clear pending registers */ 146 writel(0xff, &dp_regs->common_int_sta1); 147 writel(0xff, &dp_regs->common_int_sta2); 148 writel(0xff, &dp_regs->common_int_sta3); 149 writel(0xff, &dp_regs->common_int_sta4); 150 writel(0xff, &dp_regs->int_sta); 151 152 /* 0:mask,1: unmask */ 153 writel(0x00, &dp_regs->int_sta_mask1); 154 writel(0x00, &dp_regs->int_sta_mask2); 155 writel(0x00, &dp_regs->int_sta_mask3); 156 writel(0x00, &dp_regs->int_sta_mask4); 157 writel(0x00, &dp_regs->int_sta_mask); 158 } 159 160 void exynos_dp_reset(void) 161 { 162 unsigned int reg_func_1; 163 164 /* dp tx sw reset */ 165 writel(RESET_DP_TX, &dp_regs->tx_sw_reset); 166 167 exynos_dp_enable_video_input(DP_DISABLE); 168 exynos_dp_enable_video_bist(DP_DISABLE); 169 exynos_dp_enable_video_mute(DP_DISABLE); 170 171 /* software reset */ 172 reg_func_1 = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | 173 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | 174 HDCP_FUNC_EN_N | SW_FUNC_EN_N; 175 176 writel(reg_func_1, &dp_regs->func_en1); 177 writel(reg_func_1, &dp_regs->func_en2); 178 179 mdelay(1); 180 181 exynos_dp_init_analog_param(); 182 exynos_dp_init_interrupt(); 183 184 return; 185 } 186 187 void exynos_dp_enable_sw_func(unsigned int enable) 188 { 189 unsigned int reg; 190 191 reg = readl(&dp_regs->func_en1); 192 reg &= ~(SW_FUNC_EN_N); 193 194 if (!enable) 195 reg |= SW_FUNC_EN_N; 196 197 writel(reg, &dp_regs->func_en1); 198 199 return; 200 } 201 202 unsigned int exynos_dp_set_analog_power_down(unsigned int block, u32 enable) 203 { 204 unsigned int reg; 205 206 reg = readl(&dp_regs->phy_pd); 207 switch (block) { 208 case AUX_BLOCK: 209 reg &= ~(AUX_PD); 210 if (enable) 211 reg |= AUX_PD; 212 break; 213 case CH0_BLOCK: 214 reg &= ~(CH0_PD); 215 if (enable) 216 reg |= CH0_PD; 217 break; 218 case CH1_BLOCK: 219 reg &= ~(CH1_PD); 220 if (enable) 221 reg |= CH1_PD; 222 break; 223 case CH2_BLOCK: 224 reg &= ~(CH2_PD); 225 if (enable) 226 reg |= CH2_PD; 227 break; 228 case CH3_BLOCK: 229 reg &= ~(CH3_PD); 230 if (enable) 231 reg |= CH3_PD; 232 break; 233 case ANALOG_TOTAL: 234 reg &= ~PHY_PD; 235 if (enable) 236 reg |= PHY_PD; 237 break; 238 case POWER_ALL: 239 reg &= ~(PHY_PD | AUX_PD | CH0_PD | CH1_PD | CH2_PD | 240 CH3_PD); 241 if (enable) 242 reg |= (PHY_PD | AUX_PD | CH0_PD | CH1_PD | 243 CH2_PD | CH3_PD); 244 break; 245 default: 246 printf("DP undefined block number : %d\n", block); 247 return -1; 248 } 249 250 writel(reg, &dp_regs->phy_pd); 251 252 return 0; 253 } 254 255 unsigned int exynos_dp_get_pll_lock_status(void) 256 { 257 unsigned int reg; 258 259 reg = readl(&dp_regs->debug_ctl); 260 261 if (reg & PLL_LOCK) 262 return PLL_LOCKED; 263 else 264 return PLL_UNLOCKED; 265 } 266 267 static void exynos_dp_set_pll_power(unsigned int enable) 268 { 269 unsigned int reg; 270 271 reg = readl(&dp_regs->pll_ctl); 272 reg &= ~(DP_PLL_PD); 273 274 if (!enable) 275 reg |= DP_PLL_PD; 276 277 writel(reg, &dp_regs->pll_ctl); 278 } 279 280 int exynos_dp_init_analog_func(void) 281 { 282 int ret = EXYNOS_DP_SUCCESS; 283 unsigned int retry_cnt = 10; 284 unsigned int reg; 285 286 /* Power On All Analog block */ 287 exynos_dp_set_analog_power_down(POWER_ALL, DP_DISABLE); 288 289 reg = PLL_LOCK_CHG; 290 writel(reg, &dp_regs->common_int_sta1); 291 292 reg = readl(&dp_regs->debug_ctl); 293 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); 294 writel(reg, &dp_regs->debug_ctl); 295 296 /* Assert DP PLL Reset */ 297 reg = readl(&dp_regs->pll_ctl); 298 reg |= DP_PLL_RESET; 299 writel(reg, &dp_regs->pll_ctl); 300 301 mdelay(1); 302 303 /* Deassert DP PLL Reset */ 304 reg = readl(&dp_regs->pll_ctl); 305 reg &= ~(DP_PLL_RESET); 306 writel(reg, &dp_regs->pll_ctl); 307 308 exynos_dp_set_pll_power(DP_ENABLE); 309 310 while (exynos_dp_get_pll_lock_status() == PLL_UNLOCKED) { 311 mdelay(1); 312 retry_cnt--; 313 if (retry_cnt == 0) { 314 printf("DP dp's pll lock failed : retry : %d\n", 315 retry_cnt); 316 return -EINVAL; 317 } 318 } 319 320 debug("dp's pll lock success(%d)\n", retry_cnt); 321 322 /* Enable Serdes FIFO function and Link symbol clock domain module */ 323 reg = readl(&dp_regs->func_en2); 324 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N 325 | AUX_FUNC_EN_N); 326 writel(reg, &dp_regs->func_en2); 327 328 return ret; 329 } 330 331 void exynos_dp_init_hpd(void) 332 { 333 unsigned int reg; 334 335 /* Clear interrupts related to Hot Plug Detect */ 336 reg = HOTPLUG_CHG | HPD_LOST | PLUG; 337 writel(reg, &dp_regs->common_int_sta4); 338 339 reg = INT_HPD; 340 writel(reg, &dp_regs->int_sta); 341 342 reg = readl(&dp_regs->sys_ctl3); 343 reg &= ~(F_HPD | HPD_CTRL); 344 writel(reg, &dp_regs->sys_ctl3); 345 346 return; 347 } 348 349 static inline void exynos_dp_reset_aux(void) 350 { 351 unsigned int reg; 352 353 /* Disable AUX channel module */ 354 reg = readl(&dp_regs->func_en2); 355 reg |= AUX_FUNC_EN_N; 356 writel(reg, &dp_regs->func_en2); 357 358 return; 359 } 360 361 void exynos_dp_init_aux(void) 362 { 363 unsigned int reg; 364 365 /* Clear interrupts related to AUX channel */ 366 reg = RPLY_RECEIV | AUX_ERR; 367 writel(reg, &dp_regs->int_sta); 368 369 exynos_dp_reset_aux(); 370 371 /* Disable AUX transaction H/W retry */ 372 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(3)| 373 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 374 writel(reg, &dp_regs->aux_hw_retry_ctl); 375 376 /* Receive AUX Channel DEFER commands equal to DEFER_COUNT*64 */ 377 reg = DEFER_CTRL_EN | DEFER_COUNT(1); 378 writel(reg, &dp_regs->aux_ch_defer_ctl); 379 380 /* Enable AUX channel module */ 381 reg = readl(&dp_regs->func_en2); 382 reg &= ~AUX_FUNC_EN_N; 383 writel(reg, &dp_regs->func_en2); 384 385 return; 386 } 387 388 void exynos_dp_config_interrupt(void) 389 { 390 unsigned int reg; 391 392 /* 0: mask, 1: unmask */ 393 reg = COMMON_INT_MASK_1; 394 writel(reg, &dp_regs->common_int_mask1); 395 396 reg = COMMON_INT_MASK_2; 397 writel(reg, &dp_regs->common_int_mask2); 398 399 reg = COMMON_INT_MASK_3; 400 writel(reg, &dp_regs->common_int_mask3); 401 402 reg = COMMON_INT_MASK_4; 403 writel(reg, &dp_regs->common_int_mask4); 404 405 reg = INT_STA_MASK; 406 writel(reg, &dp_regs->int_sta_mask); 407 408 return; 409 } 410 411 unsigned int exynos_dp_get_plug_in_status(void) 412 { 413 unsigned int reg; 414 415 reg = readl(&dp_regs->sys_ctl3); 416 if (reg & HPD_STATUS) 417 return 0; 418 419 return -1; 420 } 421 422 unsigned int exynos_dp_detect_hpd(void) 423 { 424 int timeout_loop = DP_TIMEOUT_LOOP_COUNT; 425 426 mdelay(2); 427 428 while (exynos_dp_get_plug_in_status() != 0) { 429 if (timeout_loop == 0) 430 return -EINVAL; 431 mdelay(10); 432 timeout_loop--; 433 } 434 435 return EXYNOS_DP_SUCCESS; 436 } 437 438 unsigned int exynos_dp_start_aux_transaction(void) 439 { 440 unsigned int reg; 441 unsigned int ret = 0; 442 unsigned int retry_cnt; 443 444 /* Enable AUX CH operation */ 445 reg = readl(&dp_regs->aux_ch_ctl2); 446 reg |= AUX_EN; 447 writel(reg, &dp_regs->aux_ch_ctl2); 448 449 retry_cnt = 10; 450 while (retry_cnt) { 451 reg = readl(&dp_regs->int_sta); 452 if (!(reg & RPLY_RECEIV)) { 453 if (retry_cnt == 0) { 454 printf("DP Reply Timeout!!\n"); 455 ret = -EAGAIN; 456 return ret; 457 } 458 mdelay(1); 459 retry_cnt--; 460 } else 461 break; 462 } 463 464 /* Clear interrupt source for AUX CH command reply */ 465 writel(reg, &dp_regs->int_sta); 466 467 /* Clear interrupt source for AUX CH access error */ 468 reg = readl(&dp_regs->int_sta); 469 if (reg & AUX_ERR) { 470 printf("DP Aux Access Error\n"); 471 writel(AUX_ERR, &dp_regs->int_sta); 472 ret = -EAGAIN; 473 return ret; 474 } 475 476 /* Check AUX CH error access status */ 477 reg = readl(&dp_regs->aux_ch_sta); 478 if ((reg & AUX_STATUS_MASK) != 0) { 479 debug("DP AUX CH error happens: %x\n", reg & AUX_STATUS_MASK); 480 ret = -EAGAIN; 481 return ret; 482 } 483 484 return EXYNOS_DP_SUCCESS; 485 } 486 487 unsigned int exynos_dp_write_byte_to_dpcd(unsigned int reg_addr, 488 unsigned char data) 489 { 490 unsigned int reg, ret; 491 492 /* Clear AUX CH data buffer */ 493 reg = BUF_CLR; 494 writel(reg, &dp_regs->buffer_data_ctl); 495 496 /* Select DPCD device address */ 497 reg = AUX_ADDR_7_0(reg_addr); 498 writel(reg, &dp_regs->aux_addr_7_0); 499 reg = AUX_ADDR_15_8(reg_addr); 500 writel(reg, &dp_regs->aux_addr_15_8); 501 reg = AUX_ADDR_19_16(reg_addr); 502 writel(reg, &dp_regs->aux_addr_19_16); 503 504 /* Write data buffer */ 505 reg = (unsigned int)data; 506 writel(reg, &dp_regs->buf_data0); 507 508 /* 509 * Set DisplayPort transaction and write 1 byte 510 * If bit 3 is 1, DisplayPort transaction. 511 * If Bit 3 is 0, I2C transaction. 512 */ 513 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 514 writel(reg, &dp_regs->aux_ch_ctl1); 515 516 /* Start AUX transaction */ 517 ret = exynos_dp_start_aux_transaction(); 518 if (ret != EXYNOS_DP_SUCCESS) { 519 printf("DP Aux transaction failed\n"); 520 return ret; 521 } 522 523 return ret; 524 } 525 526 unsigned int exynos_dp_read_byte_from_dpcd(unsigned int reg_addr, 527 unsigned char *data) 528 { 529 unsigned int reg; 530 int retval; 531 532 /* Clear AUX CH data buffer */ 533 reg = BUF_CLR; 534 writel(reg, &dp_regs->buffer_data_ctl); 535 536 /* Select DPCD device address */ 537 reg = AUX_ADDR_7_0(reg_addr); 538 writel(reg, &dp_regs->aux_addr_7_0); 539 reg = AUX_ADDR_15_8(reg_addr); 540 writel(reg, &dp_regs->aux_addr_15_8); 541 reg = AUX_ADDR_19_16(reg_addr); 542 writel(reg, &dp_regs->aux_addr_19_16); 543 544 /* 545 * Set DisplayPort transaction and read 1 byte 546 * If bit 3 is 1, DisplayPort transaction. 547 * If Bit 3 is 0, I2C transaction. 548 */ 549 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 550 writel(reg, &dp_regs->aux_ch_ctl1); 551 552 /* Start AUX transaction */ 553 retval = exynos_dp_start_aux_transaction(); 554 if (!retval) 555 debug("DP Aux Transaction fail!\n"); 556 557 /* Read data buffer */ 558 reg = readl(&dp_regs->buf_data0); 559 *data = (unsigned char)(reg & 0xff); 560 561 return retval; 562 } 563 564 unsigned int exynos_dp_write_bytes_to_dpcd(unsigned int reg_addr, 565 unsigned int count, 566 unsigned char data[]) 567 { 568 unsigned int reg; 569 unsigned int start_offset; 570 unsigned int cur_data_count; 571 unsigned int cur_data_idx; 572 unsigned int retry_cnt; 573 unsigned int ret = 0; 574 575 /* Clear AUX CH data buffer */ 576 reg = BUF_CLR; 577 writel(reg, &dp_regs->buffer_data_ctl); 578 579 start_offset = 0; 580 while (start_offset < count) { 581 /* Buffer size of AUX CH is 16 * 4bytes */ 582 if ((count - start_offset) > 16) 583 cur_data_count = 16; 584 else 585 cur_data_count = count - start_offset; 586 587 retry_cnt = 5; 588 while (retry_cnt) { 589 /* Select DPCD device address */ 590 reg = AUX_ADDR_7_0(reg_addr + start_offset); 591 writel(reg, &dp_regs->aux_addr_7_0); 592 reg = AUX_ADDR_15_8(reg_addr + start_offset); 593 writel(reg, &dp_regs->aux_addr_15_8); 594 reg = AUX_ADDR_19_16(reg_addr + start_offset); 595 writel(reg, &dp_regs->aux_addr_19_16); 596 597 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 598 cur_data_idx++) { 599 reg = data[start_offset + cur_data_idx]; 600 writel(reg, (unsigned int)&dp_regs->buf_data0 + 601 (4 * cur_data_idx)); 602 } 603 /* 604 * Set DisplayPort transaction and write 605 * If bit 3 is 1, DisplayPort transaction. 606 * If Bit 3 is 0, I2C transaction. 607 */ 608 reg = AUX_LENGTH(cur_data_count) | 609 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 610 writel(reg, &dp_regs->aux_ch_ctl1); 611 612 /* Start AUX transaction */ 613 ret = exynos_dp_start_aux_transaction(); 614 if (ret != EXYNOS_DP_SUCCESS) { 615 if (retry_cnt == 0) { 616 printf("DP Aux Transaction failed\n"); 617 return ret; 618 } 619 retry_cnt--; 620 } else 621 break; 622 } 623 start_offset += cur_data_count; 624 } 625 626 return ret; 627 } 628 629 unsigned int exynos_dp_read_bytes_from_dpcd(unsigned int reg_addr, 630 unsigned int count, 631 unsigned char data[]) 632 { 633 unsigned int reg; 634 unsigned int start_offset; 635 unsigned int cur_data_count; 636 unsigned int cur_data_idx; 637 unsigned int retry_cnt; 638 unsigned int ret = 0; 639 640 /* Clear AUX CH data buffer */ 641 reg = BUF_CLR; 642 writel(reg, &dp_regs->buffer_data_ctl); 643 644 start_offset = 0; 645 while (start_offset < count) { 646 /* Buffer size of AUX CH is 16 * 4bytes */ 647 if ((count - start_offset) > 16) 648 cur_data_count = 16; 649 else 650 cur_data_count = count - start_offset; 651 652 retry_cnt = 5; 653 while (retry_cnt) { 654 /* Select DPCD device address */ 655 reg = AUX_ADDR_7_0(reg_addr + start_offset); 656 writel(reg, &dp_regs->aux_addr_7_0); 657 reg = AUX_ADDR_15_8(reg_addr + start_offset); 658 writel(reg, &dp_regs->aux_addr_15_8); 659 reg = AUX_ADDR_19_16(reg_addr + start_offset); 660 writel(reg, &dp_regs->aux_addr_19_16); 661 /* 662 * Set DisplayPort transaction and read 663 * If bit 3 is 1, DisplayPort transaction. 664 * If Bit 3 is 0, I2C transaction. 665 */ 666 reg = AUX_LENGTH(cur_data_count) | 667 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 668 writel(reg, &dp_regs->aux_ch_ctl1); 669 670 /* Start AUX transaction */ 671 ret = exynos_dp_start_aux_transaction(); 672 if (ret != EXYNOS_DP_SUCCESS) { 673 if (retry_cnt == 0) { 674 printf("DP Aux Transaction failed\n"); 675 return ret; 676 } 677 retry_cnt--; 678 } else 679 break; 680 } 681 682 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 683 cur_data_idx++) { 684 reg = readl((unsigned int)&dp_regs->buf_data0 + 685 4 * cur_data_idx); 686 data[start_offset + cur_data_idx] = (unsigned char)reg; 687 } 688 689 start_offset += cur_data_count; 690 } 691 692 return ret; 693 } 694 695 int exynos_dp_select_i2c_device(unsigned int device_addr, 696 unsigned int reg_addr) 697 { 698 unsigned int reg; 699 int retval; 700 701 /* Set EDID device address */ 702 reg = device_addr; 703 writel(reg, &dp_regs->aux_addr_7_0); 704 writel(0x0, &dp_regs->aux_addr_15_8); 705 writel(0x0, &dp_regs->aux_addr_19_16); 706 707 /* Set offset from base address of EDID device */ 708 writel(reg_addr, &dp_regs->buf_data0); 709 710 /* 711 * Set I2C transaction and write address 712 * If bit 3 is 1, DisplayPort transaction. 713 * If Bit 3 is 0, I2C transaction. 714 */ 715 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | 716 AUX_TX_COMM_WRITE; 717 writel(reg, &dp_regs->aux_ch_ctl1); 718 719 /* Start AUX transaction */ 720 retval = exynos_dp_start_aux_transaction(); 721 if (retval != 0) 722 printf("%s: DP Aux Transaction fail!\n", __func__); 723 724 return retval; 725 } 726 727 int exynos_dp_read_byte_from_i2c(unsigned int device_addr, 728 unsigned int reg_addr, 729 unsigned int *data) 730 { 731 unsigned int reg; 732 int i; 733 int retval; 734 735 for (i = 0; i < 10; i++) { 736 /* Clear AUX CH data buffer */ 737 reg = BUF_CLR; 738 writel(reg, &dp_regs->buffer_data_ctl); 739 740 /* Select EDID device */ 741 retval = exynos_dp_select_i2c_device(device_addr, reg_addr); 742 if (retval != 0) { 743 printf("DP Select EDID device fail. retry !\n"); 744 continue; 745 } 746 747 /* 748 * Set I2C transaction and read data 749 * If bit 3 is 1, DisplayPort transaction. 750 * If Bit 3 is 0, I2C transaction. 751 */ 752 reg = AUX_TX_COMM_I2C_TRANSACTION | 753 AUX_TX_COMM_READ; 754 writel(reg, &dp_regs->aux_ch_ctl1); 755 756 /* Start AUX transaction */ 757 retval = exynos_dp_start_aux_transaction(); 758 if (retval != EXYNOS_DP_SUCCESS) 759 printf("%s: DP Aux Transaction fail!\n", __func__); 760 } 761 762 /* Read data */ 763 if (retval == 0) 764 *data = readl(&dp_regs->buf_data0); 765 766 return retval; 767 } 768 769 int exynos_dp_read_bytes_from_i2c(unsigned int device_addr, 770 unsigned int reg_addr, unsigned int count, unsigned char edid[]) 771 { 772 unsigned int reg; 773 unsigned int i, j; 774 unsigned int cur_data_idx; 775 unsigned int defer = 0; 776 int retval = 0; 777 778 for (i = 0; i < count; i += 16) { /* use 16 burst */ 779 for (j = 0; j < 100; j++) { 780 /* Clear AUX CH data buffer */ 781 reg = BUF_CLR; 782 writel(reg, &dp_regs->buffer_data_ctl); 783 784 /* Set normal AUX CH command */ 785 reg = readl(&dp_regs->aux_ch_ctl2); 786 reg &= ~ADDR_ONLY; 787 writel(reg, &dp_regs->aux_ch_ctl2); 788 789 /* 790 * If Rx sends defer, Tx sends only reads 791 * request without sending addres 792 */ 793 if (!defer) 794 retval = 795 exynos_dp_select_i2c_device(device_addr, 796 reg_addr + i); 797 else 798 defer = 0; 799 800 if (retval == EXYNOS_DP_SUCCESS) { 801 /* 802 * Set I2C transaction and write data 803 * If bit 3 is 1, DisplayPort transaction. 804 * If Bit 3 is 0, I2C transaction. 805 */ 806 reg = AUX_LENGTH(16) | 807 AUX_TX_COMM_I2C_TRANSACTION | 808 AUX_TX_COMM_READ; 809 writel(reg, &dp_regs->aux_ch_ctl1); 810 811 /* Start AUX transaction */ 812 retval = exynos_dp_start_aux_transaction(); 813 if (retval == 0) 814 break; 815 else 816 printf("DP Aux Transaction fail!\n"); 817 } 818 /* Check if Rx sends defer */ 819 reg = readl(&dp_regs->aux_rx_comm); 820 if (reg == AUX_RX_COMM_AUX_DEFER || 821 reg == AUX_RX_COMM_I2C_DEFER) { 822 printf("DP Defer: %d\n", reg); 823 defer = 1; 824 } 825 } 826 827 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { 828 reg = readl((unsigned int)&dp_regs->buf_data0 829 + 4 * cur_data_idx); 830 edid[i + cur_data_idx] = (unsigned char)reg; 831 } 832 } 833 834 return retval; 835 } 836 837 void exynos_dp_reset_macro(void) 838 { 839 unsigned int reg; 840 841 reg = readl(&dp_regs->phy_test); 842 reg |= MACRO_RST; 843 writel(reg, &dp_regs->phy_test); 844 845 /* 10 us is the minimum Macro reset time. */ 846 mdelay(1); 847 848 reg &= ~MACRO_RST; 849 writel(reg, &dp_regs->phy_test); 850 } 851 852 void exynos_dp_set_link_bandwidth(unsigned char bwtype) 853 { 854 unsigned int reg; 855 856 reg = (unsigned int)bwtype; 857 858 /* Set bandwidth to 2.7G or 1.62G */ 859 if ((bwtype == DP_LANE_BW_1_62) || (bwtype == DP_LANE_BW_2_70)) 860 writel(reg, &dp_regs->link_bw_set); 861 } 862 863 unsigned char exynos_dp_get_link_bandwidth(void) 864 { 865 unsigned char ret; 866 unsigned int reg; 867 868 reg = readl(&dp_regs->link_bw_set); 869 ret = (unsigned char)reg; 870 871 return ret; 872 } 873 874 void exynos_dp_set_lane_count(unsigned char count) 875 { 876 unsigned int reg; 877 878 reg = (unsigned int)count; 879 880 if ((count == DP_LANE_CNT_1) || (count == DP_LANE_CNT_2) || 881 (count == DP_LANE_CNT_4)) 882 writel(reg, &dp_regs->lane_count_set); 883 } 884 885 unsigned int exynos_dp_get_lane_count(void) 886 { 887 unsigned int reg; 888 889 reg = readl(&dp_regs->lane_count_set); 890 891 return reg; 892 } 893 894 unsigned char exynos_dp_get_lanex_pre_emphasis(unsigned char lanecnt) 895 { 896 unsigned int reg_list[DP_LANE_CNT_4] = { 897 (unsigned int)&dp_regs->ln0_link_training_ctl, 898 (unsigned int)&dp_regs->ln1_link_training_ctl, 899 (unsigned int)&dp_regs->ln2_link_training_ctl, 900 (unsigned int)&dp_regs->ln3_link_training_ctl, 901 }; 902 903 return readl(reg_list[lanecnt]); 904 } 905 906 void exynos_dp_set_lanex_pre_emphasis(unsigned char request_val, 907 unsigned char lanecnt) 908 { 909 unsigned int reg_list[DP_LANE_CNT_4] = { 910 (unsigned int)&dp_regs->ln0_link_training_ctl, 911 (unsigned int)&dp_regs->ln1_link_training_ctl, 912 (unsigned int)&dp_regs->ln2_link_training_ctl, 913 (unsigned int)&dp_regs->ln3_link_training_ctl, 914 }; 915 916 writel(request_val, reg_list[lanecnt]); 917 } 918 919 void exynos_dp_set_lane_pre_emphasis(unsigned int level, unsigned char lanecnt) 920 { 921 unsigned char i; 922 unsigned int reg; 923 unsigned int reg_list[DP_LANE_CNT_4] = { 924 (unsigned int)&dp_regs->ln0_link_training_ctl, 925 (unsigned int)&dp_regs->ln1_link_training_ctl, 926 (unsigned int)&dp_regs->ln2_link_training_ctl, 927 (unsigned int)&dp_regs->ln3_link_training_ctl, 928 }; 929 unsigned int reg_shift[DP_LANE_CNT_4] = { 930 PRE_EMPHASIS_SET_0_SHIFT, 931 PRE_EMPHASIS_SET_1_SHIFT, 932 PRE_EMPHASIS_SET_2_SHIFT, 933 PRE_EMPHASIS_SET_3_SHIFT 934 }; 935 936 for (i = 0; i < lanecnt; i++) { 937 reg = level << reg_shift[i]; 938 writel(reg, reg_list[i]); 939 } 940 } 941 942 void exynos_dp_set_training_pattern(unsigned int pattern) 943 { 944 unsigned int reg = 0; 945 946 switch (pattern) { 947 case PRBS7: 948 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; 949 break; 950 case D10_2: 951 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; 952 break; 953 case TRAINING_PTN1: 954 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; 955 break; 956 case TRAINING_PTN2: 957 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; 958 break; 959 case DP_NONE: 960 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_DISABLE | 961 SW_TRAINING_PATTERN_SET_NORMAL; 962 break; 963 default: 964 break; 965 } 966 967 writel(reg, &dp_regs->training_ptn_set); 968 } 969 970 void exynos_dp_enable_enhanced_mode(unsigned char enable) 971 { 972 unsigned int reg; 973 974 reg = readl(&dp_regs->sys_ctl4); 975 reg &= ~ENHANCED; 976 977 if (enable) 978 reg |= ENHANCED; 979 980 writel(reg, &dp_regs->sys_ctl4); 981 } 982 983 void exynos_dp_enable_scrambling(unsigned int enable) 984 { 985 unsigned int reg; 986 987 reg = readl(&dp_regs->training_ptn_set); 988 reg &= ~(SCRAMBLING_DISABLE); 989 990 if (!enable) 991 reg |= SCRAMBLING_DISABLE; 992 993 writel(reg, &dp_regs->training_ptn_set); 994 } 995 996 int exynos_dp_init_video(void) 997 { 998 unsigned int reg; 999 1000 /* Clear VID_CLK_CHG[1] and VID_FORMAT_CHG[3] and VSYNC_DET[7] */ 1001 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; 1002 writel(reg, &dp_regs->common_int_sta1); 1003 1004 /* I_STRM__CLK detect : DE_CTL : Auto detect */ 1005 reg &= ~DET_CTRL; 1006 writel(reg, &dp_regs->sys_ctl1); 1007 1008 return 0; 1009 } 1010 1011 void exynos_dp_config_video_slave_mode(struct edp_video_info *video_info) 1012 { 1013 unsigned int reg; 1014 1015 /* Video Slave mode setting */ 1016 reg = readl(&dp_regs->func_en1); 1017 reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N); 1018 reg |= MASTER_VID_FUNC_EN_N; 1019 writel(reg, &dp_regs->func_en1); 1020 1021 /* Configure Interlaced for slave mode video */ 1022 reg = readl(&dp_regs->video_ctl10); 1023 reg &= ~INTERACE_SCAN_CFG; 1024 reg |= (video_info->interlaced << INTERACE_SCAN_CFG_SHIFT); 1025 writel(reg, &dp_regs->video_ctl10); 1026 1027 /* Configure V sync polarity for slave mode video */ 1028 reg = readl(&dp_regs->video_ctl10); 1029 reg &= ~VSYNC_POLARITY_CFG; 1030 reg |= (video_info->v_sync_polarity << V_S_POLARITY_CFG_SHIFT); 1031 writel(reg, &dp_regs->video_ctl10); 1032 1033 /* Configure H sync polarity for slave mode video */ 1034 reg = readl(&dp_regs->video_ctl10); 1035 reg &= ~HSYNC_POLARITY_CFG; 1036 reg |= (video_info->h_sync_polarity << H_S_POLARITY_CFG_SHIFT); 1037 writel(reg, &dp_regs->video_ctl10); 1038 1039 /* Set video mode to slave mode */ 1040 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; 1041 writel(reg, &dp_regs->soc_general_ctl); 1042 } 1043 1044 void exynos_dp_set_video_color_format(struct edp_video_info *video_info) 1045 { 1046 unsigned int reg; 1047 1048 /* Configure the input color depth, color space, dynamic range */ 1049 reg = (video_info->dynamic_range << IN_D_RANGE_SHIFT) | 1050 (video_info->color_depth << IN_BPC_SHIFT) | 1051 (video_info->color_space << IN_COLOR_F_SHIFT); 1052 writel(reg, &dp_regs->video_ctl2); 1053 1054 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ 1055 reg = readl(&dp_regs->video_ctl3); 1056 reg &= ~IN_YC_COEFFI_MASK; 1057 if (video_info->ycbcr_coeff) 1058 reg |= IN_YC_COEFFI_ITU709; 1059 else 1060 reg |= IN_YC_COEFFI_ITU601; 1061 writel(reg, &dp_regs->video_ctl3); 1062 } 1063 1064 int exynos_dp_config_video_bist(struct edp_device_info *edp_info) 1065 { 1066 unsigned int reg; 1067 unsigned int bist_type = 0; 1068 struct edp_video_info video_info = edp_info->video_info; 1069 1070 /* For master mode, you don't need to set the video format */ 1071 if (video_info.master_mode == 0) { 1072 writel(TOTAL_LINE_CFG_L(edp_info->disp_info.v_total), 1073 &dp_regs->total_ln_cfg_l); 1074 writel(TOTAL_LINE_CFG_H(edp_info->disp_info.v_total), 1075 &dp_regs->total_ln_cfg_h); 1076 writel(ACTIVE_LINE_CFG_L(edp_info->disp_info.v_res), 1077 &dp_regs->active_ln_cfg_l); 1078 writel(ACTIVE_LINE_CFG_H(edp_info->disp_info.v_res), 1079 &dp_regs->active_ln_cfg_h); 1080 writel(edp_info->disp_info.v_sync_width, 1081 &dp_regs->vsw_cfg); 1082 writel(edp_info->disp_info.v_back_porch, 1083 &dp_regs->vbp_cfg); 1084 writel(edp_info->disp_info.v_front_porch, 1085 &dp_regs->vfp_cfg); 1086 1087 writel(TOTAL_PIXEL_CFG_L(edp_info->disp_info.h_total), 1088 &dp_regs->total_pix_cfg_l); 1089 writel(TOTAL_PIXEL_CFG_H(edp_info->disp_info.h_total), 1090 &dp_regs->total_pix_cfg_h); 1091 writel(ACTIVE_PIXEL_CFG_L(edp_info->disp_info.h_res), 1092 &dp_regs->active_pix_cfg_l); 1093 writel(ACTIVE_PIXEL_CFG_H(edp_info->disp_info.h_res), 1094 &dp_regs->active_pix_cfg_h); 1095 writel(H_F_PORCH_CFG_L(edp_info->disp_info.h_front_porch), 1096 &dp_regs->hfp_cfg_l); 1097 writel(H_F_PORCH_CFG_H(edp_info->disp_info.h_front_porch), 1098 &dp_regs->hfp_cfg_h); 1099 writel(H_SYNC_PORCH_CFG_L(edp_info->disp_info.h_sync_width), 1100 &dp_regs->hsw_cfg_l); 1101 writel(H_SYNC_PORCH_CFG_H(edp_info->disp_info.h_sync_width), 1102 &dp_regs->hsw_cfg_h); 1103 writel(H_B_PORCH_CFG_L(edp_info->disp_info.h_back_porch), 1104 &dp_regs->hbp_cfg_l); 1105 writel(H_B_PORCH_CFG_H(edp_info->disp_info.h_back_porch), 1106 &dp_regs->hbp_cfg_h); 1107 1108 /* 1109 * Set SLAVE_I_SCAN_CFG[2], VSYNC_P_CFG[1], 1110 * HSYNC_P_CFG[0] properly 1111 */ 1112 reg = (video_info.interlaced << INTERACE_SCAN_CFG_SHIFT | 1113 video_info.v_sync_polarity << V_S_POLARITY_CFG_SHIFT | 1114 video_info.h_sync_polarity << H_S_POLARITY_CFG_SHIFT); 1115 writel(reg, &dp_regs->video_ctl10); 1116 } 1117 1118 /* BIST color bar width set--set to each bar is 32 pixel width */ 1119 switch (video_info.bist_pattern) { 1120 case COLORBAR_32: 1121 bist_type = BIST_WIDTH_BAR_32_PIXEL | 1122 BIST_TYPE_COLOR_BAR; 1123 break; 1124 case COLORBAR_64: 1125 bist_type = BIST_WIDTH_BAR_64_PIXEL | 1126 BIST_TYPE_COLOR_BAR; 1127 break; 1128 case WHITE_GRAY_BALCKBAR_32: 1129 bist_type = BIST_WIDTH_BAR_32_PIXEL | 1130 BIST_TYPE_WHITE_GRAY_BLACK_BAR; 1131 break; 1132 case WHITE_GRAY_BALCKBAR_64: 1133 bist_type = BIST_WIDTH_BAR_64_PIXEL | 1134 BIST_TYPE_WHITE_GRAY_BLACK_BAR; 1135 break; 1136 case MOBILE_WHITEBAR_32: 1137 bist_type = BIST_WIDTH_BAR_32_PIXEL | 1138 BIST_TYPE_MOBILE_WHITE_BAR; 1139 break; 1140 case MOBILE_WHITEBAR_64: 1141 bist_type = BIST_WIDTH_BAR_64_PIXEL | 1142 BIST_TYPE_MOBILE_WHITE_BAR; 1143 break; 1144 default: 1145 return -1; 1146 } 1147 1148 reg = bist_type; 1149 writel(reg, &dp_regs->video_ctl4); 1150 1151 return 0; 1152 } 1153 1154 unsigned int exynos_dp_is_slave_video_stream_clock_on(void) 1155 { 1156 unsigned int reg; 1157 1158 /* Update Video stream clk detect status */ 1159 reg = readl(&dp_regs->sys_ctl1); 1160 writel(reg, &dp_regs->sys_ctl1); 1161 1162 reg = readl(&dp_regs->sys_ctl1); 1163 1164 if (!(reg & DET_STA)) { 1165 debug("DP Input stream clock not detected.\n"); 1166 return -EIO; 1167 } 1168 1169 return EXYNOS_DP_SUCCESS; 1170 } 1171 1172 void exynos_dp_set_video_cr_mn(unsigned int type, unsigned int m_value, 1173 unsigned int n_value) 1174 { 1175 unsigned int reg; 1176 1177 if (type == REGISTER_M) { 1178 reg = readl(&dp_regs->sys_ctl4); 1179 reg |= FIX_M_VID; 1180 writel(reg, &dp_regs->sys_ctl4); 1181 reg = M_VID0_CFG(m_value); 1182 writel(reg, &dp_regs->m_vid0); 1183 reg = M_VID1_CFG(m_value); 1184 writel(reg, &dp_regs->m_vid1); 1185 reg = M_VID2_CFG(m_value); 1186 writel(reg, &dp_regs->m_vid2); 1187 1188 reg = N_VID0_CFG(n_value); 1189 writel(reg, &dp_regs->n_vid0); 1190 reg = N_VID1_CFG(n_value); 1191 writel(reg, &dp_regs->n_vid1); 1192 reg = N_VID2_CFG(n_value); 1193 writel(reg, &dp_regs->n_vid2); 1194 } else { 1195 reg = readl(&dp_regs->sys_ctl4); 1196 reg &= ~FIX_M_VID; 1197 writel(reg, &dp_regs->sys_ctl4); 1198 } 1199 } 1200 1201 void exynos_dp_set_video_timing_mode(unsigned int type) 1202 { 1203 unsigned int reg; 1204 1205 reg = readl(&dp_regs->video_ctl10); 1206 reg &= ~FORMAT_SEL; 1207 1208 if (type != VIDEO_TIMING_FROM_CAPTURE) 1209 reg |= FORMAT_SEL; 1210 1211 writel(reg, &dp_regs->video_ctl10); 1212 } 1213 1214 void exynos_dp_enable_video_master(unsigned int enable) 1215 { 1216 unsigned int reg; 1217 1218 reg = readl(&dp_regs->soc_general_ctl); 1219 if (enable) { 1220 reg &= ~VIDEO_MODE_MASK; 1221 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; 1222 } else { 1223 reg &= ~VIDEO_MODE_MASK; 1224 reg |= VIDEO_MODE_SLAVE_MODE; 1225 } 1226 1227 writel(reg, &dp_regs->soc_general_ctl); 1228 } 1229 1230 void exynos_dp_start_video(void) 1231 { 1232 unsigned int reg; 1233 1234 /* Enable Video input and disable Mute */ 1235 reg = readl(&dp_regs->video_ctl1); 1236 reg |= VIDEO_EN; 1237 writel(reg, &dp_regs->video_ctl1); 1238 } 1239 1240 unsigned int exynos_dp_is_video_stream_on(void) 1241 { 1242 unsigned int reg; 1243 1244 /* Update STRM_VALID */ 1245 reg = readl(&dp_regs->sys_ctl3); 1246 writel(reg, &dp_regs->sys_ctl3); 1247 1248 reg = readl(&dp_regs->sys_ctl3); 1249 if (!(reg & STRM_VALID)) 1250 return -EIO; 1251 1252 return EXYNOS_DP_SUCCESS; 1253 } 1254