1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_VOP_REG_H 8 #define _ROCKCHIP_VOP_REG_H 9 10 /* rk3288 register definition */ 11 #define RK3288_REG_CFG_DONE 0x0000 12 #define RK3288_VERSION_INFO 0x0004 13 #define RK3288_SYS_CTRL 0x0008 14 #define RK3288_SYS_CTRL1 0x000c 15 #define RK3288_DSP_CTRL0 0x0010 16 #define RK3288_DSP_CTRL1 0x0014 17 #define RK3288_DSP_BG 0x0018 18 #define RK3288_MCU_CTRL 0x001c 19 #define RK3288_INTR_CTRL0 0x0020 20 #define RK3288_INTR_CTRL1 0x0024 21 #define RK3288_WIN0_CTRL0 0x0030 22 #define RK3288_WIN0_CTRL1 0x0034 23 #define RK3288_WIN0_COLOR_KEY 0x0038 24 #define RK3288_WIN0_VIR 0x003c 25 #define RK3288_WIN0_YRGB_MST 0x0040 26 #define RK3288_WIN0_CBR_MST 0x0044 27 #define RK3288_WIN0_ACT_INFO 0x0048 28 #define RK3288_WIN0_DSP_INFO 0x004c 29 #define RK3288_WIN0_DSP_ST 0x0050 30 #define RK3288_WIN0_SCL_FACTOR_YRGB 0x0054 31 #define RK3288_WIN0_SCL_FACTOR_CBR 0x0058 32 #define RK3288_WIN0_SCL_OFFSET 0x005c 33 #define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060 34 #define RK3288_WIN0_DST_ALPHA_CTRL 0x0064 35 #define RK3288_WIN0_FADING_CTRL 0x0068 36 37 /* win1 register */ 38 #define RK3288_WIN1_CTRL0 0x0070 39 #define RK3288_WIN1_CTRL1 0x0074 40 #define RK3288_WIN1_COLOR_KEY 0x0078 41 #define RK3288_WIN1_VIR 0x007c 42 #define RK3288_WIN1_YRGB_MST 0x0080 43 #define RK3288_WIN1_CBR_MST 0x0084 44 #define RK3288_WIN1_ACT_INFO 0x0088 45 #define RK3288_WIN1_DSP_INFO 0x008c 46 #define RK3288_WIN1_DSP_ST 0x0090 47 #define RK3288_WIN1_SCL_FACTOR_YRGB 0x0094 48 #define RK3288_WIN1_SCL_FACTOR_CBR 0x0098 49 #define RK3288_WIN1_SCL_OFFSET 0x009c 50 #define RK3288_WIN1_SRC_ALPHA_CTRL 0x00a0 51 #define RK3288_WIN1_DST_ALPHA_CTRL 0x00a4 52 #define RK3288_WIN1_FADING_CTRL 0x00a8 53 /* win2 register */ 54 #define RK3288_WIN2_CTRL0 0x00b0 55 #define RK3288_WIN2_CTRL1 0x00b4 56 #define RK3288_WIN2_VIR0_1 0x00b8 57 #define RK3288_WIN2_VIR2_3 0x00bc 58 #define RK3288_WIN2_MST0 0x00c0 59 #define RK3288_WIN2_DSP_INFO0 0x00c4 60 #define RK3288_WIN2_DSP_ST0 0x00c8 61 #define RK3288_WIN2_COLOR_KEY 0x00cc 62 #define RK3288_WIN2_MST1 0x00d0 63 #define RK3288_WIN2_DSP_INFO1 0x00d4 64 #define RK3288_WIN2_DSP_ST1 0x00d8 65 #define RK3288_WIN2_SRC_ALPHA_CTRL 0x00dc 66 #define RK3288_WIN2_MST2 0x00e0 67 #define RK3288_WIN2_DSP_INFO2 0x00e4 68 #define RK3288_WIN2_DSP_ST2 0x00e8 69 #define RK3288_WIN2_DST_ALPHA_CTRL 0x00ec 70 #define RK3288_WIN2_MST3 0x00f0 71 #define RK3288_WIN2_DSP_INFO3 0x00f4 72 #define RK3288_WIN2_DSP_ST3 0x00f8 73 #define RK3288_WIN2_FADING_CTRL 0x00fc 74 /* win3 register */ 75 #define RK3288_WIN3_CTRL0 0x0100 76 #define RK3288_WIN3_CTRL1 0x0104 77 #define RK3288_WIN3_VIR0_1 0x0108 78 #define RK3288_WIN3_VIR2_3 0x010c 79 #define RK3288_WIN3_MST0 0x0110 80 #define RK3288_WIN3_DSP_INFO0 0x0114 81 #define RK3288_WIN3_DSP_ST0 0x0118 82 #define RK3288_WIN3_COLOR_KEY 0x011c 83 #define RK3288_WIN3_MST1 0x0120 84 #define RK3288_WIN3_DSP_INFO1 0x0124 85 #define RK3288_WIN3_DSP_ST1 0x0128 86 #define RK3288_WIN3_SRC_ALPHA_CTRL 0x012c 87 #define RK3288_WIN3_MST2 0x0130 88 #define RK3288_WIN3_DSP_INFO2 0x0134 89 #define RK3288_WIN3_DSP_ST2 0x0138 90 #define RK3288_WIN3_DST_ALPHA_CTRL 0x013c 91 #define RK3288_WIN3_MST3 0x0140 92 #define RK3288_WIN3_DSP_INFO3 0x0144 93 #define RK3288_WIN3_DSP_ST3 0x0148 94 #define RK3288_WIN3_FADING_CTRL 0x014c 95 /* hwc register */ 96 #define RK3288_HWC_CTRL0 0x0150 97 #define RK3288_HWC_CTRL1 0x0154 98 #define RK3288_HWC_MST 0x0158 99 #define RK3288_HWC_DSP_ST 0x015c 100 #define RK3288_HWC_SRC_ALPHA_CTRL 0x0160 101 #define RK3288_HWC_DST_ALPHA_CTRL 0x0164 102 #define RK3288_HWC_FADING_CTRL 0x0168 103 /* post process register */ 104 #define RK3288_POST_DSP_HACT_INFO 0x0170 105 #define RK3288_POST_DSP_VACT_INFO 0x0174 106 #define RK3288_POST_SCL_FACTOR_YRGB 0x0178 107 #define RK3288_POST_SCL_CTRL 0x0180 108 #define RK3288_POST_DSP_VACT_INFO_F1 0x0184 109 #define RK3288_DSP_HTOTAL_HS_END 0x0188 110 #define RK3288_DSP_HACT_ST_END 0x018c 111 #define RK3288_DSP_VTOTAL_VS_END 0x0190 112 #define RK3288_DSP_VACT_ST_END 0x0194 113 #define RK3288_DSP_VS_ST_END_F1 0x0198 114 #define RK3288_DSP_VACT_ST_END_F1 0x019c 115 116 #define RK3288_BCSH_COLOR_BAR 0x01b0 117 #define RK3288_BCSH_BCS 0x01b4 118 #define RK3288_BCSH_H 0x01b8 119 /* register definition end */ 120 121 /* rk3368 register definition */ 122 #define RK3368_REG_CFG_DONE 0x0000 123 #define RK3368_VERSION_INFO 0x0004 124 #define RK3368_SYS_CTRL 0x0008 125 #define RK3368_SYS_CTRL1 0x000c 126 #define RK3368_DSP_CTRL0 0x0010 127 #define RK3368_DSP_CTRL1 0x0014 128 #define RK3368_DSP_BG 0x0018 129 #define RK3368_MCU_CTRL 0x001c 130 #define RK3368_LINE_FLAG 0x0020 131 #define RK3368_INTR_EN 0x0024 132 #define RK3368_INTR_CLEAR 0x0028 133 #define RK3368_INTR_STATUS 0x002c 134 #define RK3368_WIN0_CTRL0 0x0030 135 #define RK3368_WIN0_CTRL1 0x0034 136 #define RK3368_WIN0_COLOR_KEY 0x0038 137 #define RK3368_WIN0_VIR 0x003c 138 #define RK3368_WIN0_YRGB_MST 0x0040 139 #define RK3368_WIN0_CBR_MST 0x0044 140 #define RK3368_WIN0_ACT_INFO 0x0048 141 #define RK3368_WIN0_DSP_INFO 0x004c 142 #define RK3368_WIN0_DSP_ST 0x0050 143 #define RK3368_WIN0_SCL_FACTOR_YRGB 0x0054 144 #define RK3368_WIN0_SCL_FACTOR_CBR 0x0058 145 #define RK3368_WIN0_SCL_OFFSET 0x005c 146 #define RK3368_WIN0_SRC_ALPHA_CTRL 0x0060 147 #define RK3368_WIN0_DST_ALPHA_CTRL 0x0064 148 #define RK3368_WIN0_FADING_CTRL 0x0068 149 #define RK3368_WIN0_CTRL2 0x006c 150 #define RK3368_WIN1_CTRL0 0x0070 151 #define RK3368_WIN1_CTRL1 0x0074 152 #define RK3368_WIN1_COLOR_KEY 0x0078 153 #define RK3368_WIN1_VIR 0x007c 154 #define RK3368_WIN1_YRGB_MST 0x0080 155 #define RK3368_WIN1_CBR_MST 0x0084 156 #define RK3368_WIN1_ACT_INFO 0x0088 157 #define RK3368_WIN1_DSP_INFO 0x008c 158 #define RK3368_WIN1_DSP_ST 0x0090 159 #define RK3368_WIN1_SCL_FACTOR_YRGB 0x0094 160 #define RK3368_WIN1_SCL_FACTOR_CBR 0x0098 161 #define RK3368_WIN1_SCL_OFFSET 0x009c 162 #define RK3368_WIN1_SRC_ALPHA_CTRL 0x00a0 163 #define RK3368_WIN1_DST_ALPHA_CTRL 0x00a4 164 #define RK3368_WIN1_FADING_CTRL 0x00a8 165 #define RK3368_WIN1_CTRL2 0x00ac 166 #define RK3368_WIN2_CTRL0 0x00b0 167 #define RK3368_WIN2_CTRL1 0x00b4 168 #define RK3368_WIN2_VIR0_1 0x00b8 169 #define RK3368_WIN2_VIR2_3 0x00bc 170 #define RK3368_WIN2_MST0 0x00c0 171 #define RK3368_WIN2_DSP_INFO0 0x00c4 172 #define RK3368_WIN2_DSP_ST0 0x00c8 173 #define RK3368_WIN2_COLOR_KEY 0x00cc 174 #define RK3368_WIN2_MST1 0x00d0 175 #define RK3368_WIN2_DSP_INFO1 0x00d4 176 #define RK3368_WIN2_DSP_ST1 0x00d8 177 #define RK3368_WIN2_SRC_ALPHA_CTRL 0x00dc 178 #define RK3368_WIN2_MST2 0x00e0 179 #define RK3368_WIN2_DSP_INFO2 0x00e4 180 #define RK3368_WIN2_DSP_ST2 0x00e8 181 #define RK3368_WIN2_DST_ALPHA_CTRL 0x00ec 182 #define RK3368_WIN2_MST3 0x00f0 183 #define RK3368_WIN2_DSP_INFO3 0x00f4 184 #define RK3368_WIN2_DSP_ST3 0x00f8 185 #define RK3368_WIN2_FADING_CTRL 0x00fc 186 #define RK3368_WIN3_CTRL0 0x0100 187 #define RK3368_WIN3_CTRL1 0x0104 188 #define RK3368_WIN3_VIR0_1 0x0108 189 #define RK3368_WIN3_VIR2_3 0x010c 190 #define RK3368_WIN3_MST0 0x0110 191 #define RK3368_WIN3_DSP_INFO0 0x0114 192 #define RK3368_WIN3_DSP_ST0 0x0118 193 #define RK3368_WIN3_COLOR_KEY 0x011c 194 #define RK3368_WIN3_MST1 0x0120 195 #define RK3368_WIN3_DSP_INFO1 0x0124 196 #define RK3368_WIN3_DSP_ST1 0x0128 197 #define RK3368_WIN3_SRC_ALPHA_CTRL 0x012c 198 #define RK3368_WIN3_MST2 0x0130 199 #define RK3368_WIN3_DSP_INFO2 0x0134 200 #define RK3368_WIN3_DSP_ST2 0x0138 201 #define RK3368_WIN3_DST_ALPHA_CTRL 0x013c 202 #define RK3368_WIN3_MST3 0x0140 203 #define RK3368_WIN3_DSP_INFO3 0x0144 204 #define RK3368_WIN3_DSP_ST3 0x0148 205 #define RK3368_WIN3_FADING_CTRL 0x014c 206 #define RK3368_HWC_CTRL0 0x0150 207 #define RK3368_HWC_CTRL1 0x0154 208 #define RK3368_HWC_MST 0x0158 209 #define RK3368_HWC_DSP_ST 0x015c 210 #define RK3368_HWC_SRC_ALPHA_CTRL 0x0160 211 #define RK3368_HWC_DST_ALPHA_CTRL 0x0164 212 #define RK3368_HWC_FADING_CTRL 0x0168 213 #define RK3368_HWC_RESERVED1 0x016c 214 #define RK3368_POST_DSP_HACT_INFO 0x0170 215 #define RK3368_POST_DSP_VACT_INFO 0x0174 216 #define RK3368_POST_SCL_FACTOR_YRGB 0x0178 217 #define RK3368_POST_RESERVED 0x017c 218 #define RK3368_POST_SCL_CTRL 0x0180 219 #define RK3368_POST_DSP_VACT_INFO_F1 0x0184 220 #define RK3368_DSP_HTOTAL_HS_END 0x0188 221 #define RK3368_DSP_HACT_ST_END 0x018c 222 #define RK3368_DSP_VTOTAL_VS_END 0x0190 223 #define RK3368_DSP_VACT_ST_END 0x0194 224 #define RK3368_DSP_VS_ST_END_F1 0x0198 225 #define RK3368_DSP_VACT_ST_END_F1 0x019c 226 #define RK3368_PWM_CTRL 0x01a0 227 #define RK3368_PWM_PERIOD_HPR 0x01a4 228 #define RK3368_PWM_DUTY_LPR 0x01a8 229 #define RK3368_PWM_CNT 0x01ac 230 #define RK3368_BCSH_COLOR_BAR 0x01b0 231 #define RK3368_BCSH_BCS 0x01b4 232 #define RK3368_BCSH_H 0x01b8 233 #define RK3368_BCSH_CTRL 0x01bc 234 #define RK3368_CABC_CTRL0 0x01c0 235 #define RK3368_CABC_CTRL1 0x01c4 236 #define RK3368_CABC_CTRL2 0x01c8 237 #define RK3368_CABC_CTRL3 0x01cc 238 #define RK3368_CABC_GAUSS_LINE0_0 0x01d0 239 #define RK3368_CABC_GAUSS_LINE0_1 0x01d4 240 #define RK3368_CABC_GAUSS_LINE1_0 0x01d8 241 #define RK3368_CABC_GAUSS_LINE1_1 0x01dc 242 #define RK3368_CABC_GAUSS_LINE2_0 0x01e0 243 #define RK3368_CABC_GAUSS_LINE2_1 0x01e4 244 #define RK3368_FRC_LOWER01_0 0x01e8 245 #define RK3368_FRC_LOWER01_1 0x01ec 246 #define RK3368_FRC_LOWER10_0 0x01f0 247 #define RK3368_FRC_LOWER10_1 0x01f4 248 #define RK3368_FRC_LOWER11_0 0x01f8 249 #define RK3368_FRC_LOWER11_1 0x01fc 250 #define RK3368_IFBDC_CTRL 0x0200 251 #define RK3368_IFBDC_TILES_NUM 0x0204 252 #define RK3368_IFBDC_FRAME_RST_CYCLE 0x0208 253 #define RK3368_IFBDC_BASE_ADDR 0x020c 254 #define RK3368_IFBDC_MB_SIZE 0x0210 255 #define RK3368_IFBDC_CMP_INDEX_INIT 0x0214 256 #define RK3368_IFBDC_VIR 0x0220 257 #define RK3368_IFBDC_DEBUG0 0x0230 258 #define RK3368_IFBDC_DEBUG1 0x0234 259 #define RK3368_LATENCY_CTRL0 0x0250 260 #define RK3368_RD_MAX_LATENCY_NUM0 0x0254 261 #define RK3368_RD_LATENCY_THR_NUM0 0x0258 262 #define RK3368_RD_LATENCY_SAMP_NUM0 0x025c 263 #define RK3368_WIN0_DSP_BG 0x0260 264 #define RK3368_WIN1_DSP_BG 0x0264 265 #define RK3368_WIN2_DSP_BG 0x0268 266 #define RK3368_WIN3_DSP_BG 0x026c 267 #define RK3368_SCAN_LINE_NUM 0x0270 268 #define RK3368_CABC_DEBUG0 0x0274 269 #define RK3368_CABC_DEBUG1 0x0278 270 #define RK3368_CABC_DEBUG2 0x027c 271 #define RK3368_DBG_REG_000 0x0280 272 #define RK3368_DBG_REG_001 0x0284 273 #define RK3368_DBG_REG_002 0x0288 274 #define RK3368_DBG_REG_003 0x028c 275 #define RK3368_DBG_REG_004 0x0290 276 #define RK3368_DBG_REG_005 0x0294 277 #define RK3368_DBG_REG_006 0x0298 278 #define RK3368_DBG_REG_007 0x029c 279 #define RK3368_DBG_REG_008 0x02a0 280 #define RK3368_DBG_REG_016 0x02c0 281 #define RK3368_DBG_REG_017 0x02c4 282 #define RK3368_DBG_REG_018 0x02c8 283 #define RK3368_DBG_REG_019 0x02cc 284 #define RK3368_DBG_REG_020 0x02d0 285 #define RK3368_DBG_REG_021 0x02d4 286 #define RK3368_DBG_REG_022 0x02d8 287 #define RK3368_DBG_REG_023 0x02dc 288 #define RK3368_DBG_REG_028 0x02f0 289 #define RK3368_MMU_DTE_ADDR 0x0300 290 #define RK3368_MMU_STATUS 0x0304 291 #define RK3368_MMU_COMMAND 0x0308 292 #define RK3368_MMU_PAGE_FAULT_ADDR 0x030c 293 #define RK3368_MMU_ZAP_ONE_LINE 0x0310 294 #define RK3368_MMU_INT_RAWSTAT 0x0314 295 #define RK3368_MMU_INT_CLEAR 0x0318 296 #define RK3368_MMU_INT_MASK 0x031c 297 #define RK3368_MMU_INT_STATUS 0x0320 298 #define RK3368_MMU_AUTO_GATING 0x0324 299 #define RK3368_WIN2_LUT_ADDR 0x0400 300 #define RK3368_WIN3_LUT_ADDR 0x0800 301 #define RK3368_HWC_LUT_ADDR 0x0c00 302 #define RK3368_GAMMA_LUT_ADDR 0x1000 303 #define RK3368_CABC_GAMMA_LUT_ADDR 0x1800 304 #define RK3368_MCU_BYPASS_WPORT 0x2200 305 #define RK3368_MCU_BYPASS_RPORT 0x2300 306 /* rk3368 register definition end */ 307 308 #define RK3366_REG_CFG_DONE 0x0000 309 #define RK3366_VERSION_INFO 0x0004 310 #define RK3366_SYS_CTRL 0x0008 311 #define RK3366_SYS_CTRL1 0x000c 312 #define RK3366_DSP_CTRL0 0x0010 313 #define RK3366_DSP_CTRL1 0x0014 314 #define RK3366_DSP_BG 0x0018 315 #define RK3366_MCU_CTRL 0x001c 316 #define RK3366_WB_CTRL0 0x0020 317 #define RK3366_WB_CTRL1 0x0024 318 #define RK3366_WB_YRGB_MST 0x0028 319 #define RK3366_WB_CBR_MST 0x002c 320 #define RK3366_WIN0_CTRL0 0x0030 321 #define RK3366_WIN0_CTRL1 0x0034 322 #define RK3366_WIN0_COLOR_KEY 0x0038 323 #define RK3366_WIN0_VIR 0x003c 324 #define RK3366_WIN0_YRGB_MST 0x0040 325 #define RK3366_WIN0_CBR_MST 0x0044 326 #define RK3366_WIN0_ACT_INFO 0x0048 327 #define RK3366_WIN0_DSP_INFO 0x004c 328 #define RK3366_WIN0_DSP_ST 0x0050 329 #define RK3366_WIN0_SCL_FACTOR_YRGB 0x0054 330 #define RK3366_WIN0_SCL_FACTOR_CBR 0x0058 331 #define RK3366_WIN0_SCL_OFFSET 0x005c 332 #define RK3366_WIN0_SRC_ALPHA_CTRL 0x0060 333 #define RK3366_WIN0_DST_ALPHA_CTRL 0x0064 334 #define RK3366_WIN0_FADING_CTRL 0x0068 335 #define RK3366_WIN0_CTRL2 0x006c 336 #define RK3366_WIN1_CTRL0 0x0070 337 #define RK3366_WIN1_CTRL1 0x0074 338 #define RK3366_WIN1_COLOR_KEY 0x0078 339 #define RK3366_WIN1_VIR 0x007c 340 #define RK3366_WIN1_YRGB_MST 0x0080 341 #define RK3366_WIN1_CBR_MST 0x0084 342 #define RK3366_WIN1_ACT_INFO 0x0088 343 #define RK3366_WIN1_DSP_INFO 0x008c 344 #define RK3366_WIN1_DSP_ST 0x0090 345 #define RK3366_WIN1_SCL_FACTOR_YRGB 0x0094 346 #define RK3366_WIN1_SCL_FACTOR_CBR 0x0098 347 #define RK3366_WIN1_SCL_OFFSET 0x009c 348 #define RK3366_WIN1_SRC_ALPHA_CTRL 0x00a0 349 #define RK3366_WIN1_DST_ALPHA_CTRL 0x00a4 350 #define RK3366_WIN1_FADING_CTRL 0x00a8 351 #define RK3366_WIN1_CTRL2 0x00ac 352 #define RK3366_WIN2_CTRL0 0x00b0 353 #define RK3366_WIN2_CTRL1 0x00b4 354 #define RK3366_WIN2_VIR0_1 0x00b8 355 #define RK3366_WIN2_VIR2_3 0x00bc 356 #define RK3366_WIN2_MST0 0x00c0 357 #define RK3366_WIN2_DSP_INFO0 0x00c4 358 #define RK3366_WIN2_DSP_ST0 0x00c8 359 #define RK3366_WIN2_COLOR_KEY 0x00cc 360 #define RK3366_WIN2_MST1 0x00d0 361 #define RK3366_WIN2_DSP_INFO1 0x00d4 362 #define RK3366_WIN2_DSP_ST1 0x00d8 363 #define RK3366_WIN2_SRC_ALPHA_CTRL 0x00dc 364 #define RK3366_WIN2_MST2 0x00e0 365 #define RK3366_WIN2_DSP_INFO2 0x00e4 366 #define RK3366_WIN2_DSP_ST2 0x00e8 367 #define RK3366_WIN2_DST_ALPHA_CTRL 0x00ec 368 #define RK3366_WIN2_MST3 0x00f0 369 #define RK3366_WIN2_DSP_INFO3 0x00f4 370 #define RK3366_WIN2_DSP_ST3 0x00f8 371 #define RK3366_WIN2_FADING_CTRL 0x00fc 372 #define RK3366_WIN3_CTRL0 0x0100 373 #define RK3366_WIN3_CTRL1 0x0104 374 #define RK3366_WIN3_VIR0_1 0x0108 375 #define RK3366_WIN3_VIR2_3 0x010c 376 #define RK3366_WIN3_MST0 0x0110 377 #define RK3366_WIN3_DSP_INFO0 0x0114 378 #define RK3366_WIN3_DSP_ST0 0x0118 379 #define RK3366_WIN3_COLOR_KEY 0x011c 380 #define RK3366_WIN3_MST1 0x0120 381 #define RK3366_WIN3_DSP_INFO1 0x0124 382 #define RK3366_WIN3_DSP_ST1 0x0128 383 #define RK3366_WIN3_SRC_ALPHA_CTRL 0x012c 384 #define RK3366_WIN3_MST2 0x0130 385 #define RK3366_WIN3_DSP_INFO2 0x0134 386 #define RK3366_WIN3_DSP_ST2 0x0138 387 #define RK3366_WIN3_DST_ALPHA_CTRL 0x013c 388 #define RK3366_WIN3_MST3 0x0140 389 #define RK3366_WIN3_DSP_INFO3 0x0144 390 #define RK3366_WIN3_DSP_ST3 0x0148 391 #define RK3366_WIN3_FADING_CTRL 0x014c 392 #define RK3366_HWC_CTRL0 0x0150 393 #define RK3366_HWC_CTRL1 0x0154 394 #define RK3366_HWC_MST 0x0158 395 #define RK3366_HWC_DSP_ST 0x015c 396 #define RK3366_HWC_SRC_ALPHA_CTRL 0x0160 397 #define RK3366_HWC_DST_ALPHA_CTRL 0x0164 398 #define RK3366_HWC_FADING_CTRL 0x0168 399 #define RK3366_HWC_RESERVED1 0x016c 400 #define RK3366_POST_DSP_HACT_INFO 0x0170 401 #define RK3366_POST_DSP_VACT_INFO 0x0174 402 #define RK3366_POST_SCL_FACTOR_YRGB 0x0178 403 #define RK3366_POST_RESERVED 0x017c 404 #define RK3366_POST_SCL_CTRL 0x0180 405 #define RK3366_POST_DSP_VACT_INFO_F1 0x0184 406 #define RK3366_DSP_HTOTAL_HS_END 0x0188 407 #define RK3366_DSP_HACT_ST_END 0x018c 408 #define RK3366_DSP_VTOTAL_VS_END 0x0190 409 #define RK3366_DSP_VACT_ST_END 0x0194 410 #define RK3366_DSP_VS_ST_END_F1 0x0198 411 #define RK3366_DSP_VACT_ST_END_F1 0x019c 412 #define RK3366_PWM_CTRL 0x01a0 413 #define RK3366_PWM_PERIOD_HPR 0x01a4 414 #define RK3366_PWM_DUTY_LPR 0x01a8 415 #define RK3366_PWM_CNT 0x01ac 416 #define RK3366_BCSH_COLOR_BAR 0x01b0 417 #define RK3366_BCSH_BCS 0x01b4 418 #define RK3366_BCSH_H 0x01b8 419 #define RK3366_BCSH_CTRL 0x01bc 420 #define RK3366_CABC_CTRL0 0x01c0 421 #define RK3366_CABC_CTRL1 0x01c4 422 #define RK3366_CABC_CTRL2 0x01c8 423 #define RK3366_CABC_CTRL3 0x01cc 424 #define RK3366_CABC_GAUSS_LINE0_0 0x01d0 425 #define RK3366_CABC_GAUSS_LINE0_1 0x01d4 426 #define RK3366_CABC_GAUSS_LINE1_0 0x01d8 427 #define RK3366_CABC_GAUSS_LINE1_1 0x01dc 428 #define RK3366_CABC_GAUSS_LINE2_0 0x01e0 429 #define RK3366_CABC_GAUSS_LINE2_1 0x01e4 430 #define RK3366_FRC_LOWER01_0 0x01e8 431 #define RK3366_FRC_LOWER01_1 0x01ec 432 #define RK3366_FRC_LOWER10_0 0x01f0 433 #define RK3366_FRC_LOWER10_1 0x01f4 434 #define RK3366_FRC_LOWER11_0 0x01f8 435 #define RK3366_FRC_LOWER11_1 0x01fc 436 #define RK3366_INTR_EN0 0x0280 437 #define RK3366_INTR_CLEAR0 0x0284 438 #define RK3366_INTR_STATUS0 0x0288 439 #define RK3366_INTR_RAW_STATUS0 0x028c 440 #define RK3366_INTR_EN1 0x0290 441 #define RK3366_INTR_CLEAR1 0x0294 442 #define RK3366_INTR_STATUS1 0x0298 443 #define RK3366_INTR_RAW_STATUS1 0x029c 444 #define RK3366_LINE_FLAG 0x02a0 445 #define RK3366_VOP_STATUS 0x02a4 446 #define RK3366_BLANKING_VALUE 0x02a8 447 #define RK3366_WIN0_DSP_BG 0x02b0 448 #define RK3366_WIN1_DSP_BG 0x02b4 449 #define RK3366_WIN2_DSP_BG 0x02b8 450 #define RK3366_WIN3_DSP_BG 0x02bc 451 #define RK3366_WIN2_LUT_ADDR 0x0400 452 #define RK3366_WIN3_LUT_ADDR 0x0800 453 #define RK3366_HWC_LUT_ADDR 0x0c00 454 #define RK3366_GAMMA0_LUT_ADDR 0x1000 455 #define RK3366_GAMMA1_LUT_ADDR 0x1400 456 #define RK3366_CABC_GAMMA_LUT_ADDR 0x1800 457 #define RK3366_MCU_BYPASS_WPORT 0x2200 458 #define RK3366_MCU_BYPASS_RPORT 0x2300 459 #define RK3366_MMU_DTE_ADDR 0x2400 460 #define RK3366_MMU_STATUS 0x2404 461 #define RK3366_MMU_COMMAND 0x2408 462 #define RK3366_MMU_PAGE_FAULT_ADDR 0x240c 463 #define RK3366_MMU_ZAP_ONE_LINE 0x2410 464 #define RK3366_MMU_INT_RAWSTAT 0x2414 465 #define RK3366_MMU_INT_CLEAR 0x2418 466 #define RK3366_MMU_INT_MASK 0x241c 467 #define RK3366_MMU_INT_STATUS 0x2420 468 #define RK3366_MMU_AUTO_GATING 0x2424 469 470 /* rk3399 register definition */ 471 #define RK3399_REG_CFG_DONE 0x0000 472 #define RK3399_VERSION_INFO 0x0004 473 #define RK3399_SYS_CTRL 0x0008 474 #define RK3399_SYS_CTRL1 0x000c 475 #define RK3399_DSP_CTRL0 0x0010 476 #define RK3399_DSP_CTRL1 0x0014 477 #define RK3399_DSP_BG 0x0018 478 #define RK3399_MCU_CTRL 0x001c 479 #define RK3399_WB_CTRL0 0x0020 480 #define RK3399_WB_CTRL1 0x0024 481 #define RK3399_WB_YRGB_MST 0x0028 482 #define RK3399_WB_CBR_MST 0x002c 483 #define RK3399_WIN0_CTRL0 0x0030 484 #define RK3399_WIN0_CTRL1 0x0034 485 #define RK3399_WIN0_COLOR_KEY 0x0038 486 #define RK3399_WIN0_VIR 0x003c 487 #define RK3399_WIN0_YRGB_MST 0x0040 488 #define RK3399_WIN0_CBR_MST 0x0044 489 #define RK3399_WIN0_ACT_INFO 0x0048 490 #define RK3399_WIN0_DSP_INFO 0x004c 491 #define RK3399_WIN0_DSP_ST 0x0050 492 #define RK3399_WIN0_SCL_FACTOR_YRGB 0x0054 493 #define RK3399_WIN0_SCL_FACTOR_CBR 0x0058 494 #define RK3399_WIN0_SCL_OFFSET 0x005c 495 #define RK3399_WIN0_SRC_ALPHA_CTRL 0x0060 496 #define RK3399_WIN0_DST_ALPHA_CTRL 0x0064 497 #define RK3399_WIN0_FADING_CTRL 0x0068 498 #define RK3399_WIN0_CTRL2 0x006c 499 #define RK3399_WIN1_CTRL0 0x0070 500 #define RK3399_WIN1_CTRL1 0x0074 501 #define RK3399_WIN1_COLOR_KEY 0x0078 502 #define RK3399_WIN1_VIR 0x007c 503 #define RK3399_WIN1_YRGB_MST 0x0080 504 #define RK3399_WIN1_CBR_MST 0x0084 505 #define RK3399_WIN1_ACT_INFO 0x0088 506 #define RK3399_WIN1_DSP_INFO 0x008c 507 #define RK3399_WIN1_DSP_ST 0x0090 508 #define RK3399_WIN1_SCL_FACTOR_YRGB 0x0094 509 #define RK3399_WIN1_SCL_FACTOR_CBR 0x0098 510 #define RK3399_WIN1_SCL_OFFSET 0x009c 511 #define RK3399_WIN1_SRC_ALPHA_CTRL 0x00a0 512 #define RK3399_WIN1_DST_ALPHA_CTRL 0x00a4 513 #define RK3399_WIN1_FADING_CTRL 0x00a8 514 #define RK3399_WIN1_CTRL2 0x00ac 515 #define RK3399_WIN2_CTRL0 0x00b0 516 #define RK3399_WIN2_CTRL1 0x00b4 517 #define RK3399_WIN2_VIR0_1 0x00b8 518 #define RK3399_WIN2_VIR2_3 0x00bc 519 #define RK3399_WIN2_MST0 0x00c0 520 #define RK3399_WIN2_DSP_INFO0 0x00c4 521 #define RK3399_WIN2_DSP_ST0 0x00c8 522 #define RK3399_WIN2_COLOR_KEY 0x00cc 523 #define RK3399_WIN2_MST1 0x00d0 524 #define RK3399_WIN2_DSP_INFO1 0x00d4 525 #define RK3399_WIN2_DSP_ST1 0x00d8 526 #define RK3399_WIN2_SRC_ALPHA_CTRL 0x00dc 527 #define RK3399_WIN2_MST2 0x00e0 528 #define RK3399_WIN2_DSP_INFO2 0x00e4 529 #define RK3399_WIN2_DSP_ST2 0x00e8 530 #define RK3399_WIN2_DST_ALPHA_CTRL 0x00ec 531 #define RK3399_WIN2_MST3 0x00f0 532 #define RK3399_WIN2_DSP_INFO3 0x00f4 533 #define RK3399_WIN2_DSP_ST3 0x00f8 534 #define RK3399_WIN2_FADING_CTRL 0x00fc 535 #define RK3399_WIN3_CTRL0 0x0100 536 #define RK3399_WIN3_CTRL1 0x0104 537 #define RK3399_WIN3_VIR0_1 0x0108 538 #define RK3399_WIN3_VIR2_3 0x010c 539 #define RK3399_WIN3_MST0 0x0110 540 #define RK3399_WIN3_DSP_INFO0 0x0114 541 #define RK3399_WIN3_DSP_ST0 0x0118 542 #define RK3399_WIN3_COLOR_KEY 0x011c 543 #define RK3399_WIN3_MST1 0x0120 544 #define RK3399_WIN3_DSP_INFO1 0x0124 545 #define RK3399_WIN3_DSP_ST1 0x0128 546 #define RK3399_WIN3_SRC_ALPHA_CTRL 0x012c 547 #define RK3399_WIN3_MST2 0x0130 548 #define RK3399_WIN3_DSP_INFO2 0x0134 549 #define RK3399_WIN3_DSP_ST2 0x0138 550 #define RK3399_WIN3_DST_ALPHA_CTRL 0x013c 551 #define RK3399_WIN3_MST3 0x0140 552 #define RK3399_WIN3_DSP_INFO3 0x0144 553 #define RK3399_WIN3_DSP_ST3 0x0148 554 #define RK3399_WIN3_FADING_CTRL 0x014c 555 #define RK3399_HWC_CTRL0 0x0150 556 #define RK3399_HWC_CTRL1 0x0154 557 #define RK3399_HWC_MST 0x0158 558 #define RK3399_HWC_DSP_ST 0x015c 559 #define RK3399_HWC_SRC_ALPHA_CTRL 0x0160 560 #define RK3399_HWC_DST_ALPHA_CTRL 0x0164 561 #define RK3399_HWC_FADING_CTRL 0x0168 562 #define RK3399_HWC_RESERVED1 0x016c 563 #define RK3399_POST_DSP_HACT_INFO 0x0170 564 #define RK3399_POST_DSP_VACT_INFO 0x0174 565 #define RK3399_POST_SCL_FACTOR_YRGB 0x0178 566 #define RK3399_POST_RESERVED 0x017c 567 #define RK3399_POST_SCL_CTRL 0x0180 568 #define RK3399_POST_DSP_VACT_INFO_F1 0x0184 569 #define RK3399_DSP_HTOTAL_HS_END 0x0188 570 #define RK3399_DSP_HACT_ST_END 0x018c 571 #define RK3399_DSP_VTOTAL_VS_END 0x0190 572 #define RK3399_DSP_VACT_ST_END 0x0194 573 #define RK3399_DSP_VS_ST_END_F1 0x0198 574 #define RK3399_DSP_VACT_ST_END_F1 0x019c 575 #define RK3399_PWM_CTRL 0x01a0 576 #define RK3399_PWM_PERIOD_HPR 0x01a4 577 #define RK3399_PWM_DUTY_LPR 0x01a8 578 #define RK3399_PWM_CNT 0x01ac 579 #define RK3399_BCSH_COLOR_BAR 0x01b0 580 #define RK3399_BCSH_BCS 0x01b4 581 #define RK3399_BCSH_H 0x01b8 582 #define RK3399_BCSH_CTRL 0x01bc 583 #define RK3399_CABC_CTRL0 0x01c0 584 #define RK3399_CABC_CTRL1 0x01c4 585 #define RK3399_CABC_CTRL2 0x01c8 586 #define RK3399_CABC_CTRL3 0x01cc 587 #define RK3399_CABC_GAUSS_LINE0_0 0x01d0 588 #define RK3399_CABC_GAUSS_LINE0_1 0x01d4 589 #define RK3399_CABC_GAUSS_LINE1_0 0x01d8 590 #define RK3399_CABC_GAUSS_LINE1_1 0x01dc 591 #define RK3399_CABC_GAUSS_LINE2_0 0x01e0 592 #define RK3399_CABC_GAUSS_LINE2_1 0x01e4 593 #define RK3399_FRC_LOWER01_0 0x01e8 594 #define RK3399_FRC_LOWER01_1 0x01ec 595 #define RK3399_FRC_LOWER10_0 0x01f0 596 #define RK3399_FRC_LOWER10_1 0x01f4 597 #define RK3399_FRC_LOWER11_0 0x01f8 598 #define RK3399_FRC_LOWER11_1 0x01fc 599 #define RK3399_AFBCD0_CTRL 0x0200 600 #define RK3399_AFBCD0_HDR_PTR 0x0204 601 #define RK3399_AFBCD0_PIC_SIZE 0x0208 602 #define RK3399_AFBCD0_STATUS 0x020c 603 #define RK3399_AFBCD1_CTRL 0x0220 604 #define RK3399_AFBCD1_HDR_PTR 0x0224 605 #define RK3399_AFBCD1_PIC_SIZE 0x0228 606 #define RK3399_AFBCD1_STATUS 0x022c 607 #define RK3399_AFBCD2_CTRL 0x0240 608 #define RK3399_AFBCD2_HDR_PTR 0x0244 609 #define RK3399_AFBCD2_PIC_SIZE 0x0248 610 #define RK3399_AFBCD2_STATUS 0x024c 611 #define RK3399_AFBCD3_CTRL 0x0260 612 #define RK3399_AFBCD3_HDR_PTR 0x0264 613 #define RK3399_AFBCD3_PIC_SIZE 0x0268 614 #define RK3399_AFBCD3_STATUS 0x026c 615 #define RK3399_INTR_EN0 0x0280 616 #define RK3399_INTR_CLEAR0 0x0284 617 #define RK3399_INTR_STATUS0 0x0288 618 #define RK3399_INTR_RAW_STATUS0 0x028c 619 #define RK3399_INTR_EN1 0x0290 620 #define RK3399_INTR_CLEAR1 0x0294 621 #define RK3399_INTR_STATUS1 0x0298 622 #define RK3399_INTR_RAW_STATUS1 0x029c 623 #define RK3399_LINE_FLAG 0x02a0 624 #define RK3399_VOP_STATUS 0x02a4 625 #define RK3399_BLANKING_VALUE 0x02a8 626 #define RK3399_MCU_BYPASS_PORT 0x02ac 627 #define RK3399_WIN0_DSP_BG 0x02b0 628 #define RK3399_WIN1_DSP_BG 0x02b4 629 #define RK3399_WIN2_DSP_BG 0x02b8 630 #define RK3399_WIN3_DSP_BG 0x02bc 631 #define RK3399_YUV2YUV_WIN 0x02c0 632 #define RK3399_YUV2YUV_POST 0x02c4 633 #define RK3399_AUTO_GATING_EN 0x02cc 634 #define RK3399_WIN0_CSC_COE 0x03a0 635 #define RK3399_WIN1_CSC_COE 0x03c0 636 #define RK3399_WIN2_CSC_COE 0x03e0 637 #define RK3399_WIN3_CSC_COE 0x0400 638 #define RK3399_HWC_CSC_COE 0x0420 639 #define RK3399_BCSH_R2Y_CSC_COE 0x0440 640 #define RK3399_BCSH_Y2R_CSC_COE 0x0460 641 #define RK3399_POST_YUV2YUV_Y2R_COE 0x0480 642 #define RK3399_POST_YUV2YUV_3X3_COE 0x04a0 643 #define RK3399_POST_YUV2YUV_R2Y_COE 0x04c0 644 #define RK3399_WIN0_YUV2YUV_Y2R 0x04e0 645 #define RK3399_WIN0_YUV2YUV_3X3 0x0500 646 #define RK3399_WIN0_YUV2YUV_R2Y 0x0520 647 #define RK3399_WIN1_YUV2YUV_Y2R 0x0540 648 #define RK3399_WIN1_YUV2YUV_3X3 0x0560 649 #define RK3399_WIN1_YUV2YUV_R2Y 0x0580 650 #define RK3399_WIN2_YUV2YUV_Y2R 0x05a0 651 #define RK3399_WIN2_YUV2YUV_3X3 0x05c0 652 #define RK3399_WIN2_YUV2YUV_R2Y 0x05e0 653 #define RK3399_WIN3_YUV2YUV_Y2R 0x0600 654 #define RK3399_WIN3_YUV2YUV_3X3 0x0620 655 #define RK3399_WIN3_YUV2YUV_R2Y 0x0640 656 #define RK3399_WIN2_LUT_ADDR 0x1000 657 #define RK3399_WIN3_LUT_ADDR 0x1400 658 #define RK3399_HWC_LUT_ADDR 0x1800 659 #define RK3399_CABC_GAMMA_LUT_ADDR 0x1c00 660 #define RK3399_GAMMA_LUT_ADDR 0x2000 661 /* rk3399 register definition end */ 662 663 /* rk3328 register definition end */ 664 #define RK3328_REG_CFG_DONE 0x00000000 665 #define RK3328_VERSION_INFO 0x00000004 666 #define RK3328_SYS_CTRL 0x00000008 667 #define RK3328_SYS_CTRL1 0x0000000c 668 #define RK3328_DSP_CTRL0 0x00000010 669 #define RK3328_DSP_CTRL1 0x00000014 670 #define RK3328_DSP_BG 0x00000018 671 #define RK3328_AUTO_GATING_EN 0x0000003c 672 #define RK3328_LINE_FLAG 0x00000040 673 #define RK3328_VOP_STATUS 0x00000044 674 #define RK3328_BLANKING_VALUE 0x00000048 675 #define RK3328_WIN0_DSP_BG 0x00000050 676 #define RK3328_WIN1_DSP_BG 0x00000054 677 #define RK3328_DBG_PERF_LATENCY_CTRL0 0x000000c0 678 #define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0 0x000000c4 679 #define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0 0x000000c8 680 #define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0 0x000000cc 681 #define RK3328_INTR_EN0 0x000000e0 682 #define RK3328_INTR_CLEAR0 0x000000e4 683 #define RK3328_INTR_STATUS0 0x000000e8 684 #define RK3328_INTR_RAW_STATUS0 0x000000ec 685 #define RK3328_INTR_EN1 0x000000f0 686 #define RK3328_INTR_CLEAR1 0x000000f4 687 #define RK3328_INTR_STATUS1 0x000000f8 688 #define RK3328_INTR_RAW_STATUS1 0x000000fc 689 #define RK3328_WIN0_CTRL0 0x00000100 690 #define RK3328_WIN0_CTRL1 0x00000104 691 #define RK3328_WIN0_COLOR_KEY 0x00000108 692 #define RK3328_WIN0_VIR 0x0000010c 693 #define RK3328_WIN0_YRGB_MST 0x00000110 694 #define RK3328_WIN0_CBR_MST 0x00000114 695 #define RK3328_WIN0_ACT_INFO 0x00000118 696 #define RK3328_WIN0_DSP_INFO 0x0000011c 697 #define RK3328_WIN0_DSP_ST 0x00000120 698 #define RK3328_WIN0_SCL_FACTOR_YRGB 0x00000124 699 #define RK3328_WIN0_SCL_FACTOR_CBR 0x00000128 700 #define RK3328_WIN0_SCL_OFFSET 0x0000012c 701 #define RK3328_WIN0_SRC_ALPHA_CTRL 0x00000130 702 #define RK3328_WIN0_DST_ALPHA_CTRL 0x00000134 703 #define RK3328_WIN0_FADING_CTRL 0x00000138 704 #define RK3328_WIN0_CTRL2 0x0000013c 705 #define RK3328_DBG_WIN0_REG0 0x000001f0 706 #define RK3328_DBG_WIN0_REG1 0x000001f4 707 #define RK3328_DBG_WIN0_REG2 0x000001f8 708 #define RK3328_DBG_WIN0_RESERVED 0x000001fc 709 #define RK3328_WIN1_CTRL0 0x00000200 710 #define RK3328_WIN1_CTRL1 0x00000204 711 #define RK3328_WIN1_COLOR_KEY 0x00000208 712 #define RK3328_WIN1_VIR 0x0000020c 713 #define RK3328_WIN1_YRGB_MST 0x00000210 714 #define RK3328_WIN1_CBR_MST 0x00000214 715 #define RK3328_WIN1_ACT_INFO 0x00000218 716 #define RK3328_WIN1_DSP_INFO 0x0000021c 717 #define RK3328_WIN1_DSP_ST 0x00000220 718 #define RK3328_WIN1_SCL_FACTOR_YRGB 0x00000224 719 #define RK3328_WIN1_SCL_FACTOR_CBR 0x00000228 720 #define RK3328_WIN1_SCL_OFFSET 0x0000022c 721 #define RK3328_WIN1_SRC_ALPHA_CTRL 0x00000230 722 #define RK3328_WIN1_DST_ALPHA_CTRL 0x00000234 723 #define RK3328_WIN1_FADING_CTRL 0x00000238 724 #define RK3328_WIN1_CTRL2 0x0000023c 725 #define RK3328_DBG_WIN1_REG0 0x000002f0 726 #define RK3328_DBG_WIN1_REG1 0x000002f4 727 #define RK3328_DBG_WIN1_REG2 0x000002f8 728 #define RK3328_DBG_WIN1_RESERVED 0x000002fc 729 #define RK3328_WIN2_CTRL0 0x00000300 730 #define RK3328_WIN2_CTRL1 0x00000304 731 #define RK3328_WIN2_COLOR_KEY 0x00000308 732 #define RK3328_WIN2_VIR 0x0000030c 733 #define RK3328_WIN2_YRGB_MST 0x00000310 734 #define RK3328_WIN2_CBR_MST 0x00000314 735 #define RK3328_WIN2_ACT_INFO 0x00000318 736 #define RK3328_WIN2_DSP_INFO 0x0000031c 737 #define RK3328_WIN2_DSP_ST 0x00000320 738 #define RK3328_WIN2_SCL_FACTOR_YRGB 0x00000324 739 #define RK3328_WIN2_SCL_FACTOR_CBR 0x00000328 740 #define RK3328_WIN2_SCL_OFFSET 0x0000032c 741 #define RK3328_WIN2_SRC_ALPHA_CTRL 0x00000330 742 #define RK3328_WIN2_DST_ALPHA_CTRL 0x00000334 743 #define RK3328_WIN2_FADING_CTRL 0x00000338 744 #define RK3328_WIN2_CTRL2 0x0000033c 745 #define RK3328_DBG_WIN2_REG0 0x000003f0 746 #define RK3328_DBG_WIN2_REG1 0x000003f4 747 #define RK3328_DBG_WIN2_REG2 0x000003f8 748 #define RK3328_DBG_WIN2_RESERVED 0x000003fc 749 #define RK3328_WIN3_CTRL0 0x00000400 750 #define RK3328_WIN3_CTRL1 0x00000404 751 #define RK3328_WIN3_COLOR_KEY 0x00000408 752 #define RK3328_WIN3_VIR 0x0000040c 753 #define RK3328_WIN3_YRGB_MST 0x00000410 754 #define RK3328_WIN3_CBR_MST 0x00000414 755 #define RK3328_WIN3_ACT_INFO 0x00000418 756 #define RK3328_WIN3_DSP_INFO 0x0000041c 757 #define RK3328_WIN3_DSP_ST 0x00000420 758 #define RK3328_WIN3_SCL_FACTOR_YRGB 0x00000424 759 #define RK3328_WIN3_SCL_FACTOR_CBR 0x00000428 760 #define RK3328_WIN3_SCL_OFFSET 0x0000042c 761 #define RK3328_WIN3_SRC_ALPHA_CTRL 0x00000430 762 #define RK3328_WIN3_DST_ALPHA_CTRL 0x00000434 763 #define RK3328_WIN3_FADING_CTRL 0x00000438 764 #define RK3328_WIN3_CTRL2 0x0000043c 765 #define RK3328_DBG_WIN3_REG0 0x000004f0 766 #define RK3328_DBG_WIN3_REG1 0x000004f4 767 #define RK3328_DBG_WIN3_REG2 0x000004f8 768 #define RK3328_DBG_WIN3_RESERVED 0x000004fc 769 770 #define RK3328_HWC_CTRL0 0x00000500 771 #define RK3328_HWC_CTRL1 0x00000504 772 #define RK3328_HWC_MST 0x00000508 773 #define RK3328_HWC_DSP_ST 0x0000050c 774 #define RK3328_HWC_SRC_ALPHA_CTRL 0x00000510 775 #define RK3328_HWC_DST_ALPHA_CTRL 0x00000514 776 #define RK3328_HWC_FADING_CTRL 0x00000518 777 #define RK3328_HWC_RESERVED1 0x0000051c 778 #define RK3328_POST_DSP_HACT_INFO 0x00000600 779 #define RK3328_POST_DSP_VACT_INFO 0x00000604 780 #define RK3328_POST_SCL_FACTOR_YRGB 0x00000608 781 #define RK3328_POST_RESERVED 0x0000060c 782 #define RK3328_POST_SCL_CTRL 0x00000610 783 #define RK3328_POST_DSP_VACT_INFO_F1 0x00000614 784 #define RK3328_DSP_HTOTAL_HS_END 0x00000618 785 #define RK3328_DSP_HACT_ST_END 0x0000061c 786 #define RK3328_DSP_VTOTAL_VS_END 0x00000620 787 #define RK3328_DSP_VACT_ST_END 0x00000624 788 #define RK3328_DSP_VS_ST_END_F1 0x00000628 789 #define RK3328_DSP_VACT_ST_END_F1 0x0000062c 790 #define RK3328_BCSH_COLOR_BAR 0x00000640 791 #define RK3328_BCSH_BCS 0x00000644 792 #define RK3328_BCSH_H 0x00000648 793 #define RK3328_BCSH_CTRL 0x0000064c 794 #define RK3328_FRC_LOWER01_0 0x00000678 795 #define RK3328_FRC_LOWER01_1 0x0000067c 796 #define RK3328_FRC_LOWER10_0 0x00000680 797 #define RK3328_FRC_LOWER10_1 0x00000684 798 #define RK3328_FRC_LOWER11_0 0x00000688 799 #define RK3328_FRC_LOWER11_1 0x0000068c 800 #define RK3328_DBG_POST_REG0 0x000006e8 801 #define RK3328_DBG_POST_RESERVED 0x000006ec 802 #define RK3328_DBG_DATAO 0x000006f0 803 #define RK3328_DBG_DATAO_2 0x000006f4 804 805 /* sdr to hdr */ 806 #define RK3328_SDR2HDR_CTRL 0x00000700 807 #define RK3328_EOTF_OETF_Y0 0x00000704 808 #define RK3328_RESERVED0001 0x00000708 809 #define RK3328_RESERVED0002 0x0000070c 810 #define RK3328_EOTF_OETF_Y1 0x00000710 811 #define RK3328_EOTF_OETF_Y64 0x0000080c 812 #define RK3328_OETF_DX_DXPOW1 0x00000810 813 #define RK3328_OETF_DX_DXPOW64 0x0000090c 814 #define RK3328_OETF_XN1 0x00000910 815 #define RK3328_OETF_XN63 0x00000a08 816 817 /* hdr to sdr */ 818 #define RK3328_HDR2SDR_CTRL 0x00000a10 819 #define RK3328_HDR2SDR_SRC_RANGE 0x00000a14 820 #define RK3328_HDR2SDR_NORMFACEETF 0x00000a18 821 #define RK3328_RESERVED0003 0x00000a1c 822 #define RK3328_HDR2SDR_DST_RANGE 0x00000a20 823 #define RK3328_HDR2SDR_NORMFACCGAMMA 0x00000a24 824 #define RK3328_EETF_OETF_Y0 0x00000a28 825 #define RK3328_SAT_Y0 0x00000a2c 826 #define RK3328_EETF_OETF_Y1 0x00000a30 827 #define RK3328_SAT_Y1 0x00000ab0 828 #define RK3328_SAT_Y8 0x00000acc 829 830 #define RK3328_HWC_LUT_ADDR 0x00000c00 831 832 /* rk3036 register definition */ 833 #define RK3036_SYS_CTRL 0x00 834 #define RK3036_DSP_CTRL0 0x04 835 #define RK3036_DSP_CTRL1 0x08 836 #define RK3036_INT_STATUS 0x10 837 #define RK3036_ALPHA_CTRL 0x14 838 #define RK3036_WIN0_COLOR_KEY 0x18 839 #define RK3036_WIN1_COLOR_KEY 0x1c 840 #define RK3036_WIN0_YRGB_MST 0x20 841 #define RK3036_WIN0_CBR_MST 0x24 842 #define RK3036_WIN1_VIR 0x28 843 #define RK3036_AXI_BUS_CTRL 0x2c 844 #define RK3036_WIN0_VIR 0x30 845 #define RK3036_WIN0_ACT_INFO 0x34 846 #define RK3036_WIN0_DSP_INFO 0x38 847 #define RK3036_WIN0_DSP_ST 0x3c 848 #define RK3036_WIN0_SCL_FACTOR_YRGB 0x40 849 #define RK3036_WIN0_SCL_FACTOR_CBR 0x44 850 #define RK3036_WIN0_SCL_OFFSET 0x48 851 #define RK3036_HWC_MST 0x58 852 #define RK3036_HWC_DSP_ST 0x5c 853 #define RK3036_DSP_HTOTAL_HS_END 0x6c 854 #define RK3036_DSP_HACT_ST_END 0x70 855 #define RK3036_DSP_VTOTAL_VS_END 0x74 856 #define RK3036_DSP_VACT_ST_END 0x78 857 #define RK3036_DSP_VS_ST_END_F1 0x7c 858 #define RK3036_DSP_VACT_ST_END_F1 0x80 859 #define RK3036_GATHER_TRANSFER 0x84 860 #define RK3036_VERSION_INFO 0x94 861 #define RK3036_REG_CFG_DONE 0x90 862 #define RK3036_WIN1_MST 0xa0 863 #define RK3036_WIN1_ACT_INFO 0xb4 864 #define RK3036_WIN1_DSP_INFO 0xb8 865 #define RK3036_WIN1_DSP_ST 0xbc 866 #define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0 867 #define RK3036_WIN1_SCL_OFFSET 0xc8 868 #define RK3036_BCSH_CTRL 0xd0 869 #define RK3036_BCSH_COLOR_BAR 0xd4 870 #define RK3036_BCSH_BCS 0xd8 871 #define RK3036_BCSH_H 0xdc 872 #define RK3036_WIN1_LUT_ADDR 0x400 873 #define RK3036_HWC_LUT_ADDR 0x800 874 /* rk3036 register definition end */ 875 876 /* rk3366 register definition */ 877 #define RK3366_LIT_REG_CFG_DONE 0x00000 878 #define RK3366_LIT_VERSION 0x00004 879 #define RK3366_LIT_DSP_BG 0x00008 880 #define RK3366_LIT_MCU_CTRL 0x0000c 881 #define RK3366_LIT_SYS_CTRL0 0x00010 882 #define RK3366_LIT_SYS_CTRL1 0x00014 883 #define RK3366_LIT_SYS_CTRL2 0x00018 884 #define RK3366_LIT_DSP_CTRL0 0x00020 885 #define RK3366_LIT_DSP_CTRL2 0x00028 886 #define RK3366_LIT_VOP_STATUS 0x0002c 887 #define RK3366_LIT_LINE_FLAG 0x00030 888 #define RK3366_LIT_INTR_EN 0x00034 889 #define RK3366_LIT_INTR_CLEAR 0x00038 890 #define RK3366_LIT_INTR_STATUS 0x0003c 891 #define RK3366_LIT_WIN0_CTRL0 0x00050 892 #define RK3366_LIT_WIN0_CTRL1 0x00054 893 #define RK3366_LIT_WIN0_COLOR_KEY 0x00058 894 #define RK3366_LIT_WIN0_VIR 0x0005c 895 #define RK3366_LIT_WIN0_YRGB_MST0 0x00060 896 #define RK3366_LIT_WIN0_CBR_MST0 0x00064 897 #define RK3366_LIT_WIN0_ACT_INFO 0x00068 898 #define RK3366_LIT_WIN0_DSP_INFO 0x0006c 899 #define RK3366_LIT_WIN0_DSP_ST 0x00070 900 #define RK3366_LIT_WIN0_SCL_FACTOR_YRGB 0x00074 901 #define RK3366_LIT_WIN0_SCL_FACTOR_CBR 0x00078 902 #define RK3366_LIT_WIN0_SCL_OFFSET 0x0007c 903 #define RK3366_LIT_WIN0_ALPHA_CTRL 0x00080 904 #define RK3366_LIT_WIN1_CTRL0 0x00090 905 #define RK3366_LIT_WIN1_CTRL1 0x00094 906 #define RK3366_LIT_WIN1_VIR 0x00098 907 #define RK3366_LIT_WIN1_MST 0x000a0 908 #define RK3366_LIT_WIN1_DSP_INFO 0x000a4 909 #define RK3366_LIT_WIN1_DSP_ST 0x000a8 910 #define RK3366_LIT_WIN1_COLOR_KEY 0x000ac 911 #define RK3366_LIT_WIN1_ALPHA_CTRL 0x000bc 912 #define RK3366_LIT_HWC_CTRL0 0x000e0 913 #define RK3366_LIT_HWC_CTRL1 0x000e4 914 #define RK3366_LIT_HWC_MST 0x000e8 915 #define RK3366_LIT_HWC_DSP_ST 0x000ec 916 #define RK3366_LIT_HWC_ALPHA_CTRL 0x000f0 917 #define RK3366_LIT_DSP_HTOTAL_HS_END 0x00100 918 #define RK3366_LIT_DSP_HACT_ST_END 0x00104 919 #define RK3366_LIT_DSP_VTOTAL_VS_END 0x00108 920 #define RK3366_LIT_DSP_VACT_ST_END 0x0010c 921 #define RK3366_LIT_DSP_VS_ST_END_F1 0x00110 922 #define RK3366_LIT_DSP_VACT_ST_END_F1 0x00114 923 #define RK3366_LIT_BCSH_CTRL 0x00160 924 #define RK3366_LIT_BCSH_COL_BAR 0x00164 925 #define RK3366_LIT_BCSH_BCS 0x00168 926 #define RK3366_LIT_BCSH_H 0x0016c 927 #define RK3366_LIT_FRC_LOWER01_0 0x00170 928 #define RK3366_LIT_FRC_LOWER01_1 0x00174 929 #define RK3366_LIT_FRC_LOWER10_0 0x00178 930 #define RK3366_LIT_FRC_LOWER10_1 0x0017c 931 #define RK3366_LIT_FRC_LOWER11_0 0x00180 932 #define RK3366_LIT_FRC_LOWER11_1 0x00184 933 #define RK3366_LIT_MCU_RW_BYPASS_PORT 0x0018c 934 #define RK3366_LIT_DBG_REG_000 0x00190 935 #define RK3366_LIT_BLANKING_VALUE 0x001f4 936 #define RK3366_LIT_FLAG_REG_FRM_VALID 0x001f8 937 #define RK3366_LIT_FLAG_REG 0x001fc 938 #define RK3366_LIT_HWC_LUT_ADDR 0x00600 939 #define RK3366_LIT_GAMMA_LUT_ADDR 0x00a00 940 /* rk3366 register definition end */ 941 942 /* px30 register definition */ 943 #define PX30_CABC_CTRL0 0x00200 944 #define PX30_CABC_CTRL1 0x00204 945 #define PX30_CABC_CTRL2 0x00208 946 #define PX30_CABC_CTRL3 0x0020c 947 #define PX30_CABC_GAUSS_LINE0_0 0x00210 948 #define PX30_CABC_GAUSS_LINE0_1 0x00214 949 #define PX30_CABC_GAUSS_LINE1_0 0x00218 950 #define PX30_CABC_GAUSS_LINE1_1 0x0021c 951 #define PX30_CABC_GAUSS_LINE2_0 0x00220 952 #define PX30_CABC_GAUSS_LINE2_1 0x00224 953 #define PX30_AFBCD0_CTRL 0x00240 954 #define PX30_AFBCD0_HDR_PTR 0x00244 955 #define PX30_AFBCD0_PIC_SIZE 0x00248 956 #define PX30_AFBCD0_PIC_OFFSET 0x0024c 957 #define PX30_AFBCD0_AXI_CTRL 0x00250 958 /* px30 register definition end */ 959 #endif /* _ROCKCHIP_VOP_REG_H */ 960