1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_VOP_REG_H 8 #define _ROCKCHIP_VOP_REG_H 9 10 /* rk3288 register definition */ 11 #define RK3288_REG_CFG_DONE 0x0000 12 #define RK3288_VERSION_INFO 0x0004 13 #define RK3288_SYS_CTRL 0x0008 14 #define RK3288_SYS_CTRL1 0x000c 15 #define RK3288_DSP_CTRL0 0x0010 16 #define RK3288_DSP_CTRL1 0x0014 17 #define RK3288_DSP_BG 0x0018 18 #define RK3288_MCU_CTRL 0x001c 19 #define RK3288_INTR_CTRL0 0x0020 20 #define RK3288_INTR_CTRL1 0x0024 21 #define RK3288_WIN0_CTRL0 0x0030 22 #define RK3288_WIN0_CTRL1 0x0034 23 #define RK3288_WIN0_COLOR_KEY 0x0038 24 #define RK3288_WIN0_VIR 0x003c 25 #define RK3288_WIN0_YRGB_MST 0x0040 26 #define RK3288_WIN0_CBR_MST 0x0044 27 #define RK3288_WIN0_ACT_INFO 0x0048 28 #define RK3288_WIN0_DSP_INFO 0x004c 29 #define RK3288_WIN0_DSP_ST 0x0050 30 #define RK3288_WIN0_SCL_FACTOR_YRGB 0x0054 31 #define RK3288_WIN0_SCL_FACTOR_CBR 0x0058 32 #define RK3288_WIN0_SCL_OFFSET 0x005c 33 #define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060 34 #define RK3288_WIN0_DST_ALPHA_CTRL 0x0064 35 #define RK3288_WIN0_FADING_CTRL 0x0068 36 37 /* win1 register */ 38 #define RK3288_WIN1_CTRL0 0x0070 39 #define RK3288_WIN1_CTRL1 0x0074 40 #define RK3288_WIN1_COLOR_KEY 0x0078 41 #define RK3288_WIN1_VIR 0x007c 42 #define RK3288_WIN1_YRGB_MST 0x0080 43 #define RK3288_WIN1_CBR_MST 0x0084 44 #define RK3288_WIN1_ACT_INFO 0x0088 45 #define RK3288_WIN1_DSP_INFO 0x008c 46 #define RK3288_WIN1_DSP_ST 0x0090 47 #define RK3288_WIN1_SCL_FACTOR_YRGB 0x0094 48 #define RK3288_WIN1_SCL_FACTOR_CBR 0x0098 49 #define RK3288_WIN1_SCL_OFFSET 0x009c 50 #define RK3288_WIN1_SRC_ALPHA_CTRL 0x00a0 51 #define RK3288_WIN1_DST_ALPHA_CTRL 0x00a4 52 #define RK3288_WIN1_FADING_CTRL 0x00a8 53 /* win2 register */ 54 #define RK3288_WIN2_CTRL0 0x00b0 55 #define RK3288_WIN2_CTRL1 0x00b4 56 #define RK3288_WIN2_VIR0_1 0x00b8 57 #define RK3288_WIN2_VIR2_3 0x00bc 58 #define RK3288_WIN2_MST0 0x00c0 59 #define RK3288_WIN2_DSP_INFO0 0x00c4 60 #define RK3288_WIN2_DSP_ST0 0x00c8 61 #define RK3288_WIN2_COLOR_KEY 0x00cc 62 #define RK3288_WIN2_MST1 0x00d0 63 #define RK3288_WIN2_DSP_INFO1 0x00d4 64 #define RK3288_WIN2_DSP_ST1 0x00d8 65 #define RK3288_WIN2_SRC_ALPHA_CTRL 0x00dc 66 #define RK3288_WIN2_MST2 0x00e0 67 #define RK3288_WIN2_DSP_INFO2 0x00e4 68 #define RK3288_WIN2_DSP_ST2 0x00e8 69 #define RK3288_WIN2_DST_ALPHA_CTRL 0x00ec 70 #define RK3288_WIN2_MST3 0x00f0 71 #define RK3288_WIN2_DSP_INFO3 0x00f4 72 #define RK3288_WIN2_DSP_ST3 0x00f8 73 #define RK3288_WIN2_FADING_CTRL 0x00fc 74 /* win3 register */ 75 #define RK3288_WIN3_CTRL0 0x0100 76 #define RK3288_WIN3_CTRL1 0x0104 77 #define RK3288_WIN3_VIR0_1 0x0108 78 #define RK3288_WIN3_VIR2_3 0x010c 79 #define RK3288_WIN3_MST0 0x0110 80 #define RK3288_WIN3_DSP_INFO0 0x0114 81 #define RK3288_WIN3_DSP_ST0 0x0118 82 #define RK3288_WIN3_COLOR_KEY 0x011c 83 #define RK3288_WIN3_MST1 0x0120 84 #define RK3288_WIN3_DSP_INFO1 0x0124 85 #define RK3288_WIN3_DSP_ST1 0x0128 86 #define RK3288_WIN3_SRC_ALPHA_CTRL 0x012c 87 #define RK3288_WIN3_MST2 0x0130 88 #define RK3288_WIN3_DSP_INFO2 0x0134 89 #define RK3288_WIN3_DSP_ST2 0x0138 90 #define RK3288_WIN3_DST_ALPHA_CTRL 0x013c 91 #define RK3288_WIN3_MST3 0x0140 92 #define RK3288_WIN3_DSP_INFO3 0x0144 93 #define RK3288_WIN3_DSP_ST3 0x0148 94 #define RK3288_WIN3_FADING_CTRL 0x014c 95 /* hwc register */ 96 #define RK3288_HWC_CTRL0 0x0150 97 #define RK3288_HWC_CTRL1 0x0154 98 #define RK3288_HWC_MST 0x0158 99 #define RK3288_HWC_DSP_ST 0x015c 100 #define RK3288_HWC_SRC_ALPHA_CTRL 0x0160 101 #define RK3288_HWC_DST_ALPHA_CTRL 0x0164 102 #define RK3288_HWC_FADING_CTRL 0x0168 103 /* post process register */ 104 #define RK3288_POST_DSP_HACT_INFO 0x0170 105 #define RK3288_POST_DSP_VACT_INFO 0x0174 106 #define RK3288_POST_SCL_FACTOR_YRGB 0x0178 107 #define RK3288_POST_SCL_CTRL 0x0180 108 #define RK3288_POST_DSP_VACT_INFO_F1 0x0184 109 #define RK3288_DSP_HTOTAL_HS_END 0x0188 110 #define RK3288_DSP_HACT_ST_END 0x018c 111 #define RK3288_DSP_VTOTAL_VS_END 0x0190 112 #define RK3288_DSP_VACT_ST_END 0x0194 113 #define RK3288_DSP_VS_ST_END_F1 0x0198 114 #define RK3288_DSP_VACT_ST_END_F1 0x019c 115 116 #define RK3288_BCSH_COLOR_BAR 0x01b0 117 #define RK3288_BCSH_BCS 0x01b4 118 #define RK3288_BCSH_H 0x01b8 119 #define RK3288_GRF_SOC_CON15 0x03a4 120 /* register definition end */ 121 122 /* rk3368 register definition */ 123 #define RK3368_REG_CFG_DONE 0x0000 124 #define RK3368_VERSION_INFO 0x0004 125 #define RK3368_SYS_CTRL 0x0008 126 #define RK3368_SYS_CTRL1 0x000c 127 #define RK3368_DSP_CTRL0 0x0010 128 #define RK3368_DSP_CTRL1 0x0014 129 #define RK3368_DSP_BG 0x0018 130 #define RK3368_MCU_CTRL 0x001c 131 #define RK3368_LINE_FLAG 0x0020 132 #define RK3368_INTR_EN 0x0024 133 #define RK3368_INTR_CLEAR 0x0028 134 #define RK3368_INTR_STATUS 0x002c 135 #define RK3368_WIN0_CTRL0 0x0030 136 #define RK3368_WIN0_CTRL1 0x0034 137 #define RK3368_WIN0_COLOR_KEY 0x0038 138 #define RK3368_WIN0_VIR 0x003c 139 #define RK3368_WIN0_YRGB_MST 0x0040 140 #define RK3368_WIN0_CBR_MST 0x0044 141 #define RK3368_WIN0_ACT_INFO 0x0048 142 #define RK3368_WIN0_DSP_INFO 0x004c 143 #define RK3368_WIN0_DSP_ST 0x0050 144 #define RK3368_WIN0_SCL_FACTOR_YRGB 0x0054 145 #define RK3368_WIN0_SCL_FACTOR_CBR 0x0058 146 #define RK3368_WIN0_SCL_OFFSET 0x005c 147 #define RK3368_WIN0_SRC_ALPHA_CTRL 0x0060 148 #define RK3368_WIN0_DST_ALPHA_CTRL 0x0064 149 #define RK3368_WIN0_FADING_CTRL 0x0068 150 #define RK3368_WIN0_CTRL2 0x006c 151 #define RK3368_WIN1_CTRL0 0x0070 152 #define RK3368_WIN1_CTRL1 0x0074 153 #define RK3368_WIN1_COLOR_KEY 0x0078 154 #define RK3368_WIN1_VIR 0x007c 155 #define RK3368_WIN1_YRGB_MST 0x0080 156 #define RK3368_WIN1_CBR_MST 0x0084 157 #define RK3368_WIN1_ACT_INFO 0x0088 158 #define RK3368_WIN1_DSP_INFO 0x008c 159 #define RK3368_WIN1_DSP_ST 0x0090 160 #define RK3368_WIN1_SCL_FACTOR_YRGB 0x0094 161 #define RK3368_WIN1_SCL_FACTOR_CBR 0x0098 162 #define RK3368_WIN1_SCL_OFFSET 0x009c 163 #define RK3368_WIN1_SRC_ALPHA_CTRL 0x00a0 164 #define RK3368_WIN1_DST_ALPHA_CTRL 0x00a4 165 #define RK3368_WIN1_FADING_CTRL 0x00a8 166 #define RK3368_WIN1_CTRL2 0x00ac 167 #define RK3368_WIN2_CTRL0 0x00b0 168 #define RK3368_WIN2_CTRL1 0x00b4 169 #define RK3368_WIN2_VIR0_1 0x00b8 170 #define RK3368_WIN2_VIR2_3 0x00bc 171 #define RK3368_WIN2_MST0 0x00c0 172 #define RK3368_WIN2_DSP_INFO0 0x00c4 173 #define RK3368_WIN2_DSP_ST0 0x00c8 174 #define RK3368_WIN2_COLOR_KEY 0x00cc 175 #define RK3368_WIN2_MST1 0x00d0 176 #define RK3368_WIN2_DSP_INFO1 0x00d4 177 #define RK3368_WIN2_DSP_ST1 0x00d8 178 #define RK3368_WIN2_SRC_ALPHA_CTRL 0x00dc 179 #define RK3368_WIN2_MST2 0x00e0 180 #define RK3368_WIN2_DSP_INFO2 0x00e4 181 #define RK3368_WIN2_DSP_ST2 0x00e8 182 #define RK3368_WIN2_DST_ALPHA_CTRL 0x00ec 183 #define RK3368_WIN2_MST3 0x00f0 184 #define RK3368_WIN2_DSP_INFO3 0x00f4 185 #define RK3368_WIN2_DSP_ST3 0x00f8 186 #define RK3368_WIN2_FADING_CTRL 0x00fc 187 #define RK3368_WIN3_CTRL0 0x0100 188 #define RK3368_WIN3_CTRL1 0x0104 189 #define RK3368_WIN3_VIR0_1 0x0108 190 #define RK3368_WIN3_VIR2_3 0x010c 191 #define RK3368_WIN3_MST0 0x0110 192 #define RK3368_WIN3_DSP_INFO0 0x0114 193 #define RK3368_WIN3_DSP_ST0 0x0118 194 #define RK3368_WIN3_COLOR_KEY 0x011c 195 #define RK3368_WIN3_MST1 0x0120 196 #define RK3368_WIN3_DSP_INFO1 0x0124 197 #define RK3368_WIN3_DSP_ST1 0x0128 198 #define RK3368_WIN3_SRC_ALPHA_CTRL 0x012c 199 #define RK3368_WIN3_MST2 0x0130 200 #define RK3368_WIN3_DSP_INFO2 0x0134 201 #define RK3368_WIN3_DSP_ST2 0x0138 202 #define RK3368_WIN3_DST_ALPHA_CTRL 0x013c 203 #define RK3368_WIN3_MST3 0x0140 204 #define RK3368_WIN3_DSP_INFO3 0x0144 205 #define RK3368_WIN3_DSP_ST3 0x0148 206 #define RK3368_WIN3_FADING_CTRL 0x014c 207 #define RK3368_HWC_CTRL0 0x0150 208 #define RK3368_HWC_CTRL1 0x0154 209 #define RK3368_HWC_MST 0x0158 210 #define RK3368_HWC_DSP_ST 0x015c 211 #define RK3368_HWC_SRC_ALPHA_CTRL 0x0160 212 #define RK3368_HWC_DST_ALPHA_CTRL 0x0164 213 #define RK3368_HWC_FADING_CTRL 0x0168 214 #define RK3368_HWC_RESERVED1 0x016c 215 #define RK3368_POST_DSP_HACT_INFO 0x0170 216 #define RK3368_POST_DSP_VACT_INFO 0x0174 217 #define RK3368_POST_SCL_FACTOR_YRGB 0x0178 218 #define RK3368_POST_RESERVED 0x017c 219 #define RK3368_POST_SCL_CTRL 0x0180 220 #define RK3368_POST_DSP_VACT_INFO_F1 0x0184 221 #define RK3368_DSP_HTOTAL_HS_END 0x0188 222 #define RK3368_DSP_HACT_ST_END 0x018c 223 #define RK3368_DSP_VTOTAL_VS_END 0x0190 224 #define RK3368_DSP_VACT_ST_END 0x0194 225 #define RK3368_DSP_VS_ST_END_F1 0x0198 226 #define RK3368_DSP_VACT_ST_END_F1 0x019c 227 #define RK3368_PWM_CTRL 0x01a0 228 #define RK3368_PWM_PERIOD_HPR 0x01a4 229 #define RK3368_PWM_DUTY_LPR 0x01a8 230 #define RK3368_PWM_CNT 0x01ac 231 #define RK3368_BCSH_COLOR_BAR 0x01b0 232 #define RK3368_BCSH_BCS 0x01b4 233 #define RK3368_BCSH_H 0x01b8 234 #define RK3368_BCSH_CTRL 0x01bc 235 #define RK3368_CABC_CTRL0 0x01c0 236 #define RK3368_CABC_CTRL1 0x01c4 237 #define RK3368_CABC_CTRL2 0x01c8 238 #define RK3368_CABC_CTRL3 0x01cc 239 #define RK3368_CABC_GAUSS_LINE0_0 0x01d0 240 #define RK3368_CABC_GAUSS_LINE0_1 0x01d4 241 #define RK3368_CABC_GAUSS_LINE1_0 0x01d8 242 #define RK3368_CABC_GAUSS_LINE1_1 0x01dc 243 #define RK3368_CABC_GAUSS_LINE2_0 0x01e0 244 #define RK3368_CABC_GAUSS_LINE2_1 0x01e4 245 #define RK3368_FRC_LOWER01_0 0x01e8 246 #define RK3368_FRC_LOWER01_1 0x01ec 247 #define RK3368_FRC_LOWER10_0 0x01f0 248 #define RK3368_FRC_LOWER10_1 0x01f4 249 #define RK3368_FRC_LOWER11_0 0x01f8 250 #define RK3368_FRC_LOWER11_1 0x01fc 251 #define RK3368_IFBDC_CTRL 0x0200 252 #define RK3368_IFBDC_TILES_NUM 0x0204 253 #define RK3368_IFBDC_FRAME_RST_CYCLE 0x0208 254 #define RK3368_IFBDC_BASE_ADDR 0x020c 255 #define RK3368_IFBDC_MB_SIZE 0x0210 256 #define RK3368_IFBDC_CMP_INDEX_INIT 0x0214 257 #define RK3368_IFBDC_VIR 0x0220 258 #define RK3368_IFBDC_DEBUG0 0x0230 259 #define RK3368_IFBDC_DEBUG1 0x0234 260 #define RK3368_LATENCY_CTRL0 0x0250 261 #define RK3368_RD_MAX_LATENCY_NUM0 0x0254 262 #define RK3368_RD_LATENCY_THR_NUM0 0x0258 263 #define RK3368_RD_LATENCY_SAMP_NUM0 0x025c 264 #define RK3368_WIN0_DSP_BG 0x0260 265 #define RK3368_WIN1_DSP_BG 0x0264 266 #define RK3368_WIN2_DSP_BG 0x0268 267 #define RK3368_WIN3_DSP_BG 0x026c 268 #define RK3368_SCAN_LINE_NUM 0x0270 269 #define RK3368_CABC_DEBUG0 0x0274 270 #define RK3368_CABC_DEBUG1 0x0278 271 #define RK3368_CABC_DEBUG2 0x027c 272 #define RK3368_DBG_REG_000 0x0280 273 #define RK3368_DBG_REG_001 0x0284 274 #define RK3368_DBG_REG_002 0x0288 275 #define RK3368_DBG_REG_003 0x028c 276 #define RK3368_DBG_REG_004 0x0290 277 #define RK3368_DBG_REG_005 0x0294 278 #define RK3368_DBG_REG_006 0x0298 279 #define RK3368_DBG_REG_007 0x029c 280 #define RK3368_DBG_REG_008 0x02a0 281 #define RK3368_DBG_REG_016 0x02c0 282 #define RK3368_DBG_REG_017 0x02c4 283 #define RK3368_DBG_REG_018 0x02c8 284 #define RK3368_DBG_REG_019 0x02cc 285 #define RK3368_DBG_REG_020 0x02d0 286 #define RK3368_DBG_REG_021 0x02d4 287 #define RK3368_DBG_REG_022 0x02d8 288 #define RK3368_DBG_REG_023 0x02dc 289 #define RK3368_DBG_REG_028 0x02f0 290 #define RK3368_MMU_DTE_ADDR 0x0300 291 #define RK3368_MMU_STATUS 0x0304 292 #define RK3368_MMU_COMMAND 0x0308 293 #define RK3368_MMU_PAGE_FAULT_ADDR 0x030c 294 #define RK3368_MMU_ZAP_ONE_LINE 0x0310 295 #define RK3368_MMU_INT_RAWSTAT 0x0314 296 #define RK3368_MMU_INT_CLEAR 0x0318 297 #define RK3368_MMU_INT_MASK 0x031c 298 #define RK3368_MMU_INT_STATUS 0x0320 299 #define RK3368_MMU_AUTO_GATING 0x0324 300 #define RK3368_WIN2_LUT_ADDR 0x0400 301 #define RK3368_WIN3_LUT_ADDR 0x0800 302 #define RK3368_HWC_LUT_ADDR 0x0c00 303 #define RK3368_GAMMA_LUT_ADDR 0x1000 304 #define RK3368_CABC_GAMMA_LUT_ADDR 0x1800 305 #define RK3368_MCU_BYPASS_WPORT 0x2200 306 #define RK3368_MCU_BYPASS_RPORT 0x2300 307 #define RK3368_GRF_SOC_CON6 0x0418 308 /* rk3368 register definition end */ 309 310 #define RK3366_REG_CFG_DONE 0x0000 311 #define RK3366_VERSION_INFO 0x0004 312 #define RK3366_SYS_CTRL 0x0008 313 #define RK3366_SYS_CTRL1 0x000c 314 #define RK3366_DSP_CTRL0 0x0010 315 #define RK3366_DSP_CTRL1 0x0014 316 #define RK3366_DSP_BG 0x0018 317 #define RK3366_MCU_CTRL 0x001c 318 #define RK3366_WB_CTRL0 0x0020 319 #define RK3366_WB_CTRL1 0x0024 320 #define RK3366_WB_YRGB_MST 0x0028 321 #define RK3366_WB_CBR_MST 0x002c 322 #define RK3366_WIN0_CTRL0 0x0030 323 #define RK3366_WIN0_CTRL1 0x0034 324 #define RK3366_WIN0_COLOR_KEY 0x0038 325 #define RK3366_WIN0_VIR 0x003c 326 #define RK3366_WIN0_YRGB_MST 0x0040 327 #define RK3366_WIN0_CBR_MST 0x0044 328 #define RK3366_WIN0_ACT_INFO 0x0048 329 #define RK3366_WIN0_DSP_INFO 0x004c 330 #define RK3366_WIN0_DSP_ST 0x0050 331 #define RK3366_WIN0_SCL_FACTOR_YRGB 0x0054 332 #define RK3366_WIN0_SCL_FACTOR_CBR 0x0058 333 #define RK3366_WIN0_SCL_OFFSET 0x005c 334 #define RK3366_WIN0_SRC_ALPHA_CTRL 0x0060 335 #define RK3366_WIN0_DST_ALPHA_CTRL 0x0064 336 #define RK3366_WIN0_FADING_CTRL 0x0068 337 #define RK3366_WIN0_CTRL2 0x006c 338 #define RK3366_WIN1_CTRL0 0x0070 339 #define RK3366_WIN1_CTRL1 0x0074 340 #define RK3366_WIN1_COLOR_KEY 0x0078 341 #define RK3366_WIN1_VIR 0x007c 342 #define RK3366_WIN1_YRGB_MST 0x0080 343 #define RK3366_WIN1_CBR_MST 0x0084 344 #define RK3366_WIN1_ACT_INFO 0x0088 345 #define RK3366_WIN1_DSP_INFO 0x008c 346 #define RK3366_WIN1_DSP_ST 0x0090 347 #define RK3366_WIN1_SCL_FACTOR_YRGB 0x0094 348 #define RK3366_WIN1_SCL_FACTOR_CBR 0x0098 349 #define RK3366_WIN1_SCL_OFFSET 0x009c 350 #define RK3366_WIN1_SRC_ALPHA_CTRL 0x00a0 351 #define RK3366_WIN1_DST_ALPHA_CTRL 0x00a4 352 #define RK3366_WIN1_FADING_CTRL 0x00a8 353 #define RK3366_WIN1_CTRL2 0x00ac 354 #define RK3366_WIN2_CTRL0 0x00b0 355 #define RK3366_WIN2_CTRL1 0x00b4 356 #define RK3366_WIN2_VIR0_1 0x00b8 357 #define RK3366_WIN2_VIR2_3 0x00bc 358 #define RK3366_WIN2_MST0 0x00c0 359 #define RK3366_WIN2_DSP_INFO0 0x00c4 360 #define RK3366_WIN2_DSP_ST0 0x00c8 361 #define RK3366_WIN2_COLOR_KEY 0x00cc 362 #define RK3366_WIN2_MST1 0x00d0 363 #define RK3366_WIN2_DSP_INFO1 0x00d4 364 #define RK3366_WIN2_DSP_ST1 0x00d8 365 #define RK3366_WIN2_SRC_ALPHA_CTRL 0x00dc 366 #define RK3366_WIN2_MST2 0x00e0 367 #define RK3366_WIN2_DSP_INFO2 0x00e4 368 #define RK3366_WIN2_DSP_ST2 0x00e8 369 #define RK3366_WIN2_DST_ALPHA_CTRL 0x00ec 370 #define RK3366_WIN2_MST3 0x00f0 371 #define RK3366_WIN2_DSP_INFO3 0x00f4 372 #define RK3366_WIN2_DSP_ST3 0x00f8 373 #define RK3366_WIN2_FADING_CTRL 0x00fc 374 #define RK3366_WIN3_CTRL0 0x0100 375 #define RK3366_WIN3_CTRL1 0x0104 376 #define RK3366_WIN3_VIR0_1 0x0108 377 #define RK3366_WIN3_VIR2_3 0x010c 378 #define RK3366_WIN3_MST0 0x0110 379 #define RK3366_WIN3_DSP_INFO0 0x0114 380 #define RK3366_WIN3_DSP_ST0 0x0118 381 #define RK3366_WIN3_COLOR_KEY 0x011c 382 #define RK3366_WIN3_MST1 0x0120 383 #define RK3366_WIN3_DSP_INFO1 0x0124 384 #define RK3366_WIN3_DSP_ST1 0x0128 385 #define RK3366_WIN3_SRC_ALPHA_CTRL 0x012c 386 #define RK3366_WIN3_MST2 0x0130 387 #define RK3366_WIN3_DSP_INFO2 0x0134 388 #define RK3366_WIN3_DSP_ST2 0x0138 389 #define RK3366_WIN3_DST_ALPHA_CTRL 0x013c 390 #define RK3366_WIN3_MST3 0x0140 391 #define RK3366_WIN3_DSP_INFO3 0x0144 392 #define RK3366_WIN3_DSP_ST3 0x0148 393 #define RK3366_WIN3_FADING_CTRL 0x014c 394 #define RK3366_HWC_CTRL0 0x0150 395 #define RK3366_HWC_CTRL1 0x0154 396 #define RK3366_HWC_MST 0x0158 397 #define RK3366_HWC_DSP_ST 0x015c 398 #define RK3366_HWC_SRC_ALPHA_CTRL 0x0160 399 #define RK3366_HWC_DST_ALPHA_CTRL 0x0164 400 #define RK3366_HWC_FADING_CTRL 0x0168 401 #define RK3366_HWC_RESERVED1 0x016c 402 #define RK3366_POST_DSP_HACT_INFO 0x0170 403 #define RK3366_POST_DSP_VACT_INFO 0x0174 404 #define RK3366_POST_SCL_FACTOR_YRGB 0x0178 405 #define RK3366_POST_RESERVED 0x017c 406 #define RK3366_POST_SCL_CTRL 0x0180 407 #define RK3366_POST_DSP_VACT_INFO_F1 0x0184 408 #define RK3366_DSP_HTOTAL_HS_END 0x0188 409 #define RK3366_DSP_HACT_ST_END 0x018c 410 #define RK3366_DSP_VTOTAL_VS_END 0x0190 411 #define RK3366_DSP_VACT_ST_END 0x0194 412 #define RK3366_DSP_VS_ST_END_F1 0x0198 413 #define RK3366_DSP_VACT_ST_END_F1 0x019c 414 #define RK3366_PWM_CTRL 0x01a0 415 #define RK3366_PWM_PERIOD_HPR 0x01a4 416 #define RK3366_PWM_DUTY_LPR 0x01a8 417 #define RK3366_PWM_CNT 0x01ac 418 #define RK3366_BCSH_COLOR_BAR 0x01b0 419 #define RK3366_BCSH_BCS 0x01b4 420 #define RK3366_BCSH_H 0x01b8 421 #define RK3366_BCSH_CTRL 0x01bc 422 #define RK3366_CABC_CTRL0 0x01c0 423 #define RK3366_CABC_CTRL1 0x01c4 424 #define RK3366_CABC_CTRL2 0x01c8 425 #define RK3366_CABC_CTRL3 0x01cc 426 #define RK3366_CABC_GAUSS_LINE0_0 0x01d0 427 #define RK3366_CABC_GAUSS_LINE0_1 0x01d4 428 #define RK3366_CABC_GAUSS_LINE1_0 0x01d8 429 #define RK3366_CABC_GAUSS_LINE1_1 0x01dc 430 #define RK3366_CABC_GAUSS_LINE2_0 0x01e0 431 #define RK3366_CABC_GAUSS_LINE2_1 0x01e4 432 #define RK3366_FRC_LOWER01_0 0x01e8 433 #define RK3366_FRC_LOWER01_1 0x01ec 434 #define RK3366_FRC_LOWER10_0 0x01f0 435 #define RK3366_FRC_LOWER10_1 0x01f4 436 #define RK3366_FRC_LOWER11_0 0x01f8 437 #define RK3366_FRC_LOWER11_1 0x01fc 438 #define RK3366_INTR_EN0 0x0280 439 #define RK3366_INTR_CLEAR0 0x0284 440 #define RK3366_INTR_STATUS0 0x0288 441 #define RK3366_INTR_RAW_STATUS0 0x028c 442 #define RK3366_INTR_EN1 0x0290 443 #define RK3366_INTR_CLEAR1 0x0294 444 #define RK3366_INTR_STATUS1 0x0298 445 #define RK3366_INTR_RAW_STATUS1 0x029c 446 #define RK3366_LINE_FLAG 0x02a0 447 #define RK3366_VOP_STATUS 0x02a4 448 #define RK3366_BLANKING_VALUE 0x02a8 449 #define RK3366_WIN0_DSP_BG 0x02b0 450 #define RK3366_WIN1_DSP_BG 0x02b4 451 #define RK3366_WIN2_DSP_BG 0x02b8 452 #define RK3366_WIN3_DSP_BG 0x02bc 453 #define RK3366_WIN2_LUT_ADDR 0x0400 454 #define RK3366_WIN3_LUT_ADDR 0x0800 455 #define RK3366_HWC_LUT_ADDR 0x0c00 456 #define RK3366_GAMMA0_LUT_ADDR 0x1000 457 #define RK3366_GAMMA1_LUT_ADDR 0x1400 458 #define RK3366_CABC_GAMMA_LUT_ADDR 0x1800 459 #define RK3366_MCU_BYPASS_WPORT 0x2200 460 #define RK3366_MCU_BYPASS_RPORT 0x2300 461 #define RK3366_MMU_DTE_ADDR 0x2400 462 #define RK3366_MMU_STATUS 0x2404 463 #define RK3366_MMU_COMMAND 0x2408 464 #define RK3366_MMU_PAGE_FAULT_ADDR 0x240c 465 #define RK3366_MMU_ZAP_ONE_LINE 0x2410 466 #define RK3366_MMU_INT_RAWSTAT 0x2414 467 #define RK3366_MMU_INT_CLEAR 0x2418 468 #define RK3366_MMU_INT_MASK 0x241c 469 #define RK3366_MMU_INT_STATUS 0x2420 470 #define RK3366_MMU_AUTO_GATING 0x2424 471 472 /* rk3399 register definition */ 473 #define RK3399_REG_CFG_DONE 0x0000 474 #define RK3399_VERSION_INFO 0x0004 475 #define RK3399_SYS_CTRL 0x0008 476 #define RK3399_SYS_CTRL1 0x000c 477 #define RK3399_DSP_CTRL0 0x0010 478 #define RK3399_DSP_CTRL1 0x0014 479 #define RK3399_DSP_BG 0x0018 480 #define RK3399_MCU_CTRL 0x001c 481 #define RK3399_WB_CTRL0 0x0020 482 #define RK3399_WB_CTRL1 0x0024 483 #define RK3399_WB_YRGB_MST 0x0028 484 #define RK3399_WB_CBR_MST 0x002c 485 #define RK3399_WIN0_CTRL0 0x0030 486 #define RK3399_WIN0_CTRL1 0x0034 487 #define RK3399_WIN0_COLOR_KEY 0x0038 488 #define RK3399_WIN0_VIR 0x003c 489 #define RK3399_WIN0_YRGB_MST 0x0040 490 #define RK3399_WIN0_CBR_MST 0x0044 491 #define RK3399_WIN0_ACT_INFO 0x0048 492 #define RK3399_WIN0_DSP_INFO 0x004c 493 #define RK3399_WIN0_DSP_ST 0x0050 494 #define RK3399_WIN0_SCL_FACTOR_YRGB 0x0054 495 #define RK3399_WIN0_SCL_FACTOR_CBR 0x0058 496 #define RK3399_WIN0_SCL_OFFSET 0x005c 497 #define RK3399_WIN0_SRC_ALPHA_CTRL 0x0060 498 #define RK3399_WIN0_DST_ALPHA_CTRL 0x0064 499 #define RK3399_WIN0_FADING_CTRL 0x0068 500 #define RK3399_WIN0_CTRL2 0x006c 501 #define RK3399_WIN1_CTRL0 0x0070 502 #define RK3399_WIN1_CTRL1 0x0074 503 #define RK3399_WIN1_COLOR_KEY 0x0078 504 #define RK3399_WIN1_VIR 0x007c 505 #define RK3399_WIN1_YRGB_MST 0x0080 506 #define RK3399_WIN1_CBR_MST 0x0084 507 #define RK3399_WIN1_ACT_INFO 0x0088 508 #define RK3399_WIN1_DSP_INFO 0x008c 509 #define RK3399_WIN1_DSP_ST 0x0090 510 #define RK3399_WIN1_SCL_FACTOR_YRGB 0x0094 511 #define RK3399_WIN1_SCL_FACTOR_CBR 0x0098 512 #define RK3399_WIN1_SCL_OFFSET 0x009c 513 #define RK3399_WIN1_SRC_ALPHA_CTRL 0x00a0 514 #define RK3399_WIN1_DST_ALPHA_CTRL 0x00a4 515 #define RK3399_WIN1_FADING_CTRL 0x00a8 516 #define RK3399_WIN1_CTRL2 0x00ac 517 #define RK3399_WIN2_CTRL0 0x00b0 518 #define RK3399_WIN2_CTRL1 0x00b4 519 #define RK3399_WIN2_VIR0_1 0x00b8 520 #define RK3399_WIN2_VIR2_3 0x00bc 521 #define RK3399_WIN2_MST0 0x00c0 522 #define RK3399_WIN2_DSP_INFO0 0x00c4 523 #define RK3399_WIN2_DSP_ST0 0x00c8 524 #define RK3399_WIN2_COLOR_KEY 0x00cc 525 #define RK3399_WIN2_MST1 0x00d0 526 #define RK3399_WIN2_DSP_INFO1 0x00d4 527 #define RK3399_WIN2_DSP_ST1 0x00d8 528 #define RK3399_WIN2_SRC_ALPHA_CTRL 0x00dc 529 #define RK3399_WIN2_MST2 0x00e0 530 #define RK3399_WIN2_DSP_INFO2 0x00e4 531 #define RK3399_WIN2_DSP_ST2 0x00e8 532 #define RK3399_WIN2_DST_ALPHA_CTRL 0x00ec 533 #define RK3399_WIN2_MST3 0x00f0 534 #define RK3399_WIN2_DSP_INFO3 0x00f4 535 #define RK3399_WIN2_DSP_ST3 0x00f8 536 #define RK3399_WIN2_FADING_CTRL 0x00fc 537 #define RK3399_WIN3_CTRL0 0x0100 538 #define RK3399_WIN3_CTRL1 0x0104 539 #define RK3399_WIN3_VIR0_1 0x0108 540 #define RK3399_WIN3_VIR2_3 0x010c 541 #define RK3399_WIN3_MST0 0x0110 542 #define RK3399_WIN3_DSP_INFO0 0x0114 543 #define RK3399_WIN3_DSP_ST0 0x0118 544 #define RK3399_WIN3_COLOR_KEY 0x011c 545 #define RK3399_WIN3_MST1 0x0120 546 #define RK3399_WIN3_DSP_INFO1 0x0124 547 #define RK3399_WIN3_DSP_ST1 0x0128 548 #define RK3399_WIN3_SRC_ALPHA_CTRL 0x012c 549 #define RK3399_WIN3_MST2 0x0130 550 #define RK3399_WIN3_DSP_INFO2 0x0134 551 #define RK3399_WIN3_DSP_ST2 0x0138 552 #define RK3399_WIN3_DST_ALPHA_CTRL 0x013c 553 #define RK3399_WIN3_MST3 0x0140 554 #define RK3399_WIN3_DSP_INFO3 0x0144 555 #define RK3399_WIN3_DSP_ST3 0x0148 556 #define RK3399_WIN3_FADING_CTRL 0x014c 557 #define RK3399_HWC_CTRL0 0x0150 558 #define RK3399_HWC_CTRL1 0x0154 559 #define RK3399_HWC_MST 0x0158 560 #define RK3399_HWC_DSP_ST 0x015c 561 #define RK3399_HWC_SRC_ALPHA_CTRL 0x0160 562 #define RK3399_HWC_DST_ALPHA_CTRL 0x0164 563 #define RK3399_HWC_FADING_CTRL 0x0168 564 #define RK3399_HWC_RESERVED1 0x016c 565 #define RK3399_POST_DSP_HACT_INFO 0x0170 566 #define RK3399_POST_DSP_VACT_INFO 0x0174 567 #define RK3399_POST_SCL_FACTOR_YRGB 0x0178 568 #define RK3399_POST_RESERVED 0x017c 569 #define RK3399_POST_SCL_CTRL 0x0180 570 #define RK3399_POST_DSP_VACT_INFO_F1 0x0184 571 #define RK3399_DSP_HTOTAL_HS_END 0x0188 572 #define RK3399_DSP_HACT_ST_END 0x018c 573 #define RK3399_DSP_VTOTAL_VS_END 0x0190 574 #define RK3399_DSP_VACT_ST_END 0x0194 575 #define RK3399_DSP_VS_ST_END_F1 0x0198 576 #define RK3399_DSP_VACT_ST_END_F1 0x019c 577 #define RK3399_PWM_CTRL 0x01a0 578 #define RK3399_PWM_PERIOD_HPR 0x01a4 579 #define RK3399_PWM_DUTY_LPR 0x01a8 580 #define RK3399_PWM_CNT 0x01ac 581 #define RK3399_BCSH_COLOR_BAR 0x01b0 582 #define RK3399_BCSH_BCS 0x01b4 583 #define RK3399_BCSH_H 0x01b8 584 #define RK3399_BCSH_CTRL 0x01bc 585 #define RK3399_CABC_CTRL0 0x01c0 586 #define RK3399_CABC_CTRL1 0x01c4 587 #define RK3399_CABC_CTRL2 0x01c8 588 #define RK3399_CABC_CTRL3 0x01cc 589 #define RK3399_CABC_GAUSS_LINE0_0 0x01d0 590 #define RK3399_CABC_GAUSS_LINE0_1 0x01d4 591 #define RK3399_CABC_GAUSS_LINE1_0 0x01d8 592 #define RK3399_CABC_GAUSS_LINE1_1 0x01dc 593 #define RK3399_CABC_GAUSS_LINE2_0 0x01e0 594 #define RK3399_CABC_GAUSS_LINE2_1 0x01e4 595 #define RK3399_FRC_LOWER01_0 0x01e8 596 #define RK3399_FRC_LOWER01_1 0x01ec 597 #define RK3399_FRC_LOWER10_0 0x01f0 598 #define RK3399_FRC_LOWER10_1 0x01f4 599 #define RK3399_FRC_LOWER11_0 0x01f8 600 #define RK3399_FRC_LOWER11_1 0x01fc 601 #define RK3399_AFBCD0_CTRL 0x0200 602 #define RK3399_AFBCD0_HDR_PTR 0x0204 603 #define RK3399_AFBCD0_PIC_SIZE 0x0208 604 #define RK3399_AFBCD0_STATUS 0x020c 605 #define RK3399_AFBCD1_CTRL 0x0220 606 #define RK3399_AFBCD1_HDR_PTR 0x0224 607 #define RK3399_AFBCD1_PIC_SIZE 0x0228 608 #define RK3399_AFBCD1_STATUS 0x022c 609 #define RK3399_AFBCD2_CTRL 0x0240 610 #define RK3399_AFBCD2_HDR_PTR 0x0244 611 #define RK3399_AFBCD2_PIC_SIZE 0x0248 612 #define RK3399_AFBCD2_STATUS 0x024c 613 #define RK3399_AFBCD3_CTRL 0x0260 614 #define RK3399_AFBCD3_HDR_PTR 0x0264 615 #define RK3399_AFBCD3_PIC_SIZE 0x0268 616 #define RK3399_AFBCD3_STATUS 0x026c 617 #define RK3399_INTR_EN0 0x0280 618 #define RK3399_INTR_CLEAR0 0x0284 619 #define RK3399_INTR_STATUS0 0x0288 620 #define RK3399_INTR_RAW_STATUS0 0x028c 621 #define RK3399_INTR_EN1 0x0290 622 #define RK3399_INTR_CLEAR1 0x0294 623 #define RK3399_INTR_STATUS1 0x0298 624 #define RK3399_INTR_RAW_STATUS1 0x029c 625 #define RK3399_LINE_FLAG 0x02a0 626 #define RK3399_VOP_STATUS 0x02a4 627 #define RK3399_BLANKING_VALUE 0x02a8 628 #define RK3399_MCU_BYPASS_PORT 0x02ac 629 #define RK3399_WIN0_DSP_BG 0x02b0 630 #define RK3399_WIN1_DSP_BG 0x02b4 631 #define RK3399_WIN2_DSP_BG 0x02b8 632 #define RK3399_WIN3_DSP_BG 0x02bc 633 #define RK3399_YUV2YUV_WIN 0x02c0 634 #define RK3399_YUV2YUV_POST 0x02c4 635 #define RK3399_AUTO_GATING_EN 0x02cc 636 #define RK3399_WIN0_CSC_COE 0x03a0 637 #define RK3399_WIN1_CSC_COE 0x03c0 638 #define RK3399_WIN2_CSC_COE 0x03e0 639 #define RK3399_WIN3_CSC_COE 0x0400 640 #define RK3399_HWC_CSC_COE 0x0420 641 #define RK3399_BCSH_R2Y_CSC_COE 0x0440 642 #define RK3399_BCSH_Y2R_CSC_COE 0x0460 643 #define RK3399_POST_YUV2YUV_Y2R_COE 0x0480 644 #define RK3399_POST_YUV2YUV_3X3_COE 0x04a0 645 #define RK3399_POST_YUV2YUV_R2Y_COE 0x04c0 646 #define RK3399_WIN0_YUV2YUV_Y2R 0x04e0 647 #define RK3399_WIN0_YUV2YUV_3X3 0x0500 648 #define RK3399_WIN0_YUV2YUV_R2Y 0x0520 649 #define RK3399_WIN1_YUV2YUV_Y2R 0x0540 650 #define RK3399_WIN1_YUV2YUV_3X3 0x0560 651 #define RK3399_WIN1_YUV2YUV_R2Y 0x0580 652 #define RK3399_WIN2_YUV2YUV_Y2R 0x05a0 653 #define RK3399_WIN2_YUV2YUV_3X3 0x05c0 654 #define RK3399_WIN2_YUV2YUV_R2Y 0x05e0 655 #define RK3399_WIN3_YUV2YUV_Y2R 0x0600 656 #define RK3399_WIN3_YUV2YUV_3X3 0x0620 657 #define RK3399_WIN3_YUV2YUV_R2Y 0x0640 658 #define RK3399_WIN2_LUT_ADDR 0x1000 659 #define RK3399_WIN3_LUT_ADDR 0x1400 660 #define RK3399_HWC_LUT_ADDR 0x1800 661 #define RK3399_CABC_GAMMA_LUT_ADDR 0x1c00 662 #define RK3399_GAMMA_LUT_ADDR 0x2000 663 /* rk3399 register definition end */ 664 665 /* rk3328 register definition end */ 666 #define RK3328_REG_CFG_DONE 0x00000000 667 #define RK3328_VERSION_INFO 0x00000004 668 #define RK3328_SYS_CTRL 0x00000008 669 #define RK3328_SYS_CTRL1 0x0000000c 670 #define RK3328_DSP_CTRL0 0x00000010 671 #define RK3328_DSP_CTRL1 0x00000014 672 #define RK3328_DSP_BG 0x00000018 673 #define RK3328_AUTO_GATING_EN 0x0000003c 674 #define RK3328_LINE_FLAG 0x00000040 675 #define RK3328_VOP_STATUS 0x00000044 676 #define RK3328_BLANKING_VALUE 0x00000048 677 #define RK3328_WIN0_DSP_BG 0x00000050 678 #define RK3328_WIN1_DSP_BG 0x00000054 679 #define RK3328_DBG_PERF_LATENCY_CTRL0 0x000000c0 680 #define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0 0x000000c4 681 #define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0 0x000000c8 682 #define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0 0x000000cc 683 #define RK3328_INTR_EN0 0x000000e0 684 #define RK3328_INTR_CLEAR0 0x000000e4 685 #define RK3328_INTR_STATUS0 0x000000e8 686 #define RK3328_INTR_RAW_STATUS0 0x000000ec 687 #define RK3328_INTR_EN1 0x000000f0 688 #define RK3328_INTR_CLEAR1 0x000000f4 689 #define RK3328_INTR_STATUS1 0x000000f8 690 #define RK3328_INTR_RAW_STATUS1 0x000000fc 691 #define RK3328_WIN0_CTRL0 0x00000100 692 #define RK3328_WIN0_CTRL1 0x00000104 693 #define RK3328_WIN0_COLOR_KEY 0x00000108 694 #define RK3328_WIN0_VIR 0x0000010c 695 #define RK3328_WIN0_YRGB_MST 0x00000110 696 #define RK3328_WIN0_CBR_MST 0x00000114 697 #define RK3328_WIN0_ACT_INFO 0x00000118 698 #define RK3328_WIN0_DSP_INFO 0x0000011c 699 #define RK3328_WIN0_DSP_ST 0x00000120 700 #define RK3328_WIN0_SCL_FACTOR_YRGB 0x00000124 701 #define RK3328_WIN0_SCL_FACTOR_CBR 0x00000128 702 #define RK3328_WIN0_SCL_OFFSET 0x0000012c 703 #define RK3328_WIN0_SRC_ALPHA_CTRL 0x00000130 704 #define RK3328_WIN0_DST_ALPHA_CTRL 0x00000134 705 #define RK3328_WIN0_FADING_CTRL 0x00000138 706 #define RK3328_WIN0_CTRL2 0x0000013c 707 #define RK3328_DBG_WIN0_REG0 0x000001f0 708 #define RK3328_DBG_WIN0_REG1 0x000001f4 709 #define RK3328_DBG_WIN0_REG2 0x000001f8 710 #define RK3328_DBG_WIN0_RESERVED 0x000001fc 711 #define RK3328_WIN1_CTRL0 0x00000200 712 #define RK3328_WIN1_CTRL1 0x00000204 713 #define RK3328_WIN1_COLOR_KEY 0x00000208 714 #define RK3328_WIN1_VIR 0x0000020c 715 #define RK3328_WIN1_YRGB_MST 0x00000210 716 #define RK3328_WIN1_CBR_MST 0x00000214 717 #define RK3328_WIN1_ACT_INFO 0x00000218 718 #define RK3328_WIN1_DSP_INFO 0x0000021c 719 #define RK3328_WIN1_DSP_ST 0x00000220 720 #define RK3328_WIN1_SCL_FACTOR_YRGB 0x00000224 721 #define RK3328_WIN1_SCL_FACTOR_CBR 0x00000228 722 #define RK3328_WIN1_SCL_OFFSET 0x0000022c 723 #define RK3328_WIN1_SRC_ALPHA_CTRL 0x00000230 724 #define RK3328_WIN1_DST_ALPHA_CTRL 0x00000234 725 #define RK3328_WIN1_FADING_CTRL 0x00000238 726 #define RK3328_WIN1_CTRL2 0x0000023c 727 #define RK3328_DBG_WIN1_REG0 0x000002f0 728 #define RK3328_DBG_WIN1_REG1 0x000002f4 729 #define RK3328_DBG_WIN1_REG2 0x000002f8 730 #define RK3328_DBG_WIN1_RESERVED 0x000002fc 731 #define RK3328_WIN2_CTRL0 0x00000300 732 #define RK3328_WIN2_CTRL1 0x00000304 733 #define RK3328_WIN2_COLOR_KEY 0x00000308 734 #define RK3328_WIN2_VIR 0x0000030c 735 #define RK3328_WIN2_YRGB_MST 0x00000310 736 #define RK3328_WIN2_CBR_MST 0x00000314 737 #define RK3328_WIN2_ACT_INFO 0x00000318 738 #define RK3328_WIN2_DSP_INFO 0x0000031c 739 #define RK3328_WIN2_DSP_ST 0x00000320 740 #define RK3328_WIN2_SCL_FACTOR_YRGB 0x00000324 741 #define RK3328_WIN2_SCL_FACTOR_CBR 0x00000328 742 #define RK3328_WIN2_SCL_OFFSET 0x0000032c 743 #define RK3328_WIN2_SRC_ALPHA_CTRL 0x00000330 744 #define RK3328_WIN2_DST_ALPHA_CTRL 0x00000334 745 #define RK3328_WIN2_FADING_CTRL 0x00000338 746 #define RK3328_WIN2_CTRL2 0x0000033c 747 #define RK3328_DBG_WIN2_REG0 0x000003f0 748 #define RK3328_DBG_WIN2_REG1 0x000003f4 749 #define RK3328_DBG_WIN2_REG2 0x000003f8 750 #define RK3328_DBG_WIN2_RESERVED 0x000003fc 751 #define RK3328_WIN3_CTRL0 0x00000400 752 #define RK3328_WIN3_CTRL1 0x00000404 753 #define RK3328_WIN3_COLOR_KEY 0x00000408 754 #define RK3328_WIN3_VIR 0x0000040c 755 #define RK3328_WIN3_YRGB_MST 0x00000410 756 #define RK3328_WIN3_CBR_MST 0x00000414 757 #define RK3328_WIN3_ACT_INFO 0x00000418 758 #define RK3328_WIN3_DSP_INFO 0x0000041c 759 #define RK3328_WIN3_DSP_ST 0x00000420 760 #define RK3328_WIN3_SCL_FACTOR_YRGB 0x00000424 761 #define RK3328_WIN3_SCL_FACTOR_CBR 0x00000428 762 #define RK3328_WIN3_SCL_OFFSET 0x0000042c 763 #define RK3328_WIN3_SRC_ALPHA_CTRL 0x00000430 764 #define RK3328_WIN3_DST_ALPHA_CTRL 0x00000434 765 #define RK3328_WIN3_FADING_CTRL 0x00000438 766 #define RK3328_WIN3_CTRL2 0x0000043c 767 #define RK3328_DBG_WIN3_REG0 0x000004f0 768 #define RK3328_DBG_WIN3_REG1 0x000004f4 769 #define RK3328_DBG_WIN3_REG2 0x000004f8 770 #define RK3328_DBG_WIN3_RESERVED 0x000004fc 771 772 #define RK3328_HWC_CTRL0 0x00000500 773 #define RK3328_HWC_CTRL1 0x00000504 774 #define RK3328_HWC_MST 0x00000508 775 #define RK3328_HWC_DSP_ST 0x0000050c 776 #define RK3328_HWC_SRC_ALPHA_CTRL 0x00000510 777 #define RK3328_HWC_DST_ALPHA_CTRL 0x00000514 778 #define RK3328_HWC_FADING_CTRL 0x00000518 779 #define RK3328_HWC_RESERVED1 0x0000051c 780 #define RK3328_POST_DSP_HACT_INFO 0x00000600 781 #define RK3328_POST_DSP_VACT_INFO 0x00000604 782 #define RK3328_POST_SCL_FACTOR_YRGB 0x00000608 783 #define RK3328_POST_RESERVED 0x0000060c 784 #define RK3328_POST_SCL_CTRL 0x00000610 785 #define RK3328_POST_DSP_VACT_INFO_F1 0x00000614 786 #define RK3328_DSP_HTOTAL_HS_END 0x00000618 787 #define RK3328_DSP_HACT_ST_END 0x0000061c 788 #define RK3328_DSP_VTOTAL_VS_END 0x00000620 789 #define RK3328_DSP_VACT_ST_END 0x00000624 790 #define RK3328_DSP_VS_ST_END_F1 0x00000628 791 #define RK3328_DSP_VACT_ST_END_F1 0x0000062c 792 #define RK3328_BCSH_COLOR_BAR 0x00000640 793 #define RK3328_BCSH_BCS 0x00000644 794 #define RK3328_BCSH_H 0x00000648 795 #define RK3328_BCSH_CTRL 0x0000064c 796 #define RK3328_FRC_LOWER01_0 0x00000678 797 #define RK3328_FRC_LOWER01_1 0x0000067c 798 #define RK3328_FRC_LOWER10_0 0x00000680 799 #define RK3328_FRC_LOWER10_1 0x00000684 800 #define RK3328_FRC_LOWER11_0 0x00000688 801 #define RK3328_FRC_LOWER11_1 0x0000068c 802 #define RK3328_DBG_POST_REG0 0x000006e8 803 #define RK3328_DBG_POST_RESERVED 0x000006ec 804 #define RK3328_DBG_DATAO 0x000006f0 805 #define RK3328_DBG_DATAO_2 0x000006f4 806 807 /* sdr to hdr */ 808 #define RK3328_SDR2HDR_CTRL 0x00000700 809 #define RK3328_EOTF_OETF_Y0 0x00000704 810 #define RK3328_RESERVED0001 0x00000708 811 #define RK3328_RESERVED0002 0x0000070c 812 #define RK3328_EOTF_OETF_Y1 0x00000710 813 #define RK3328_EOTF_OETF_Y64 0x0000080c 814 #define RK3328_OETF_DX_DXPOW1 0x00000810 815 #define RK3328_OETF_DX_DXPOW64 0x0000090c 816 #define RK3328_OETF_XN1 0x00000910 817 #define RK3328_OETF_XN63 0x00000a08 818 819 /* hdr to sdr */ 820 #define RK3328_HDR2SDR_CTRL 0x00000a10 821 #define RK3328_HDR2SDR_SRC_RANGE 0x00000a14 822 #define RK3328_HDR2SDR_NORMFACEETF 0x00000a18 823 #define RK3328_RESERVED0003 0x00000a1c 824 #define RK3328_HDR2SDR_DST_RANGE 0x00000a20 825 #define RK3328_HDR2SDR_NORMFACCGAMMA 0x00000a24 826 #define RK3328_EETF_OETF_Y0 0x00000a28 827 #define RK3328_SAT_Y0 0x00000a2c 828 #define RK3328_EETF_OETF_Y1 0x00000a30 829 #define RK3328_SAT_Y1 0x00000ab0 830 #define RK3328_SAT_Y8 0x00000acc 831 832 #define RK3328_HWC_LUT_ADDR 0x00000c00 833 834 /* rk3036 register definition */ 835 #define RK3036_SYS_CTRL 0x00 836 #define RK3036_DSP_CTRL0 0x04 837 #define RK3036_DSP_CTRL1 0x08 838 #define RK3036_INT_SCALER 0x0c 839 #define RK3036_INT_STATUS 0x10 840 #define RK3036_ALPHA_CTRL 0x14 841 #define RK3036_WIN0_COLOR_KEY 0x18 842 #define RK3036_WIN1_COLOR_KEY 0x1c 843 #define RK3036_WIN0_YRGB_MST 0x20 844 #define RK3036_WIN0_CBR_MST 0x24 845 #define RK3036_WIN1_VIR 0x28 846 #define RK3036_AXI_BUS_CTRL 0x2c 847 #define RK3036_WIN0_VIR 0x30 848 #define RK3036_WIN0_ACT_INFO 0x34 849 #define RK3036_WIN0_DSP_INFO 0x38 850 #define RK3036_WIN0_DSP_ST 0x3c 851 #define RK3036_WIN0_SCL_FACTOR_YRGB 0x40 852 #define RK3036_WIN0_SCL_FACTOR_CBR 0x44 853 #define RK3036_WIN0_SCL_OFFSET 0x48 854 #define RK3036_HWC_MST 0x58 855 #define RK3036_HWC_DSP_ST 0x5c 856 #define RK3036_DSP_HTOTAL_HS_END 0x6c 857 #define RK3036_DSP_HACT_ST_END 0x70 858 #define RK3036_DSP_VTOTAL_VS_END 0x74 859 #define RK3036_DSP_VACT_ST_END 0x78 860 #define RK3036_DSP_VS_ST_END_F1 0x7c 861 #define RK3036_DSP_VACT_ST_END_F1 0x80 862 #define RK3036_GATHER_TRANSFER 0x84 863 #define RK3036_VERSION_INFO 0x94 864 #define RK3036_REG_CFG_DONE 0x90 865 #define RK3036_WIN1_MST 0xa0 866 #define RK3036_WIN1_ACT_INFO 0xb4 867 #define RK3036_WIN1_DSP_INFO 0xb8 868 #define RK3036_WIN1_DSP_ST 0xbc 869 #define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0 870 #define RK3036_WIN1_SCL_OFFSET 0xc8 871 #define RK3036_BCSH_CTRL 0xd0 872 #define RK3036_BCSH_COLOR_BAR 0xd4 873 #define RK3036_BCSH_BCS 0xd8 874 #define RK3036_BCSH_H 0xdc 875 #define RK3036_WIN1_LUT_ADDR 0x400 876 #define RK3036_HWC_LUT_ADDR 0x800 877 /* rk3036 register definition end */ 878 879 /* rk3366 register definition */ 880 #define RK3366_LIT_REG_CFG_DONE 0x00000 881 #define RK3366_LIT_VERSION 0x00004 882 #define RK3366_LIT_DSP_BG 0x00008 883 #define RK3366_LIT_MCU_CTRL 0x0000c 884 #define RK3366_LIT_SYS_CTRL0 0x00010 885 #define RK3366_LIT_SYS_CTRL1 0x00014 886 #define RK3366_LIT_SYS_CTRL2 0x00018 887 #define RK3366_LIT_DSP_CTRL0 0x00020 888 #define RK3366_LIT_DSP_CTRL2 0x00028 889 #define RK3366_LIT_VOP_STATUS 0x0002c 890 #define RK3366_LIT_LINE_FLAG 0x00030 891 #define RK3366_LIT_INTR_EN 0x00034 892 #define RK3366_LIT_INTR_CLEAR 0x00038 893 #define RK3366_LIT_INTR_STATUS 0x0003c 894 #define RK3366_LIT_WIN0_CTRL0 0x00050 895 #define RK3366_LIT_WIN0_CTRL1 0x00054 896 #define RK3366_LIT_WIN0_COLOR_KEY 0x00058 897 #define RK3366_LIT_WIN0_VIR 0x0005c 898 #define RK3366_LIT_WIN0_YRGB_MST0 0x00060 899 #define RK3366_LIT_WIN0_CBR_MST0 0x00064 900 #define RK3366_LIT_WIN0_ACT_INFO 0x00068 901 #define RK3366_LIT_WIN0_DSP_INFO 0x0006c 902 #define RK3366_LIT_WIN0_DSP_ST 0x00070 903 #define RK3366_LIT_WIN0_SCL_FACTOR_YRGB 0x00074 904 #define RK3366_LIT_WIN0_SCL_FACTOR_CBR 0x00078 905 #define RK3366_LIT_WIN0_SCL_OFFSET 0x0007c 906 #define RK3366_LIT_WIN0_ALPHA_CTRL 0x00080 907 #define RK3366_LIT_WIN1_CTRL0 0x00090 908 #define RK3366_LIT_WIN1_CTRL1 0x00094 909 #define RK3366_LIT_WIN1_VIR 0x00098 910 #define RK3366_LIT_WIN1_MST 0x000a0 911 #define RK3366_LIT_WIN1_DSP_INFO 0x000a4 912 #define RK3366_LIT_WIN1_DSP_ST 0x000a8 913 #define RK3366_LIT_WIN1_COLOR_KEY 0x000ac 914 #define RK3366_LIT_WIN1_ALPHA_CTRL 0x000bc 915 #define RK3366_LIT_HWC_CTRL0 0x000e0 916 #define RK3366_LIT_HWC_CTRL1 0x000e4 917 #define RK3366_LIT_HWC_MST 0x000e8 918 #define RK3366_LIT_HWC_DSP_ST 0x000ec 919 #define RK3366_LIT_HWC_ALPHA_CTRL 0x000f0 920 #define RK3366_LIT_DSP_HTOTAL_HS_END 0x00100 921 #define RK3366_LIT_DSP_HACT_ST_END 0x00104 922 #define RK3366_LIT_DSP_VTOTAL_VS_END 0x00108 923 #define RK3366_LIT_DSP_VACT_ST_END 0x0010c 924 #define RK3366_LIT_DSP_VS_ST_END_F1 0x00110 925 #define RK3366_LIT_DSP_VACT_ST_END_F1 0x00114 926 #define RK3366_LIT_BCSH_CTRL 0x00160 927 #define RK3366_LIT_BCSH_COL_BAR 0x00164 928 #define RK3366_LIT_BCSH_BCS 0x00168 929 #define RK3366_LIT_BCSH_H 0x0016c 930 #define RK3366_LIT_FRC_LOWER01_0 0x00170 931 #define RK3366_LIT_FRC_LOWER01_1 0x00174 932 #define RK3366_LIT_FRC_LOWER10_0 0x00178 933 #define RK3366_LIT_FRC_LOWER10_1 0x0017c 934 #define RK3366_LIT_FRC_LOWER11_0 0x00180 935 #define RK3366_LIT_FRC_LOWER11_1 0x00184 936 #define RK3366_LIT_MCU_RW_BYPASS_PORT 0x0018c 937 #define RK3366_LIT_DBG_REG_000 0x00190 938 #define RK3366_LIT_BLANKING_VALUE 0x001f4 939 #define RK3366_LIT_FLAG_REG_FRM_VALID 0x001f8 940 #define RK3366_LIT_FLAG_REG 0x001fc 941 #define RK3366_LIT_HWC_LUT_ADDR 0x00600 942 #define RK3366_LIT_GAMMA_LUT_ADDR 0x00a00 943 /* rk3366 register definition end */ 944 945 /* px30 register definition */ 946 #define PX30_CABC_CTRL0 0x00200 947 #define PX30_CABC_CTRL1 0x00204 948 #define PX30_CABC_CTRL2 0x00208 949 #define PX30_CABC_CTRL3 0x0020c 950 #define PX30_CABC_GAUSS_LINE0_0 0x00210 951 #define PX30_CABC_GAUSS_LINE0_1 0x00214 952 #define PX30_CABC_GAUSS_LINE1_0 0x00218 953 #define PX30_CABC_GAUSS_LINE1_1 0x0021c 954 #define PX30_CABC_GAUSS_LINE2_0 0x00220 955 #define PX30_CABC_GAUSS_LINE2_1 0x00224 956 #define PX30_AFBCD0_CTRL 0x00240 957 #define PX30_AFBCD0_HDR_PTR 0x00244 958 #define PX30_AFBCD0_PIC_SIZE 0x00248 959 #define PX30_AFBCD0_PIC_OFFSET 0x0024c 960 #define PX30_AFBCD0_AXI_CTRL 0x00250 961 #define PX30_GRF_PD_VO_CON1 0x00438 962 /* px30 register definition end */ 963 964 /* rk1808 register definition start*/ 965 #define RK1808_GRF_PD_VO_CON1 0x00000444 966 /* rk1808 register definition end*/ 967 968 #endif /* _ROCKCHIP_VOP_REG_H */ 969