1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _ROCKCHIP_VOP_REG_H 8 #define _ROCKCHIP_VOP_REG_H 9 10 /* rk3288 register definition */ 11 #define RK3288_REG_CFG_DONE 0x0000 12 #define RK3288_VERSION_INFO 0x0004 13 #define RK3288_SYS_CTRL 0x0008 14 #define RK3288_SYS_CTRL1 0x000c 15 #define RK3288_DSP_CTRL0 0x0010 16 #define RK3288_DSP_CTRL1 0x0014 17 #define RK3288_DSP_BG 0x0018 18 #define RK3288_MCU_CTRL 0x001c 19 #define RK3288_INTR_CTRL0 0x0020 20 #define RK3288_INTR_CTRL1 0x0024 21 #define RK3288_WIN0_CTRL0 0x0030 22 #define RK3288_WIN0_CTRL1 0x0034 23 #define RK3288_WIN0_COLOR_KEY 0x0038 24 #define RK3288_WIN0_VIR 0x003c 25 #define RK3288_WIN0_YRGB_MST 0x0040 26 #define RK3288_WIN0_CBR_MST 0x0044 27 #define RK3288_WIN0_ACT_INFO 0x0048 28 #define RK3288_WIN0_DSP_INFO 0x004c 29 #define RK3288_WIN0_DSP_ST 0x0050 30 #define RK3288_WIN0_SCL_FACTOR_YRGB 0x0054 31 #define RK3288_WIN0_SCL_FACTOR_CBR 0x0058 32 #define RK3288_WIN0_SCL_OFFSET 0x005c 33 #define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060 34 #define RK3288_WIN0_DST_ALPHA_CTRL 0x0064 35 #define RK3288_WIN0_FADING_CTRL 0x0068 36 37 /* win1 register */ 38 #define RK3288_WIN1_CTRL0 0x0070 39 #define RK3288_WIN1_CTRL1 0x0074 40 #define RK3288_WIN1_COLOR_KEY 0x0078 41 #define RK3288_WIN1_VIR 0x007c 42 #define RK3288_WIN1_YRGB_MST 0x0080 43 #define RK3288_WIN1_CBR_MST 0x0084 44 #define RK3288_WIN1_ACT_INFO 0x0088 45 #define RK3288_WIN1_DSP_INFO 0x008c 46 #define RK3288_WIN1_DSP_ST 0x0090 47 #define RK3288_WIN1_SCL_FACTOR_YRGB 0x0094 48 #define RK3288_WIN1_SCL_FACTOR_CBR 0x0098 49 #define RK3288_WIN1_SCL_OFFSET 0x009c 50 #define RK3288_WIN1_SRC_ALPHA_CTRL 0x00a0 51 #define RK3288_WIN1_DST_ALPHA_CTRL 0x00a4 52 #define RK3288_WIN1_FADING_CTRL 0x00a8 53 /* win2 register */ 54 #define RK3288_WIN2_CTRL0 0x00b0 55 #define RK3288_WIN2_CTRL1 0x00b4 56 #define RK3288_WIN2_VIR0_1 0x00b8 57 #define RK3288_WIN2_VIR2_3 0x00bc 58 #define RK3288_WIN2_MST0 0x00c0 59 #define RK3288_WIN2_DSP_INFO0 0x00c4 60 #define RK3288_WIN2_DSP_ST0 0x00c8 61 #define RK3288_WIN2_COLOR_KEY 0x00cc 62 #define RK3288_WIN2_MST1 0x00d0 63 #define RK3288_WIN2_DSP_INFO1 0x00d4 64 #define RK3288_WIN2_DSP_ST1 0x00d8 65 #define RK3288_WIN2_SRC_ALPHA_CTRL 0x00dc 66 #define RK3288_WIN2_MST2 0x00e0 67 #define RK3288_WIN2_DSP_INFO2 0x00e4 68 #define RK3288_WIN2_DSP_ST2 0x00e8 69 #define RK3288_WIN2_DST_ALPHA_CTRL 0x00ec 70 #define RK3288_WIN2_MST3 0x00f0 71 #define RK3288_WIN2_DSP_INFO3 0x00f4 72 #define RK3288_WIN2_DSP_ST3 0x00f8 73 #define RK3288_WIN2_FADING_CTRL 0x00fc 74 /* win3 register */ 75 #define RK3288_WIN3_CTRL0 0x0100 76 #define RK3288_WIN3_CTRL1 0x0104 77 #define RK3288_WIN3_VIR0_1 0x0108 78 #define RK3288_WIN3_VIR2_3 0x010c 79 #define RK3288_WIN3_MST0 0x0110 80 #define RK3288_WIN3_DSP_INFO0 0x0114 81 #define RK3288_WIN3_DSP_ST0 0x0118 82 #define RK3288_WIN3_COLOR_KEY 0x011c 83 #define RK3288_WIN3_MST1 0x0120 84 #define RK3288_WIN3_DSP_INFO1 0x0124 85 #define RK3288_WIN3_DSP_ST1 0x0128 86 #define RK3288_WIN3_SRC_ALPHA_CTRL 0x012c 87 #define RK3288_WIN3_MST2 0x0130 88 #define RK3288_WIN3_DSP_INFO2 0x0134 89 #define RK3288_WIN3_DSP_ST2 0x0138 90 #define RK3288_WIN3_DST_ALPHA_CTRL 0x013c 91 #define RK3288_WIN3_MST3 0x0140 92 #define RK3288_WIN3_DSP_INFO3 0x0144 93 #define RK3288_WIN3_DSP_ST3 0x0148 94 #define RK3288_WIN3_FADING_CTRL 0x014c 95 /* hwc register */ 96 #define RK3288_HWC_CTRL0 0x0150 97 #define RK3288_HWC_CTRL1 0x0154 98 #define RK3288_HWC_MST 0x0158 99 #define RK3288_HWC_DSP_ST 0x015c 100 #define RK3288_HWC_SRC_ALPHA_CTRL 0x0160 101 #define RK3288_HWC_DST_ALPHA_CTRL 0x0164 102 #define RK3288_HWC_FADING_CTRL 0x0168 103 /* post process register */ 104 #define RK3288_POST_DSP_HACT_INFO 0x0170 105 #define RK3288_POST_DSP_VACT_INFO 0x0174 106 #define RK3288_POST_SCL_FACTOR_YRGB 0x0178 107 #define RK3288_POST_SCL_CTRL 0x0180 108 #define RK3288_POST_DSP_VACT_INFO_F1 0x0184 109 #define RK3288_DSP_HTOTAL_HS_END 0x0188 110 #define RK3288_DSP_HACT_ST_END 0x018c 111 #define RK3288_DSP_VTOTAL_VS_END 0x0190 112 #define RK3288_DSP_VACT_ST_END 0x0194 113 #define RK3288_DSP_VS_ST_END_F1 0x0198 114 #define RK3288_DSP_VACT_ST_END_F1 0x019c 115 /* register definition end */ 116 117 /* rk3368 register definition */ 118 #define RK3368_REG_CFG_DONE 0x0000 119 #define RK3368_VERSION_INFO 0x0004 120 #define RK3368_SYS_CTRL 0x0008 121 #define RK3368_SYS_CTRL1 0x000c 122 #define RK3368_DSP_CTRL0 0x0010 123 #define RK3368_DSP_CTRL1 0x0014 124 #define RK3368_DSP_BG 0x0018 125 #define RK3368_MCU_CTRL 0x001c 126 #define RK3368_LINE_FLAG 0x0020 127 #define RK3368_INTR_EN 0x0024 128 #define RK3368_INTR_CLEAR 0x0028 129 #define RK3368_INTR_STATUS 0x002c 130 #define RK3368_WIN0_CTRL0 0x0030 131 #define RK3368_WIN0_CTRL1 0x0034 132 #define RK3368_WIN0_COLOR_KEY 0x0038 133 #define RK3368_WIN0_VIR 0x003c 134 #define RK3368_WIN0_YRGB_MST 0x0040 135 #define RK3368_WIN0_CBR_MST 0x0044 136 #define RK3368_WIN0_ACT_INFO 0x0048 137 #define RK3368_WIN0_DSP_INFO 0x004c 138 #define RK3368_WIN0_DSP_ST 0x0050 139 #define RK3368_WIN0_SCL_FACTOR_YRGB 0x0054 140 #define RK3368_WIN0_SCL_FACTOR_CBR 0x0058 141 #define RK3368_WIN0_SCL_OFFSET 0x005c 142 #define RK3368_WIN0_SRC_ALPHA_CTRL 0x0060 143 #define RK3368_WIN0_DST_ALPHA_CTRL 0x0064 144 #define RK3368_WIN0_FADING_CTRL 0x0068 145 #define RK3368_WIN0_CTRL2 0x006c 146 #define RK3368_WIN1_CTRL0 0x0070 147 #define RK3368_WIN1_CTRL1 0x0074 148 #define RK3368_WIN1_COLOR_KEY 0x0078 149 #define RK3368_WIN1_VIR 0x007c 150 #define RK3368_WIN1_YRGB_MST 0x0080 151 #define RK3368_WIN1_CBR_MST 0x0084 152 #define RK3368_WIN1_ACT_INFO 0x0088 153 #define RK3368_WIN1_DSP_INFO 0x008c 154 #define RK3368_WIN1_DSP_ST 0x0090 155 #define RK3368_WIN1_SCL_FACTOR_YRGB 0x0094 156 #define RK3368_WIN1_SCL_FACTOR_CBR 0x0098 157 #define RK3368_WIN1_SCL_OFFSET 0x009c 158 #define RK3368_WIN1_SRC_ALPHA_CTRL 0x00a0 159 #define RK3368_WIN1_DST_ALPHA_CTRL 0x00a4 160 #define RK3368_WIN1_FADING_CTRL 0x00a8 161 #define RK3368_WIN1_CTRL2 0x00ac 162 #define RK3368_WIN2_CTRL0 0x00b0 163 #define RK3368_WIN2_CTRL1 0x00b4 164 #define RK3368_WIN2_VIR0_1 0x00b8 165 #define RK3368_WIN2_VIR2_3 0x00bc 166 #define RK3368_WIN2_MST0 0x00c0 167 #define RK3368_WIN2_DSP_INFO0 0x00c4 168 #define RK3368_WIN2_DSP_ST0 0x00c8 169 #define RK3368_WIN2_COLOR_KEY 0x00cc 170 #define RK3368_WIN2_MST1 0x00d0 171 #define RK3368_WIN2_DSP_INFO1 0x00d4 172 #define RK3368_WIN2_DSP_ST1 0x00d8 173 #define RK3368_WIN2_SRC_ALPHA_CTRL 0x00dc 174 #define RK3368_WIN2_MST2 0x00e0 175 #define RK3368_WIN2_DSP_INFO2 0x00e4 176 #define RK3368_WIN2_DSP_ST2 0x00e8 177 #define RK3368_WIN2_DST_ALPHA_CTRL 0x00ec 178 #define RK3368_WIN2_MST3 0x00f0 179 #define RK3368_WIN2_DSP_INFO3 0x00f4 180 #define RK3368_WIN2_DSP_ST3 0x00f8 181 #define RK3368_WIN2_FADING_CTRL 0x00fc 182 #define RK3368_WIN3_CTRL0 0x0100 183 #define RK3368_WIN3_CTRL1 0x0104 184 #define RK3368_WIN3_VIR0_1 0x0108 185 #define RK3368_WIN3_VIR2_3 0x010c 186 #define RK3368_WIN3_MST0 0x0110 187 #define RK3368_WIN3_DSP_INFO0 0x0114 188 #define RK3368_WIN3_DSP_ST0 0x0118 189 #define RK3368_WIN3_COLOR_KEY 0x011c 190 #define RK3368_WIN3_MST1 0x0120 191 #define RK3368_WIN3_DSP_INFO1 0x0124 192 #define RK3368_WIN3_DSP_ST1 0x0128 193 #define RK3368_WIN3_SRC_ALPHA_CTRL 0x012c 194 #define RK3368_WIN3_MST2 0x0130 195 #define RK3368_WIN3_DSP_INFO2 0x0134 196 #define RK3368_WIN3_DSP_ST2 0x0138 197 #define RK3368_WIN3_DST_ALPHA_CTRL 0x013c 198 #define RK3368_WIN3_MST3 0x0140 199 #define RK3368_WIN3_DSP_INFO3 0x0144 200 #define RK3368_WIN3_DSP_ST3 0x0148 201 #define RK3368_WIN3_FADING_CTRL 0x014c 202 #define RK3368_HWC_CTRL0 0x0150 203 #define RK3368_HWC_CTRL1 0x0154 204 #define RK3368_HWC_MST 0x0158 205 #define RK3368_HWC_DSP_ST 0x015c 206 #define RK3368_HWC_SRC_ALPHA_CTRL 0x0160 207 #define RK3368_HWC_DST_ALPHA_CTRL 0x0164 208 #define RK3368_HWC_FADING_CTRL 0x0168 209 #define RK3368_HWC_RESERVED1 0x016c 210 #define RK3368_POST_DSP_HACT_INFO 0x0170 211 #define RK3368_POST_DSP_VACT_INFO 0x0174 212 #define RK3368_POST_SCL_FACTOR_YRGB 0x0178 213 #define RK3368_POST_RESERVED 0x017c 214 #define RK3368_POST_SCL_CTRL 0x0180 215 #define RK3368_POST_DSP_VACT_INFO_F1 0x0184 216 #define RK3368_DSP_HTOTAL_HS_END 0x0188 217 #define RK3368_DSP_HACT_ST_END 0x018c 218 #define RK3368_DSP_VTOTAL_VS_END 0x0190 219 #define RK3368_DSP_VACT_ST_END 0x0194 220 #define RK3368_DSP_VS_ST_END_F1 0x0198 221 #define RK3368_DSP_VACT_ST_END_F1 0x019c 222 #define RK3368_PWM_CTRL 0x01a0 223 #define RK3368_PWM_PERIOD_HPR 0x01a4 224 #define RK3368_PWM_DUTY_LPR 0x01a8 225 #define RK3368_PWM_CNT 0x01ac 226 #define RK3368_BCSH_COLOR_BAR 0x01b0 227 #define RK3368_BCSH_BCS 0x01b4 228 #define RK3368_BCSH_H 0x01b8 229 #define RK3368_BCSH_CTRL 0x01bc 230 #define RK3368_CABC_CTRL0 0x01c0 231 #define RK3368_CABC_CTRL1 0x01c4 232 #define RK3368_CABC_CTRL2 0x01c8 233 #define RK3368_CABC_CTRL3 0x01cc 234 #define RK3368_CABC_GAUSS_LINE0_0 0x01d0 235 #define RK3368_CABC_GAUSS_LINE0_1 0x01d4 236 #define RK3368_CABC_GAUSS_LINE1_0 0x01d8 237 #define RK3368_CABC_GAUSS_LINE1_1 0x01dc 238 #define RK3368_CABC_GAUSS_LINE2_0 0x01e0 239 #define RK3368_CABC_GAUSS_LINE2_1 0x01e4 240 #define RK3368_FRC_LOWER01_0 0x01e8 241 #define RK3368_FRC_LOWER01_1 0x01ec 242 #define RK3368_FRC_LOWER10_0 0x01f0 243 #define RK3368_FRC_LOWER10_1 0x01f4 244 #define RK3368_FRC_LOWER11_0 0x01f8 245 #define RK3368_FRC_LOWER11_1 0x01fc 246 #define RK3368_IFBDC_CTRL 0x0200 247 #define RK3368_IFBDC_TILES_NUM 0x0204 248 #define RK3368_IFBDC_FRAME_RST_CYCLE 0x0208 249 #define RK3368_IFBDC_BASE_ADDR 0x020c 250 #define RK3368_IFBDC_MB_SIZE 0x0210 251 #define RK3368_IFBDC_CMP_INDEX_INIT 0x0214 252 #define RK3368_IFBDC_VIR 0x0220 253 #define RK3368_IFBDC_DEBUG0 0x0230 254 #define RK3368_IFBDC_DEBUG1 0x0234 255 #define RK3368_LATENCY_CTRL0 0x0250 256 #define RK3368_RD_MAX_LATENCY_NUM0 0x0254 257 #define RK3368_RD_LATENCY_THR_NUM0 0x0258 258 #define RK3368_RD_LATENCY_SAMP_NUM0 0x025c 259 #define RK3368_WIN0_DSP_BG 0x0260 260 #define RK3368_WIN1_DSP_BG 0x0264 261 #define RK3368_WIN2_DSP_BG 0x0268 262 #define RK3368_WIN3_DSP_BG 0x026c 263 #define RK3368_SCAN_LINE_NUM 0x0270 264 #define RK3368_CABC_DEBUG0 0x0274 265 #define RK3368_CABC_DEBUG1 0x0278 266 #define RK3368_CABC_DEBUG2 0x027c 267 #define RK3368_DBG_REG_000 0x0280 268 #define RK3368_DBG_REG_001 0x0284 269 #define RK3368_DBG_REG_002 0x0288 270 #define RK3368_DBG_REG_003 0x028c 271 #define RK3368_DBG_REG_004 0x0290 272 #define RK3368_DBG_REG_005 0x0294 273 #define RK3368_DBG_REG_006 0x0298 274 #define RK3368_DBG_REG_007 0x029c 275 #define RK3368_DBG_REG_008 0x02a0 276 #define RK3368_DBG_REG_016 0x02c0 277 #define RK3368_DBG_REG_017 0x02c4 278 #define RK3368_DBG_REG_018 0x02c8 279 #define RK3368_DBG_REG_019 0x02cc 280 #define RK3368_DBG_REG_020 0x02d0 281 #define RK3368_DBG_REG_021 0x02d4 282 #define RK3368_DBG_REG_022 0x02d8 283 #define RK3368_DBG_REG_023 0x02dc 284 #define RK3368_DBG_REG_028 0x02f0 285 #define RK3368_MMU_DTE_ADDR 0x0300 286 #define RK3368_MMU_STATUS 0x0304 287 #define RK3368_MMU_COMMAND 0x0308 288 #define RK3368_MMU_PAGE_FAULT_ADDR 0x030c 289 #define RK3368_MMU_ZAP_ONE_LINE 0x0310 290 #define RK3368_MMU_INT_RAWSTAT 0x0314 291 #define RK3368_MMU_INT_CLEAR 0x0318 292 #define RK3368_MMU_INT_MASK 0x031c 293 #define RK3368_MMU_INT_STATUS 0x0320 294 #define RK3368_MMU_AUTO_GATING 0x0324 295 #define RK3368_WIN2_LUT_ADDR 0x0400 296 #define RK3368_WIN3_LUT_ADDR 0x0800 297 #define RK3368_HWC_LUT_ADDR 0x0c00 298 #define RK3368_GAMMA_LUT_ADDR 0x1000 299 #define RK3368_CABC_GAMMA_LUT_ADDR 0x1800 300 #define RK3368_MCU_BYPASS_WPORT 0x2200 301 #define RK3368_MCU_BYPASS_RPORT 0x2300 302 /* rk3368 register definition end */ 303 304 #define RK3366_REG_CFG_DONE 0x0000 305 #define RK3366_VERSION_INFO 0x0004 306 #define RK3366_SYS_CTRL 0x0008 307 #define RK3366_SYS_CTRL1 0x000c 308 #define RK3366_DSP_CTRL0 0x0010 309 #define RK3366_DSP_CTRL1 0x0014 310 #define RK3366_DSP_BG 0x0018 311 #define RK3366_MCU_CTRL 0x001c 312 #define RK3366_WB_CTRL0 0x0020 313 #define RK3366_WB_CTRL1 0x0024 314 #define RK3366_WB_YRGB_MST 0x0028 315 #define RK3366_WB_CBR_MST 0x002c 316 #define RK3366_WIN0_CTRL0 0x0030 317 #define RK3366_WIN0_CTRL1 0x0034 318 #define RK3366_WIN0_COLOR_KEY 0x0038 319 #define RK3366_WIN0_VIR 0x003c 320 #define RK3366_WIN0_YRGB_MST 0x0040 321 #define RK3366_WIN0_CBR_MST 0x0044 322 #define RK3366_WIN0_ACT_INFO 0x0048 323 #define RK3366_WIN0_DSP_INFO 0x004c 324 #define RK3366_WIN0_DSP_ST 0x0050 325 #define RK3366_WIN0_SCL_FACTOR_YRGB 0x0054 326 #define RK3366_WIN0_SCL_FACTOR_CBR 0x0058 327 #define RK3366_WIN0_SCL_OFFSET 0x005c 328 #define RK3366_WIN0_SRC_ALPHA_CTRL 0x0060 329 #define RK3366_WIN0_DST_ALPHA_CTRL 0x0064 330 #define RK3366_WIN0_FADING_CTRL 0x0068 331 #define RK3366_WIN0_CTRL2 0x006c 332 #define RK3366_WIN1_CTRL0 0x0070 333 #define RK3366_WIN1_CTRL1 0x0074 334 #define RK3366_WIN1_COLOR_KEY 0x0078 335 #define RK3366_WIN1_VIR 0x007c 336 #define RK3366_WIN1_YRGB_MST 0x0080 337 #define RK3366_WIN1_CBR_MST 0x0084 338 #define RK3366_WIN1_ACT_INFO 0x0088 339 #define RK3366_WIN1_DSP_INFO 0x008c 340 #define RK3366_WIN1_DSP_ST 0x0090 341 #define RK3366_WIN1_SCL_FACTOR_YRGB 0x0094 342 #define RK3366_WIN1_SCL_FACTOR_CBR 0x0098 343 #define RK3366_WIN1_SCL_OFFSET 0x009c 344 #define RK3366_WIN1_SRC_ALPHA_CTRL 0x00a0 345 #define RK3366_WIN1_DST_ALPHA_CTRL 0x00a4 346 #define RK3366_WIN1_FADING_CTRL 0x00a8 347 #define RK3366_WIN1_CTRL2 0x00ac 348 #define RK3366_WIN2_CTRL0 0x00b0 349 #define RK3366_WIN2_CTRL1 0x00b4 350 #define RK3366_WIN2_VIR0_1 0x00b8 351 #define RK3366_WIN2_VIR2_3 0x00bc 352 #define RK3366_WIN2_MST0 0x00c0 353 #define RK3366_WIN2_DSP_INFO0 0x00c4 354 #define RK3366_WIN2_DSP_ST0 0x00c8 355 #define RK3366_WIN2_COLOR_KEY 0x00cc 356 #define RK3366_WIN2_MST1 0x00d0 357 #define RK3366_WIN2_DSP_INFO1 0x00d4 358 #define RK3366_WIN2_DSP_ST1 0x00d8 359 #define RK3366_WIN2_SRC_ALPHA_CTRL 0x00dc 360 #define RK3366_WIN2_MST2 0x00e0 361 #define RK3366_WIN2_DSP_INFO2 0x00e4 362 #define RK3366_WIN2_DSP_ST2 0x00e8 363 #define RK3366_WIN2_DST_ALPHA_CTRL 0x00ec 364 #define RK3366_WIN2_MST3 0x00f0 365 #define RK3366_WIN2_DSP_INFO3 0x00f4 366 #define RK3366_WIN2_DSP_ST3 0x00f8 367 #define RK3366_WIN2_FADING_CTRL 0x00fc 368 #define RK3366_WIN3_CTRL0 0x0100 369 #define RK3366_WIN3_CTRL1 0x0104 370 #define RK3366_WIN3_VIR0_1 0x0108 371 #define RK3366_WIN3_VIR2_3 0x010c 372 #define RK3366_WIN3_MST0 0x0110 373 #define RK3366_WIN3_DSP_INFO0 0x0114 374 #define RK3366_WIN3_DSP_ST0 0x0118 375 #define RK3366_WIN3_COLOR_KEY 0x011c 376 #define RK3366_WIN3_MST1 0x0120 377 #define RK3366_WIN3_DSP_INFO1 0x0124 378 #define RK3366_WIN3_DSP_ST1 0x0128 379 #define RK3366_WIN3_SRC_ALPHA_CTRL 0x012c 380 #define RK3366_WIN3_MST2 0x0130 381 #define RK3366_WIN3_DSP_INFO2 0x0134 382 #define RK3366_WIN3_DSP_ST2 0x0138 383 #define RK3366_WIN3_DST_ALPHA_CTRL 0x013c 384 #define RK3366_WIN3_MST3 0x0140 385 #define RK3366_WIN3_DSP_INFO3 0x0144 386 #define RK3366_WIN3_DSP_ST3 0x0148 387 #define RK3366_WIN3_FADING_CTRL 0x014c 388 #define RK3366_HWC_CTRL0 0x0150 389 #define RK3366_HWC_CTRL1 0x0154 390 #define RK3366_HWC_MST 0x0158 391 #define RK3366_HWC_DSP_ST 0x015c 392 #define RK3366_HWC_SRC_ALPHA_CTRL 0x0160 393 #define RK3366_HWC_DST_ALPHA_CTRL 0x0164 394 #define RK3366_HWC_FADING_CTRL 0x0168 395 #define RK3366_HWC_RESERVED1 0x016c 396 #define RK3366_POST_DSP_HACT_INFO 0x0170 397 #define RK3366_POST_DSP_VACT_INFO 0x0174 398 #define RK3366_POST_SCL_FACTOR_YRGB 0x0178 399 #define RK3366_POST_RESERVED 0x017c 400 #define RK3366_POST_SCL_CTRL 0x0180 401 #define RK3366_POST_DSP_VACT_INFO_F1 0x0184 402 #define RK3366_DSP_HTOTAL_HS_END 0x0188 403 #define RK3366_DSP_HACT_ST_END 0x018c 404 #define RK3366_DSP_VTOTAL_VS_END 0x0190 405 #define RK3366_DSP_VACT_ST_END 0x0194 406 #define RK3366_DSP_VS_ST_END_F1 0x0198 407 #define RK3366_DSP_VACT_ST_END_F1 0x019c 408 #define RK3366_PWM_CTRL 0x01a0 409 #define RK3366_PWM_PERIOD_HPR 0x01a4 410 #define RK3366_PWM_DUTY_LPR 0x01a8 411 #define RK3366_PWM_CNT 0x01ac 412 #define RK3366_BCSH_COLOR_BAR 0x01b0 413 #define RK3366_BCSH_BCS 0x01b4 414 #define RK3366_BCSH_H 0x01b8 415 #define RK3366_BCSH_CTRL 0x01bc 416 #define RK3366_CABC_CTRL0 0x01c0 417 #define RK3366_CABC_CTRL1 0x01c4 418 #define RK3366_CABC_CTRL2 0x01c8 419 #define RK3366_CABC_CTRL3 0x01cc 420 #define RK3366_CABC_GAUSS_LINE0_0 0x01d0 421 #define RK3366_CABC_GAUSS_LINE0_1 0x01d4 422 #define RK3366_CABC_GAUSS_LINE1_0 0x01d8 423 #define RK3366_CABC_GAUSS_LINE1_1 0x01dc 424 #define RK3366_CABC_GAUSS_LINE2_0 0x01e0 425 #define RK3366_CABC_GAUSS_LINE2_1 0x01e4 426 #define RK3366_FRC_LOWER01_0 0x01e8 427 #define RK3366_FRC_LOWER01_1 0x01ec 428 #define RK3366_FRC_LOWER10_0 0x01f0 429 #define RK3366_FRC_LOWER10_1 0x01f4 430 #define RK3366_FRC_LOWER11_0 0x01f8 431 #define RK3366_FRC_LOWER11_1 0x01fc 432 #define RK3366_INTR_EN0 0x0280 433 #define RK3366_INTR_CLEAR0 0x0284 434 #define RK3366_INTR_STATUS0 0x0288 435 #define RK3366_INTR_RAW_STATUS0 0x028c 436 #define RK3366_INTR_EN1 0x0290 437 #define RK3366_INTR_CLEAR1 0x0294 438 #define RK3366_INTR_STATUS1 0x0298 439 #define RK3366_INTR_RAW_STATUS1 0x029c 440 #define RK3366_LINE_FLAG 0x02a0 441 #define RK3366_VOP_STATUS 0x02a4 442 #define RK3366_BLANKING_VALUE 0x02a8 443 #define RK3366_WIN0_DSP_BG 0x02b0 444 #define RK3366_WIN1_DSP_BG 0x02b4 445 #define RK3366_WIN2_DSP_BG 0x02b8 446 #define RK3366_WIN3_DSP_BG 0x02bc 447 #define RK3366_WIN2_LUT_ADDR 0x0400 448 #define RK3366_WIN3_LUT_ADDR 0x0800 449 #define RK3366_HWC_LUT_ADDR 0x0c00 450 #define RK3366_GAMMA0_LUT_ADDR 0x1000 451 #define RK3366_GAMMA1_LUT_ADDR 0x1400 452 #define RK3366_CABC_GAMMA_LUT_ADDR 0x1800 453 #define RK3366_MCU_BYPASS_WPORT 0x2200 454 #define RK3366_MCU_BYPASS_RPORT 0x2300 455 #define RK3366_MMU_DTE_ADDR 0x2400 456 #define RK3366_MMU_STATUS 0x2404 457 #define RK3366_MMU_COMMAND 0x2408 458 #define RK3366_MMU_PAGE_FAULT_ADDR 0x240c 459 #define RK3366_MMU_ZAP_ONE_LINE 0x2410 460 #define RK3366_MMU_INT_RAWSTAT 0x2414 461 #define RK3366_MMU_INT_CLEAR 0x2418 462 #define RK3366_MMU_INT_MASK 0x241c 463 #define RK3366_MMU_INT_STATUS 0x2420 464 #define RK3366_MMU_AUTO_GATING 0x2424 465 466 /* rk3399 register definition */ 467 #define RK3399_REG_CFG_DONE 0x0000 468 #define RK3399_VERSION_INFO 0x0004 469 #define RK3399_SYS_CTRL 0x0008 470 #define RK3399_SYS_CTRL1 0x000c 471 #define RK3399_DSP_CTRL0 0x0010 472 #define RK3399_DSP_CTRL1 0x0014 473 #define RK3399_DSP_BG 0x0018 474 #define RK3399_MCU_CTRL 0x001c 475 #define RK3399_WB_CTRL0 0x0020 476 #define RK3399_WB_CTRL1 0x0024 477 #define RK3399_WB_YRGB_MST 0x0028 478 #define RK3399_WB_CBR_MST 0x002c 479 #define RK3399_WIN0_CTRL0 0x0030 480 #define RK3399_WIN0_CTRL1 0x0034 481 #define RK3399_WIN0_COLOR_KEY 0x0038 482 #define RK3399_WIN0_VIR 0x003c 483 #define RK3399_WIN0_YRGB_MST 0x0040 484 #define RK3399_WIN0_CBR_MST 0x0044 485 #define RK3399_WIN0_ACT_INFO 0x0048 486 #define RK3399_WIN0_DSP_INFO 0x004c 487 #define RK3399_WIN0_DSP_ST 0x0050 488 #define RK3399_WIN0_SCL_FACTOR_YRGB 0x0054 489 #define RK3399_WIN0_SCL_FACTOR_CBR 0x0058 490 #define RK3399_WIN0_SCL_OFFSET 0x005c 491 #define RK3399_WIN0_SRC_ALPHA_CTRL 0x0060 492 #define RK3399_WIN0_DST_ALPHA_CTRL 0x0064 493 #define RK3399_WIN0_FADING_CTRL 0x0068 494 #define RK3399_WIN0_CTRL2 0x006c 495 #define RK3399_WIN1_CTRL0 0x0070 496 #define RK3399_WIN1_CTRL1 0x0074 497 #define RK3399_WIN1_COLOR_KEY 0x0078 498 #define RK3399_WIN1_VIR 0x007c 499 #define RK3399_WIN1_YRGB_MST 0x0080 500 #define RK3399_WIN1_CBR_MST 0x0084 501 #define RK3399_WIN1_ACT_INFO 0x0088 502 #define RK3399_WIN1_DSP_INFO 0x008c 503 #define RK3399_WIN1_DSP_ST 0x0090 504 #define RK3399_WIN1_SCL_FACTOR_YRGB 0x0094 505 #define RK3399_WIN1_SCL_FACTOR_CBR 0x0098 506 #define RK3399_WIN1_SCL_OFFSET 0x009c 507 #define RK3399_WIN1_SRC_ALPHA_CTRL 0x00a0 508 #define RK3399_WIN1_DST_ALPHA_CTRL 0x00a4 509 #define RK3399_WIN1_FADING_CTRL 0x00a8 510 #define RK3399_WIN1_CTRL2 0x00ac 511 #define RK3399_WIN2_CTRL0 0x00b0 512 #define RK3399_WIN2_CTRL1 0x00b4 513 #define RK3399_WIN2_VIR0_1 0x00b8 514 #define RK3399_WIN2_VIR2_3 0x00bc 515 #define RK3399_WIN2_MST0 0x00c0 516 #define RK3399_WIN2_DSP_INFO0 0x00c4 517 #define RK3399_WIN2_DSP_ST0 0x00c8 518 #define RK3399_WIN2_COLOR_KEY 0x00cc 519 #define RK3399_WIN2_MST1 0x00d0 520 #define RK3399_WIN2_DSP_INFO1 0x00d4 521 #define RK3399_WIN2_DSP_ST1 0x00d8 522 #define RK3399_WIN2_SRC_ALPHA_CTRL 0x00dc 523 #define RK3399_WIN2_MST2 0x00e0 524 #define RK3399_WIN2_DSP_INFO2 0x00e4 525 #define RK3399_WIN2_DSP_ST2 0x00e8 526 #define RK3399_WIN2_DST_ALPHA_CTRL 0x00ec 527 #define RK3399_WIN2_MST3 0x00f0 528 #define RK3399_WIN2_DSP_INFO3 0x00f4 529 #define RK3399_WIN2_DSP_ST3 0x00f8 530 #define RK3399_WIN2_FADING_CTRL 0x00fc 531 #define RK3399_WIN3_CTRL0 0x0100 532 #define RK3399_WIN3_CTRL1 0x0104 533 #define RK3399_WIN3_VIR0_1 0x0108 534 #define RK3399_WIN3_VIR2_3 0x010c 535 #define RK3399_WIN3_MST0 0x0110 536 #define RK3399_WIN3_DSP_INFO0 0x0114 537 #define RK3399_WIN3_DSP_ST0 0x0118 538 #define RK3399_WIN3_COLOR_KEY 0x011c 539 #define RK3399_WIN3_MST1 0x0120 540 #define RK3399_WIN3_DSP_INFO1 0x0124 541 #define RK3399_WIN3_DSP_ST1 0x0128 542 #define RK3399_WIN3_SRC_ALPHA_CTRL 0x012c 543 #define RK3399_WIN3_MST2 0x0130 544 #define RK3399_WIN3_DSP_INFO2 0x0134 545 #define RK3399_WIN3_DSP_ST2 0x0138 546 #define RK3399_WIN3_DST_ALPHA_CTRL 0x013c 547 #define RK3399_WIN3_MST3 0x0140 548 #define RK3399_WIN3_DSP_INFO3 0x0144 549 #define RK3399_WIN3_DSP_ST3 0x0148 550 #define RK3399_WIN3_FADING_CTRL 0x014c 551 #define RK3399_HWC_CTRL0 0x0150 552 #define RK3399_HWC_CTRL1 0x0154 553 #define RK3399_HWC_MST 0x0158 554 #define RK3399_HWC_DSP_ST 0x015c 555 #define RK3399_HWC_SRC_ALPHA_CTRL 0x0160 556 #define RK3399_HWC_DST_ALPHA_CTRL 0x0164 557 #define RK3399_HWC_FADING_CTRL 0x0168 558 #define RK3399_HWC_RESERVED1 0x016c 559 #define RK3399_POST_DSP_HACT_INFO 0x0170 560 #define RK3399_POST_DSP_VACT_INFO 0x0174 561 #define RK3399_POST_SCL_FACTOR_YRGB 0x0178 562 #define RK3399_POST_RESERVED 0x017c 563 #define RK3399_POST_SCL_CTRL 0x0180 564 #define RK3399_POST_DSP_VACT_INFO_F1 0x0184 565 #define RK3399_DSP_HTOTAL_HS_END 0x0188 566 #define RK3399_DSP_HACT_ST_END 0x018c 567 #define RK3399_DSP_VTOTAL_VS_END 0x0190 568 #define RK3399_DSP_VACT_ST_END 0x0194 569 #define RK3399_DSP_VS_ST_END_F1 0x0198 570 #define RK3399_DSP_VACT_ST_END_F1 0x019c 571 #define RK3399_PWM_CTRL 0x01a0 572 #define RK3399_PWM_PERIOD_HPR 0x01a4 573 #define RK3399_PWM_DUTY_LPR 0x01a8 574 #define RK3399_PWM_CNT 0x01ac 575 #define RK3399_BCSH_COLOR_BAR 0x01b0 576 #define RK3399_BCSH_BCS 0x01b4 577 #define RK3399_BCSH_H 0x01b8 578 #define RK3399_BCSH_CTRL 0x01bc 579 #define RK3399_CABC_CTRL0 0x01c0 580 #define RK3399_CABC_CTRL1 0x01c4 581 #define RK3399_CABC_CTRL2 0x01c8 582 #define RK3399_CABC_CTRL3 0x01cc 583 #define RK3399_CABC_GAUSS_LINE0_0 0x01d0 584 #define RK3399_CABC_GAUSS_LINE0_1 0x01d4 585 #define RK3399_CABC_GAUSS_LINE1_0 0x01d8 586 #define RK3399_CABC_GAUSS_LINE1_1 0x01dc 587 #define RK3399_CABC_GAUSS_LINE2_0 0x01e0 588 #define RK3399_CABC_GAUSS_LINE2_1 0x01e4 589 #define RK3399_FRC_LOWER01_0 0x01e8 590 #define RK3399_FRC_LOWER01_1 0x01ec 591 #define RK3399_FRC_LOWER10_0 0x01f0 592 #define RK3399_FRC_LOWER10_1 0x01f4 593 #define RK3399_FRC_LOWER11_0 0x01f8 594 #define RK3399_FRC_LOWER11_1 0x01fc 595 #define RK3399_AFBCD0_CTRL 0x0200 596 #define RK3399_AFBCD0_HDR_PTR 0x0204 597 #define RK3399_AFBCD0_PIC_SIZE 0x0208 598 #define RK3399_AFBCD0_STATUS 0x020c 599 #define RK3399_AFBCD1_CTRL 0x0220 600 #define RK3399_AFBCD1_HDR_PTR 0x0224 601 #define RK3399_AFBCD1_PIC_SIZE 0x0228 602 #define RK3399_AFBCD1_STATUS 0x022c 603 #define RK3399_AFBCD2_CTRL 0x0240 604 #define RK3399_AFBCD2_HDR_PTR 0x0244 605 #define RK3399_AFBCD2_PIC_SIZE 0x0248 606 #define RK3399_AFBCD2_STATUS 0x024c 607 #define RK3399_AFBCD3_CTRL 0x0260 608 #define RK3399_AFBCD3_HDR_PTR 0x0264 609 #define RK3399_AFBCD3_PIC_SIZE 0x0268 610 #define RK3399_AFBCD3_STATUS 0x026c 611 #define RK3399_INTR_EN0 0x0280 612 #define RK3399_INTR_CLEAR0 0x0284 613 #define RK3399_INTR_STATUS0 0x0288 614 #define RK3399_INTR_RAW_STATUS0 0x028c 615 #define RK3399_INTR_EN1 0x0290 616 #define RK3399_INTR_CLEAR1 0x0294 617 #define RK3399_INTR_STATUS1 0x0298 618 #define RK3399_INTR_RAW_STATUS1 0x029c 619 #define RK3399_LINE_FLAG 0x02a0 620 #define RK3399_VOP_STATUS 0x02a4 621 #define RK3399_BLANKING_VALUE 0x02a8 622 #define RK3399_MCU_BYPASS_PORT 0x02ac 623 #define RK3399_WIN0_DSP_BG 0x02b0 624 #define RK3399_WIN1_DSP_BG 0x02b4 625 #define RK3399_WIN2_DSP_BG 0x02b8 626 #define RK3399_WIN3_DSP_BG 0x02bc 627 #define RK3399_YUV2YUV_WIN 0x02c0 628 #define RK3399_YUV2YUV_POST 0x02c4 629 #define RK3399_AUTO_GATING_EN 0x02cc 630 #define RK3399_WIN0_CSC_COE 0x03a0 631 #define RK3399_WIN1_CSC_COE 0x03c0 632 #define RK3399_WIN2_CSC_COE 0x03e0 633 #define RK3399_WIN3_CSC_COE 0x0400 634 #define RK3399_HWC_CSC_COE 0x0420 635 #define RK3399_BCSH_R2Y_CSC_COE 0x0440 636 #define RK3399_BCSH_Y2R_CSC_COE 0x0460 637 #define RK3399_POST_YUV2YUV_Y2R_COE 0x0480 638 #define RK3399_POST_YUV2YUV_3X3_COE 0x04a0 639 #define RK3399_POST_YUV2YUV_R2Y_COE 0x04c0 640 #define RK3399_WIN0_YUV2YUV_Y2R 0x04e0 641 #define RK3399_WIN0_YUV2YUV_3X3 0x0500 642 #define RK3399_WIN0_YUV2YUV_R2Y 0x0520 643 #define RK3399_WIN1_YUV2YUV_Y2R 0x0540 644 #define RK3399_WIN1_YUV2YUV_3X3 0x0560 645 #define RK3399_WIN1_YUV2YUV_R2Y 0x0580 646 #define RK3399_WIN2_YUV2YUV_Y2R 0x05a0 647 #define RK3399_WIN2_YUV2YUV_3X3 0x05c0 648 #define RK3399_WIN2_YUV2YUV_R2Y 0x05e0 649 #define RK3399_WIN3_YUV2YUV_Y2R 0x0600 650 #define RK3399_WIN3_YUV2YUV_3X3 0x0620 651 #define RK3399_WIN3_YUV2YUV_R2Y 0x0640 652 #define RK3399_WIN2_LUT_ADDR 0x1000 653 #define RK3399_WIN3_LUT_ADDR 0x1400 654 #define RK3399_HWC_LUT_ADDR 0x1800 655 #define RK3399_CABC_GAMMA_LUT_ADDR 0x1c00 656 #define RK3399_GAMMA_LUT_ADDR 0x2000 657 /* rk3399 register definition end */ 658 659 /* rk3328 register definition end */ 660 #define RK3328_REG_CFG_DONE 0x00000000 661 #define RK3328_VERSION_INFO 0x00000004 662 #define RK3328_SYS_CTRL 0x00000008 663 #define RK3328_SYS_CTRL1 0x0000000c 664 #define RK3328_DSP_CTRL0 0x00000010 665 #define RK3328_DSP_CTRL1 0x00000014 666 #define RK3328_DSP_BG 0x00000018 667 #define RK3328_AUTO_GATING_EN 0x0000003c 668 #define RK3328_LINE_FLAG 0x00000040 669 #define RK3328_VOP_STATUS 0x00000044 670 #define RK3328_BLANKING_VALUE 0x00000048 671 #define RK3328_WIN0_DSP_BG 0x00000050 672 #define RK3328_WIN1_DSP_BG 0x00000054 673 #define RK3328_DBG_PERF_LATENCY_CTRL0 0x000000c0 674 #define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0 0x000000c4 675 #define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0 0x000000c8 676 #define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0 0x000000cc 677 #define RK3328_INTR_EN0 0x000000e0 678 #define RK3328_INTR_CLEAR0 0x000000e4 679 #define RK3328_INTR_STATUS0 0x000000e8 680 #define RK3328_INTR_RAW_STATUS0 0x000000ec 681 #define RK3328_INTR_EN1 0x000000f0 682 #define RK3328_INTR_CLEAR1 0x000000f4 683 #define RK3328_INTR_STATUS1 0x000000f8 684 #define RK3328_INTR_RAW_STATUS1 0x000000fc 685 #define RK3328_WIN0_CTRL0 0x00000100 686 #define RK3328_WIN0_CTRL1 0x00000104 687 #define RK3328_WIN0_COLOR_KEY 0x00000108 688 #define RK3328_WIN0_VIR 0x0000010c 689 #define RK3328_WIN0_YRGB_MST 0x00000110 690 #define RK3328_WIN0_CBR_MST 0x00000114 691 #define RK3328_WIN0_ACT_INFO 0x00000118 692 #define RK3328_WIN0_DSP_INFO 0x0000011c 693 #define RK3328_WIN0_DSP_ST 0x00000120 694 #define RK3328_WIN0_SCL_FACTOR_YRGB 0x00000124 695 #define RK3328_WIN0_SCL_FACTOR_CBR 0x00000128 696 #define RK3328_WIN0_SCL_OFFSET 0x0000012c 697 #define RK3328_WIN0_SRC_ALPHA_CTRL 0x00000130 698 #define RK3328_WIN0_DST_ALPHA_CTRL 0x00000134 699 #define RK3328_WIN0_FADING_CTRL 0x00000138 700 #define RK3328_WIN0_CTRL2 0x0000013c 701 #define RK3328_DBG_WIN0_REG0 0x000001f0 702 #define RK3328_DBG_WIN0_REG1 0x000001f4 703 #define RK3328_DBG_WIN0_REG2 0x000001f8 704 #define RK3328_DBG_WIN0_RESERVED 0x000001fc 705 #define RK3328_WIN1_CTRL0 0x00000200 706 #define RK3328_WIN1_CTRL1 0x00000204 707 #define RK3328_WIN1_COLOR_KEY 0x00000208 708 #define RK3328_WIN1_VIR 0x0000020c 709 #define RK3328_WIN1_YRGB_MST 0x00000210 710 #define RK3328_WIN1_CBR_MST 0x00000214 711 #define RK3328_WIN1_ACT_INFO 0x00000218 712 #define RK3328_WIN1_DSP_INFO 0x0000021c 713 #define RK3328_WIN1_DSP_ST 0x00000220 714 #define RK3328_WIN1_SCL_FACTOR_YRGB 0x00000224 715 #define RK3328_WIN1_SCL_FACTOR_CBR 0x00000228 716 #define RK3328_WIN1_SCL_OFFSET 0x0000022c 717 #define RK3328_WIN1_SRC_ALPHA_CTRL 0x00000230 718 #define RK3328_WIN1_DST_ALPHA_CTRL 0x00000234 719 #define RK3328_WIN1_FADING_CTRL 0x00000238 720 #define RK3328_WIN1_CTRL2 0x0000023c 721 #define RK3328_DBG_WIN1_REG0 0x000002f0 722 #define RK3328_DBG_WIN1_REG1 0x000002f4 723 #define RK3328_DBG_WIN1_REG2 0x000002f8 724 #define RK3328_DBG_WIN1_RESERVED 0x000002fc 725 #define RK3328_WIN2_CTRL0 0x00000300 726 #define RK3328_WIN2_CTRL1 0x00000304 727 #define RK3328_WIN2_COLOR_KEY 0x00000308 728 #define RK3328_WIN2_VIR 0x0000030c 729 #define RK3328_WIN2_YRGB_MST 0x00000310 730 #define RK3328_WIN2_CBR_MST 0x00000314 731 #define RK3328_WIN2_ACT_INFO 0x00000318 732 #define RK3328_WIN2_DSP_INFO 0x0000031c 733 #define RK3328_WIN2_DSP_ST 0x00000320 734 #define RK3328_WIN2_SCL_FACTOR_YRGB 0x00000324 735 #define RK3328_WIN2_SCL_FACTOR_CBR 0x00000328 736 #define RK3328_WIN2_SCL_OFFSET 0x0000032c 737 #define RK3328_WIN2_SRC_ALPHA_CTRL 0x00000330 738 #define RK3328_WIN2_DST_ALPHA_CTRL 0x00000334 739 #define RK3328_WIN2_FADING_CTRL 0x00000338 740 #define RK3328_WIN2_CTRL2 0x0000033c 741 #define RK3328_DBG_WIN2_REG0 0x000003f0 742 #define RK3328_DBG_WIN2_REG1 0x000003f4 743 #define RK3328_DBG_WIN2_REG2 0x000003f8 744 #define RK3328_DBG_WIN2_RESERVED 0x000003fc 745 #define RK3328_WIN3_CTRL0 0x00000400 746 #define RK3328_WIN3_CTRL1 0x00000404 747 #define RK3328_WIN3_COLOR_KEY 0x00000408 748 #define RK3328_WIN3_VIR 0x0000040c 749 #define RK3328_WIN3_YRGB_MST 0x00000410 750 #define RK3328_WIN3_CBR_MST 0x00000414 751 #define RK3328_WIN3_ACT_INFO 0x00000418 752 #define RK3328_WIN3_DSP_INFO 0x0000041c 753 #define RK3328_WIN3_DSP_ST 0x00000420 754 #define RK3328_WIN3_SCL_FACTOR_YRGB 0x00000424 755 #define RK3328_WIN3_SCL_FACTOR_CBR 0x00000428 756 #define RK3328_WIN3_SCL_OFFSET 0x0000042c 757 #define RK3328_WIN3_SRC_ALPHA_CTRL 0x00000430 758 #define RK3328_WIN3_DST_ALPHA_CTRL 0x00000434 759 #define RK3328_WIN3_FADING_CTRL 0x00000438 760 #define RK3328_WIN3_CTRL2 0x0000043c 761 #define RK3328_DBG_WIN3_REG0 0x000004f0 762 #define RK3328_DBG_WIN3_REG1 0x000004f4 763 #define RK3328_DBG_WIN3_REG2 0x000004f8 764 #define RK3328_DBG_WIN3_RESERVED 0x000004fc 765 766 #define RK3328_HWC_CTRL0 0x00000500 767 #define RK3328_HWC_CTRL1 0x00000504 768 #define RK3328_HWC_MST 0x00000508 769 #define RK3328_HWC_DSP_ST 0x0000050c 770 #define RK3328_HWC_SRC_ALPHA_CTRL 0x00000510 771 #define RK3328_HWC_DST_ALPHA_CTRL 0x00000514 772 #define RK3328_HWC_FADING_CTRL 0x00000518 773 #define RK3328_HWC_RESERVED1 0x0000051c 774 #define RK3328_POST_DSP_HACT_INFO 0x00000600 775 #define RK3328_POST_DSP_VACT_INFO 0x00000604 776 #define RK3328_POST_SCL_FACTOR_YRGB 0x00000608 777 #define RK3328_POST_RESERVED 0x0000060c 778 #define RK3328_POST_SCL_CTRL 0x00000610 779 #define RK3328_POST_DSP_VACT_INFO_F1 0x00000614 780 #define RK3328_DSP_HTOTAL_HS_END 0x00000618 781 #define RK3328_DSP_HACT_ST_END 0x0000061c 782 #define RK3328_DSP_VTOTAL_VS_END 0x00000620 783 #define RK3328_DSP_VACT_ST_END 0x00000624 784 #define RK3328_DSP_VS_ST_END_F1 0x00000628 785 #define RK3328_DSP_VACT_ST_END_F1 0x0000062c 786 #define RK3328_BCSH_COLOR_BAR 0x00000640 787 #define RK3328_BCSH_BCS 0x00000644 788 #define RK3328_BCSH_H 0x00000648 789 #define RK3328_BCSH_CTRL 0x0000064c 790 #define RK3328_FRC_LOWER01_0 0x00000678 791 #define RK3328_FRC_LOWER01_1 0x0000067c 792 #define RK3328_FRC_LOWER10_0 0x00000680 793 #define RK3328_FRC_LOWER10_1 0x00000684 794 #define RK3328_FRC_LOWER11_0 0x00000688 795 #define RK3328_FRC_LOWER11_1 0x0000068c 796 #define RK3328_DBG_POST_REG0 0x000006e8 797 #define RK3328_DBG_POST_RESERVED 0x000006ec 798 #define RK3328_DBG_DATAO 0x000006f0 799 #define RK3328_DBG_DATAO_2 0x000006f4 800 801 /* sdr to hdr */ 802 #define RK3328_SDR2HDR_CTRL 0x00000700 803 #define RK3328_EOTF_OETF_Y0 0x00000704 804 #define RK3328_RESERVED0001 0x00000708 805 #define RK3328_RESERVED0002 0x0000070c 806 #define RK3328_EOTF_OETF_Y1 0x00000710 807 #define RK3328_EOTF_OETF_Y64 0x0000080c 808 #define RK3328_OETF_DX_DXPOW1 0x00000810 809 #define RK3328_OETF_DX_DXPOW64 0x0000090c 810 #define RK3328_OETF_XN1 0x00000910 811 #define RK3328_OETF_XN63 0x00000a08 812 813 /* hdr to sdr */ 814 #define RK3328_HDR2SDR_CTRL 0x00000a10 815 #define RK3328_HDR2SDR_SRC_RANGE 0x00000a14 816 #define RK3328_HDR2SDR_NORMFACEETF 0x00000a18 817 #define RK3328_RESERVED0003 0x00000a1c 818 #define RK3328_HDR2SDR_DST_RANGE 0x00000a20 819 #define RK3328_HDR2SDR_NORMFACCGAMMA 0x00000a24 820 #define RK3328_EETF_OETF_Y0 0x00000a28 821 #define RK3328_SAT_Y0 0x00000a2c 822 #define RK3328_EETF_OETF_Y1 0x00000a30 823 #define RK3328_SAT_Y1 0x00000ab0 824 #define RK3328_SAT_Y8 0x00000acc 825 826 #define RK3328_HWC_LUT_ADDR 0x00000c00 827 828 /* rk3036 register definition */ 829 #define RK3036_SYS_CTRL 0x00 830 #define RK3036_DSP_CTRL0 0x04 831 #define RK3036_DSP_CTRL1 0x08 832 #define RK3036_INT_STATUS 0x10 833 #define RK3036_ALPHA_CTRL 0x14 834 #define RK3036_WIN0_COLOR_KEY 0x18 835 #define RK3036_WIN1_COLOR_KEY 0x1c 836 #define RK3036_WIN0_YRGB_MST 0x20 837 #define RK3036_WIN0_CBR_MST 0x24 838 #define RK3036_WIN1_VIR 0x28 839 #define RK3036_AXI_BUS_CTRL 0x2c 840 #define RK3036_WIN0_VIR 0x30 841 #define RK3036_WIN0_ACT_INFO 0x34 842 #define RK3036_WIN0_DSP_INFO 0x38 843 #define RK3036_WIN0_DSP_ST 0x3c 844 #define RK3036_WIN0_SCL_FACTOR_YRGB 0x40 845 #define RK3036_WIN0_SCL_FACTOR_CBR 0x44 846 #define RK3036_WIN0_SCL_OFFSET 0x48 847 #define RK3036_HWC_MST 0x58 848 #define RK3036_HWC_DSP_ST 0x5c 849 #define RK3036_DSP_HTOTAL_HS_END 0x6c 850 #define RK3036_DSP_HACT_ST_END 0x70 851 #define RK3036_DSP_VTOTAL_VS_END 0x74 852 #define RK3036_DSP_VACT_ST_END 0x78 853 #define RK3036_DSP_VS_ST_END_F1 0x7c 854 #define RK3036_DSP_VACT_ST_END_F1 0x80 855 #define RK3036_GATHER_TRANSFER 0x84 856 #define RK3036_VERSION_INFO 0x94 857 #define RK3036_REG_CFG_DONE 0x90 858 #define RK3036_WIN1_MST 0xa0 859 #define RK3036_WIN1_ACT_INFO 0xb4 860 #define RK3036_WIN1_DSP_INFO 0xb8 861 #define RK3036_WIN1_DSP_ST 0xbc 862 #define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0 863 #define RK3036_WIN1_SCL_OFFSET 0xc8 864 #define RK3036_BCSH_CTRL 0xd0 865 #define RK3036_BCSH_COLOR_BAR 0xd4 866 #define RK3036_BCSH_BCS 0xd8 867 #define RK3036_BCSH_H 0xdc 868 #define RK3036_WIN1_LUT_ADDR 0x400 869 #define RK3036_HWC_LUT_ADDR 0x800 870 /* rk3036 register definition end */ 871 872 #endif /* _ROCKCHIP_VOP_REG_H */ 873