1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <linux/list.h> 14 15 #include "rockchip_vop.h" 16 #include "rockchip_vop_reg.h" 17 18 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \ 19 _begin_minor, _end_minor) \ 20 {.offset = off, \ 21 .mask = _mask, \ 22 .shift = s, \ 23 .write_mask = _write_mask, \ 24 .major = _major, \ 25 .begin_minor = _begin_minor, \ 26 .end_minor = _end_minor,} 27 28 #define VOP_REG(off, _mask, s) \ 29 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1) 30 31 #define VOP_REG_MASK(off, _mask, s) \ 32 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1) 33 34 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \ 35 VOP_REG_VER_MASK(off, _mask, s, false, \ 36 _major, _begin_minor, _end_minor) 37 38 static const struct vop_scl_extension rk3288_win_full_scl_ext = { 39 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), 40 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), 41 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28), 42 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26), 43 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24), 44 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23), 45 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22), 46 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20), 47 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18), 48 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16), 49 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15), 50 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12), 51 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8), 52 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7), 53 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6), 54 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5), 55 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4), 56 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2), 57 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1), 58 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0), 59 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5), 60 }; 61 62 static const struct vop_scl_regs rk3288_win_full_scl = { 63 .ext = &rk3288_win_full_scl_ext, 64 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 65 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 66 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 67 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 68 }; 69 70 static const struct vop_win rk3288_win01_data = { 71 .scl = &rk3288_win_full_scl, 72 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), 73 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), 74 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), 75 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1), 76 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), 77 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), 78 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0), 79 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0), 80 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0), 81 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0), 82 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), 83 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0), 84 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0), 85 }; 86 87 static const struct vop_ctrl rk3288_ctrl_data = { 88 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22), 89 .axi_outstanding_max_num = VOP_REG(RK3288_SYS_CTRL1, 0x1f, 13), 90 .axi_max_outstanding_en = VOP_REG(RK3288_SYS_CTRL1, 0x1, 12), 91 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 92 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), 93 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 94 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), 95 .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 96 .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 97 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 98 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 99 .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 100 .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 101 .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0), 102 103 .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10), 104 .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), 105 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8), 106 .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1), 107 .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1), 108 .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1), 109 .core_dclk_div = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 4, 3, 4, -1), 110 .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1), 111 .dclk_ddr = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 8, 3, 4, -1), 112 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 113 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 114 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 115 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 116 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 117 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), 118 .data01_swap = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 17, 3, 5, -1), 119 .dclk_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x1, 7, 3, 0, 1), 120 .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1), 121 .dp_dclk_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x1, 19, 3, 5, -1), 122 .dp_pin_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x7, 16, 3, 5, -1), 123 .rgb_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 19, 3, 2, -1), 124 .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 16, 3, 2, -1), 125 .tve_dclk_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 24), 126 .tve_dclk_pol = VOP_REG(RK3288_SYS_CTRL, 0x1, 25), 127 .tve_sw_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 26), 128 .sw_uv_offset_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 27), 129 .sw_genlock = VOP_REG(RK3288_SYS_CTRL, 0x1, 28), 130 .hdmi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 23, 3, 2, -1), 131 .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 20, 3, 2, -1), 132 .edp_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 27, 3, 2, -1), 133 .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 24, 3, 2, -1), 134 .mipi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 31, 3, 2, -1), 135 .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 28, 3, 2, -1), 136 137 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1), 138 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), 139 140 .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1), 141 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), 142 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20), 143 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), 144 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0), 145 .update_gamma_lut = VOP_REG_VER(RK3288_DSP_CTRL1, 0x1, 7, 3, 5, -1), 146 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), 147 148 .bcsh_brightness = VOP_REG(RK3288_BCSH_BCS, 0xff, 0), 149 .bcsh_contrast = VOP_REG(RK3288_BCSH_BCS, 0x1ff, 8), 150 .bcsh_sat_con = VOP_REG(RK3288_BCSH_BCS, 0x3ff, 20), 151 .bcsh_out_mode = VOP_REG(RK3288_BCSH_BCS, 0x3, 0), 152 .bcsh_sin_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 0), 153 .bcsh_cos_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 16), 154 .bcsh_r2y_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 6, 3, 1, -1), 155 .bcsh_r2y_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 4, 3, 1, -1), 156 .bcsh_y2r_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x3, 2, 3, 1, -1), 157 .bcsh_y2r_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 0, 3, 1, -1), 158 .bcsh_color_bar = VOP_REG(RK3288_BCSH_COLOR_BAR, 0xffffff, 8), 159 .bcsh_en = VOP_REG(RK3288_BCSH_COLOR_BAR, 0x1, 0), 160 161 .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22), 162 .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23), 163 164 .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), 165 166 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0), 167 .win_gate[0] = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), 168 .win_gate[1] = VOP_REG(RK3288_WIN3_CTRL0, 0x1, 0), 169 }; 170 171 static const struct vop_line_flag rk3288_vop_line_flag = { 172 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), 173 }; 174 175 static const struct vop_grf_ctrl rk3288_vop_big_grf_ctrl = { 176 .grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 12), 177 }; 178 179 static const struct vop_grf_ctrl rk3288_vop_lit_grf_ctrl = { 180 .grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 14), 181 }; 182 183 const struct vop_data rk3288_vop_big = { 184 .version = VOP_VERSION(3, 1), 185 .max_output = {3840, 2160}, 186 .feature = VOP_FEATURE_OUTPUT_10BIT, 187 .ctrl = &rk3288_ctrl_data, 188 .grf_ctrl = &rk3288_vop_big_grf_ctrl, 189 .win = &rk3288_win01_data, 190 .line_flag = &rk3288_vop_line_flag, 191 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 192 }; 193 194 const struct vop_data rk3288_vop_lit = { 195 .version = VOP_VERSION(3, 1), 196 .max_output = {2560, 1600}, 197 .feature = VOP_FEATURE_OUTPUT_10BIT, 198 .ctrl = &rk3288_ctrl_data, 199 .grf_ctrl = &rk3288_vop_lit_grf_ctrl, 200 .win = &rk3288_win01_data, 201 .line_flag = &rk3288_vop_line_flag, 202 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 203 }; 204 205 static const struct vop_line_flag rk3368_vop_line_flag = { 206 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), 207 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), 208 }; 209 210 static const struct vop_grf_ctrl rk3368_vop_grf_ctrl = { 211 .grf_dclk_inv = VOP_REG(RK3368_GRF_SOC_CON6, 0x1, 5), 212 }; 213 214 const struct vop_data rk3368_vop = { 215 .version = VOP_VERSION(3, 2), 216 .max_output = {4096, 2160}, 217 .ctrl = &rk3288_ctrl_data, 218 .grf_ctrl = &rk3368_vop_grf_ctrl, 219 .win = &rk3288_win01_data, 220 .line_flag = &rk3368_vop_line_flag, 221 .reg_len = RK3368_DSP_VACT_ST_END_F1 * 4, 222 }; 223 224 static const struct vop_line_flag rk3366_vop_line_flag = { 225 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), 226 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), 227 }; 228 229 const struct vop_data rk3366_vop = { 230 .version = VOP_VERSION(3, 4), 231 .max_output = {4096, 2160}, 232 .ctrl = &rk3288_ctrl_data, 233 .win = &rk3288_win01_data, 234 .line_flag = &rk3366_vop_line_flag, 235 .reg_len = RK3366_DSP_VACT_ST_END_F1 * 4, 236 }; 237 238 const struct vop_data rk3399_vop_big = { 239 .version = VOP_VERSION(3, 5), 240 .max_output = {4096, 2160}, 241 .feature = VOP_FEATURE_OUTPUT_10BIT, 242 .ctrl = &rk3288_ctrl_data, 243 .win = &rk3288_win01_data, 244 .line_flag = &rk3366_vop_line_flag, 245 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 246 }; 247 248 const struct vop_data rk3399_vop_lit = { 249 .version = VOP_VERSION(3, 6), 250 .max_output = {2560, 1600}, 251 .ctrl = &rk3288_ctrl_data, 252 .win = &rk3288_win01_data, 253 .line_flag = &rk3366_vop_line_flag, 254 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 255 }; 256 257 const struct vop_data rk322x_vop = { 258 .version = VOP_VERSION(3, 7), 259 .max_output = {4096, 2160}, 260 .feature = VOP_FEATURE_OUTPUT_10BIT, 261 .ctrl = &rk3288_ctrl_data, 262 .win = &rk3288_win01_data, 263 .line_flag = &rk3366_vop_line_flag, 264 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 265 }; 266 267 static const struct vop_ctrl rk3328_ctrl_data = { 268 .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22), 269 .axi_outstanding_max_num = VOP_REG(RK3328_SYS_CTRL1, 0x1f, 13), 270 .axi_max_outstanding_en = VOP_REG(RK3328_SYS_CTRL1, 0x1, 12), 271 .reg_done_frm = VOP_REG(RK3328_SYS_CTRL1, 0x1, 24), 272 .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23), 273 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 274 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), 275 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 276 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), 277 .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 278 .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 279 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 280 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 281 .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 282 .post_scl_factor = VOP_REG(RK3328_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 283 .post_scl_ctrl = VOP_REG(RK3328_POST_SCL_CTRL, 0x3, 0), 284 .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2), 285 .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10), 286 .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8), 287 .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18), 288 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), 289 .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), 290 .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4), 291 .dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8), 292 .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5), 293 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 294 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 295 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 296 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 297 .tve_dclk_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 24), 298 .tve_dclk_pol = VOP_REG(RK3328_SYS_CTRL, 0x1, 25), 299 .tve_sw_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 26), 300 .sw_uv_offset_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 27), 301 .sw_genlock = VOP_REG(RK3328_SYS_CTRL, 0x1, 28), 302 .sw_dac_sel = VOP_REG(RK3328_SYS_CTRL, 0x1, 29), 303 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), 304 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), 305 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), 306 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), 307 308 .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1), 309 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), 310 311 .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12), 312 .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20), 313 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), 314 .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0), 315 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), 316 317 .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22), 318 .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23), 319 320 .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0), 321 322 .bcsh_brightness = VOP_REG(RK3328_BCSH_BCS, 0xff, 0), 323 .bcsh_contrast = VOP_REG(RK3328_BCSH_BCS, 0x1ff, 8), 324 .bcsh_sat_con = VOP_REG(RK3328_BCSH_BCS, 0x3ff, 20), 325 .bcsh_out_mode = VOP_REG(RK3328_BCSH_BCS, 0x3, 30), 326 .bcsh_sin_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 0), 327 .bcsh_cos_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 16), 328 .bcsh_r2y_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 6), 329 .bcsh_r2y_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 4), 330 .bcsh_y2r_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 2), 331 .bcsh_y2r_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 0), 332 .bcsh_color_bar = VOP_REG(RK3328_BCSH_COLOR_BAR, 0xffffff, 8), 333 .bcsh_en = VOP_REG(RK3328_BCSH_COLOR_BAR, 0x1, 0), 334 .win_channel[0] = VOP_REG_VER(RK3328_WIN0_CTRL2, 0xff, 0, 3, 8, 8), 335 .win_channel[1] = VOP_REG_VER(RK3328_WIN1_CTRL2, 0xff, 0, 3, 8, 8), 336 .win_channel[2] = VOP_REG_VER(RK3328_WIN2_CTRL2, 0xff, 0, 3, 8, 8), 337 338 .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0), 339 }; 340 341 342 static const struct vop_line_flag rk3328_vop_line_flag = { 343 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), 344 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), 345 }; 346 347 const struct vop_data rk3328_vop = { 348 .version = VOP_VERSION(3, 8), 349 .max_output = {4096, 2160}, 350 .feature = VOP_FEATURE_OUTPUT_10BIT, 351 .ctrl = &rk3328_ctrl_data, 352 .win = &rk3288_win01_data, 353 .win_offset = 0xd0, 354 .line_flag = &rk3328_vop_line_flag, 355 .reg_len = RK3328_DSP_VACT_ST_END_F1 * 4, 356 }; 357 358 static const struct vop_scl_regs rk3036_win_scl = { 359 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 360 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 361 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 362 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 363 }; 364 365 static const struct vop_win rk3036_win0_data = { 366 .scl = &rk3036_win_scl, 367 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), 368 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), 369 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), 370 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), 371 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), 372 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), 373 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), 374 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), 375 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), 376 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), 377 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18), 378 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0) 379 }; 380 381 static const struct vop_ctrl rk3036_ctrl_data = { 382 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), 383 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), 384 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), 385 .dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7), 386 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), 387 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8), 388 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 389 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), 390 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 391 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), 392 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), 393 }; 394 395 static const struct vop_line_flag rk3036_vop_line_flag = { 396 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), 397 }; 398 399 const struct vop_data rk3036_vop = { 400 .version = VOP_VERSION(2, 2), 401 .max_output = {1920, 1080}, 402 .ctrl = &rk3036_ctrl_data, 403 .win = &rk3036_win0_data, 404 .line_flag = &rk3036_vop_line_flag, 405 .reg_len = RK3036_DSP_VACT_ST_END_F1 * 4, 406 }; 407 408 static const struct vop_scl_regs rk3366_lit_win_scl = { 409 .scale_yrgb_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 410 .scale_yrgb_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 411 .scale_cbcr_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 412 .scale_cbcr_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 413 }; 414 415 static const struct vop_win rk3366_win0_data = { 416 .scl = &rk3366_lit_win_scl, 417 418 .enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0), 419 .format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1), 420 .rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12), 421 .act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0), 422 .dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0), 423 .dsp_st = VOP_REG(RK3366_LIT_WIN0_DSP_ST, 0xffffffff, 0), 424 .yrgb_mst = VOP_REG(RK3366_LIT_WIN0_YRGB_MST0, 0xffffffff, 0), 425 .uv_mst = VOP_REG(RK3366_LIT_WIN0_CBR_MST0, 0xffffffff, 0), 426 .yrgb_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 0), 427 .uv_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 16), 428 429 .alpha_mode = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 1), 430 .alpha_en = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 0), 431 }; 432 433 static const struct vop_win rk3366_win1_data = { 434 .enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0), 435 .format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4), 436 .rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12), 437 .dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0), 438 .dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0), 439 .yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0), 440 .yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0), 441 442 .alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1), 443 .alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0), 444 }; 445 446 static const struct vop_ctrl px30_ctrl_data = { 447 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 448 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 449 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 450 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 451 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 452 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 453 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 454 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0), 455 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 456 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 457 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 22), 458 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 459 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13), 460 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 461 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 462 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 463 .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8), 464 .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10), 465 .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16), 466 .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18), 467 .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24), 468 .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26), 469 .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25), 470 .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17), 471 .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9), 472 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 473 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 474 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6), 475 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 476 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 477 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 478 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 479 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 480 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 481 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 482 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 483 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 484 485 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 486 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 487 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 488 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 489 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 490 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 491 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 492 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 493 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 494 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 495 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 496 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 497 498 .cabc_config_mode = VOP_REG(PX30_CABC_CTRL0, 0x3, 2), 499 .cabc_calc_pixel_num = VOP_REG(PX30_CABC_CTRL0, 0x7fffff, 4), 500 .cabc_handle_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 1), 501 .cabc_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 0), 502 .cabc_total_num = VOP_REG(PX30_CABC_CTRL1, 0x7fffff, 4), 503 .cabc_lut_en = VOP_REG(PX30_CABC_CTRL1, 0x1, 0), 504 .cabc_stage_up_mode = VOP_REG(PX30_CABC_CTRL2, 0x1, 19), 505 .cabc_stage_up = VOP_REG(PX30_CABC_CTRL2, 0x1ff, 8), 506 .cabc_stage_down = VOP_REG(PX30_CABC_CTRL2, 0xff, 0), 507 .cabc_global_dn = VOP_REG(PX30_CABC_CTRL3, 0xff, 0), 508 .cabc_global_dn_limit_en = VOP_REG(PX30_CABC_CTRL3, 0x1, 8), 509 }; 510 511 static const struct vop_line_flag rk3366_vop_lite_line_flag = { 512 .line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0), 513 }; 514 515 static const struct vop_grf_ctrl px30_grf_ctrl = { 516 .grf_dclk_inv = VOP_REG(PX30_GRF_PD_VO_CON1, 0x1, 4), 517 }; 518 519 const struct vop_data px30_vop_lit = { 520 .version = VOP_VERSION(2, 5), 521 .max_output = {1920, 1080}, 522 .ctrl = &px30_ctrl_data, 523 .grf_ctrl = &px30_grf_ctrl, 524 .win = &rk3366_win1_data, 525 .line_flag = &rk3366_vop_lite_line_flag, 526 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 527 }; 528 529 const struct vop_data px30_vop_big = { 530 .version = VOP_VERSION(2, 6), 531 .max_output = {1920, 1080}, 532 .ctrl = &px30_ctrl_data, 533 .grf_ctrl = &px30_grf_ctrl, 534 .win = &rk3366_win0_data, 535 .line_flag = &rk3366_vop_lite_line_flag, 536 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 537 }; 538 539 static const struct vop_ctrl rk3308_ctrl_data = { 540 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 541 .axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16), 542 .axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12), 543 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 544 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 545 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 546 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 547 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 548 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 549 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 550 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 551 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 3), 552 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 553 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 554 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 555 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 556 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 557 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 558 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6), 559 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 560 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 561 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 562 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 563 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 564 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 565 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 566 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 567 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 568 569 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 570 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 571 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 572 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 573 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 574 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 575 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 576 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 577 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 578 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 579 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 580 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 581 582 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), 583 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), 584 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), 585 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), 586 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), 587 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), 588 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), 589 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), 590 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), 591 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), 592 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), 593 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, 594 0xffffffff, 0), 595 }; 596 597 const struct vop_data rk3308_vop = { 598 .version = VOP_VERSION(2, 7), 599 .max_output = {1920, 1080}, 600 .ctrl = &rk3308_ctrl_data, 601 .win = &rk3366_win0_data, 602 .line_flag = &rk3366_vop_lite_line_flag, 603 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 604 }; 605