1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <linux/list.h> 14 15 #include "rockchip_vop.h" 16 #include "rockchip_vop_reg.h" 17 18 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \ 19 _begin_minor, _end_minor) \ 20 {.offset = off, \ 21 .mask = _mask, \ 22 .shift = s, \ 23 .write_mask = _write_mask, \ 24 .major = _major, \ 25 .begin_minor = _begin_minor, \ 26 .end_minor = _end_minor,} 27 28 #define VOP_REG(off, _mask, s) \ 29 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1) 30 31 #define VOP_REG_MASK(off, _mask, s) \ 32 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1) 33 34 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \ 35 VOP_REG_VER_MASK(off, _mask, s, false, \ 36 _major, _begin_minor, _end_minor) 37 38 static const struct vop_scl_extension rk3288_win_full_scl_ext = { 39 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), 40 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), 41 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28), 42 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26), 43 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24), 44 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23), 45 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22), 46 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20), 47 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18), 48 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16), 49 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15), 50 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12), 51 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8), 52 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7), 53 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6), 54 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5), 55 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4), 56 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2), 57 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1), 58 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0), 59 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5), 60 }; 61 62 static const struct vop_scl_regs rk3288_win_full_scl = { 63 .ext = &rk3288_win_full_scl_ext, 64 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 65 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 66 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 67 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 68 }; 69 70 static const struct vop_win rk3288_win01_data = { 71 .scl = &rk3288_win_full_scl, 72 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), 73 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), 74 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), 75 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1), 76 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), 77 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), 78 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0), 79 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0), 80 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0), 81 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0), 82 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), 83 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0), 84 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0), 85 }; 86 87 static const struct vop_ctrl rk3288_ctrl_data = { 88 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22), 89 .axi_outstanding_max_num = VOP_REG(RK3288_SYS_CTRL1, 0x1f, 13), 90 .axi_max_outstanding_en = VOP_REG(RK3288_SYS_CTRL1, 0x1, 12), 91 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 92 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), 93 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 94 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), 95 .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 96 .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 97 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 98 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 99 .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 100 .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 101 .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0), 102 103 .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10), 104 .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), 105 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8), 106 .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1), 107 .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1), 108 .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1), 109 .core_dclk_div = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 4, 3, 4, -1), 110 .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1), 111 .dclk_ddr = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 8, 3, 4, -1), 112 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 113 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 114 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 115 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 116 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 117 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), 118 .data01_swap = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 17, 3, 5, -1), 119 .dclk_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x1, 7, 3, 0, 1), 120 .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1), 121 .dp_dclk_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x1, 19, 3, 5, -1), 122 .dp_pin_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x7, 16, 3, 5, -1), 123 .rgb_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 19, 3, 2, -1), 124 .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 16, 3, 2, -1), 125 .tve_dclk_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 24), 126 .tve_dclk_pol = VOP_REG(RK3288_SYS_CTRL, 0x1, 25), 127 .tve_sw_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 26), 128 .sw_uv_offset_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 27), 129 .sw_genlock = VOP_REG(RK3288_SYS_CTRL, 0x1, 28), 130 .hdmi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 23, 3, 2, -1), 131 .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 20, 3, 2, -1), 132 .edp_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 27, 3, 2, -1), 133 .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 24, 3, 2, -1), 134 .mipi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 31, 3, 2, -1), 135 .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 28, 3, 2, -1), 136 137 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1), 138 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), 139 140 .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1), 141 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), 142 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20), 143 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), 144 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0), 145 .update_gamma_lut = VOP_REG_VER(RK3288_DSP_CTRL1, 0x1, 7, 3, 5, -1), 146 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), 147 148 .bcsh_brightness = VOP_REG(RK3288_BCSH_BCS, 0xff, 0), 149 .bcsh_contrast = VOP_REG(RK3288_BCSH_BCS, 0x1ff, 8), 150 .bcsh_sat_con = VOP_REG(RK3288_BCSH_BCS, 0x3ff, 20), 151 .bcsh_out_mode = VOP_REG(RK3288_BCSH_BCS, 0x3, 0), 152 .bcsh_sin_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 0), 153 .bcsh_cos_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 16), 154 .bcsh_r2y_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 6, 3, 1, -1), 155 .bcsh_r2y_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 4, 3, 1, -1), 156 .bcsh_y2r_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x3, 2, 3, 1, -1), 157 .bcsh_y2r_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 0, 3, 1, -1), 158 .bcsh_color_bar = VOP_REG(RK3288_BCSH_COLOR_BAR, 0xffffff, 8), 159 .bcsh_en = VOP_REG(RK3288_BCSH_COLOR_BAR, 0x1, 0), 160 161 .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22), 162 .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23), 163 164 .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), 165 166 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0), 167 .win_gate[0] = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), 168 .win_gate[1] = VOP_REG(RK3288_WIN3_CTRL0, 0x1, 0), 169 }; 170 171 static const struct vop_line_flag rk3288_vop_line_flag = { 172 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), 173 }; 174 175 static const struct vop_grf_ctrl rk3288_vop_big_grf_ctrl = { 176 .grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 12), 177 }; 178 179 static const struct vop_grf_ctrl rk3288_vop_lit_grf_ctrl = { 180 .grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 14), 181 }; 182 183 const struct vop_data rk3288_vop_big = { 184 .version = VOP_VERSION(3, 1), 185 .max_output = {3840, 2160}, 186 .feature = VOP_FEATURE_OUTPUT_10BIT, 187 .ctrl = &rk3288_ctrl_data, 188 .grf_ctrl = &rk3288_vop_big_grf_ctrl, 189 .win = &rk3288_win01_data, 190 .line_flag = &rk3288_vop_line_flag, 191 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 192 }; 193 194 const struct vop_data rk3288_vop_lit = { 195 .version = VOP_VERSION(3, 1), 196 .max_output = {2560, 1600}, 197 .feature = VOP_FEATURE_OUTPUT_10BIT, 198 .ctrl = &rk3288_ctrl_data, 199 .grf_ctrl = &rk3288_vop_lit_grf_ctrl, 200 .win = &rk3288_win01_data, 201 .line_flag = &rk3288_vop_line_flag, 202 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 203 }; 204 205 static const struct vop_line_flag rk3368_vop_line_flag = { 206 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), 207 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), 208 }; 209 210 static const struct vop_grf_ctrl rk3368_vop_grf_ctrl = { 211 .grf_dclk_inv = VOP_REG(RK3368_GRF_SOC_CON6, 0x1, 5), 212 }; 213 214 const struct vop_data rk3368_vop = { 215 .version = VOP_VERSION(3, 2), 216 .max_output = {4096, 2160}, 217 .ctrl = &rk3288_ctrl_data, 218 .grf_ctrl = &rk3368_vop_grf_ctrl, 219 .win = &rk3288_win01_data, 220 .line_flag = &rk3368_vop_line_flag, 221 .reg_len = RK3368_DSP_VACT_ST_END_F1 * 4, 222 }; 223 224 static const struct vop_line_flag rk3366_vop_line_flag = { 225 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), 226 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), 227 }; 228 229 const struct vop_data rk3366_vop = { 230 .version = VOP_VERSION(3, 4), 231 .max_output = {4096, 2160}, 232 .ctrl = &rk3288_ctrl_data, 233 .win = &rk3288_win01_data, 234 .line_flag = &rk3366_vop_line_flag, 235 .reg_len = RK3366_DSP_VACT_ST_END_F1 * 4, 236 }; 237 238 static const uint32_t vop_csc_r2y_bt601[] = { 239 0x02590132, 0xff530075, 0x0200fead, 0xfe530200, 240 0x0000ffad, 0x00000200, 0x00080200, 0x00080200, 241 }; 242 243 static const uint32_t vop_csc_r2y_bt601_12_235[] = { 244 0x02040107, 0xff680064, 0x01c2fed6, 0xffb7fe87, 245 0x0000ffb7, 0x00010200, 0x00080200, 0x00080200, 246 }; 247 248 static const uint32_t vop_csc_r2y_bt709[] = { 249 0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2, 250 0x0000ffd7, 0x00010200, 0x00080200, 0x00080200, 251 }; 252 253 static const uint32_t vop_csc_r2y_bt2020[] = { 254 0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1, 255 0x0000ffdc, 0x00010200, 0x00080200, 0x00080200, 256 }; 257 258 static const struct vop_csc_table rk3399_csc_table = { 259 .r2y_bt601 = vop_csc_r2y_bt601, 260 .r2y_bt601_12_235 = vop_csc_r2y_bt601_12_235, 261 .r2y_bt709 = vop_csc_r2y_bt709, 262 .r2y_bt2020 = vop_csc_r2y_bt2020, 263 }; 264 265 static const struct vop_csc rk3399_win0_csc = { 266 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0), 267 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1), 268 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2), 269 .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R, 270 .r2r_offset = RK3399_WIN0_YUV2YUV_3X3, 271 .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y, 272 }; 273 274 const struct vop_data rk3399_vop_big = { 275 .version = VOP_VERSION(3, 5), 276 .max_output = {4096, 2160}, 277 .feature = VOP_FEATURE_OUTPUT_10BIT, 278 .ctrl = &rk3288_ctrl_data, 279 .win = &rk3288_win01_data, 280 .line_flag = &rk3366_vop_line_flag, 281 .csc_table = &rk3399_csc_table, 282 .win_csc = &rk3399_win0_csc, 283 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 284 }; 285 286 const struct vop_data rk3399_vop_lit = { 287 .version = VOP_VERSION(3, 6), 288 .max_output = {2560, 1600}, 289 .ctrl = &rk3288_ctrl_data, 290 .win = &rk3288_win01_data, 291 .line_flag = &rk3366_vop_line_flag, 292 .csc_table = &rk3399_csc_table, 293 .win_csc = &rk3399_win0_csc, 294 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 295 }; 296 297 const struct vop_data rk322x_vop = { 298 .version = VOP_VERSION(3, 7), 299 .max_output = {4096, 2160}, 300 .feature = VOP_FEATURE_OUTPUT_10BIT, 301 .ctrl = &rk3288_ctrl_data, 302 .win = &rk3288_win01_data, 303 .line_flag = &rk3366_vop_line_flag, 304 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 305 }; 306 307 static const struct vop_ctrl rk3328_ctrl_data = { 308 .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22), 309 .axi_outstanding_max_num = VOP_REG(RK3328_SYS_CTRL1, 0x1f, 13), 310 .axi_max_outstanding_en = VOP_REG(RK3328_SYS_CTRL1, 0x1, 12), 311 .reg_done_frm = VOP_REG(RK3328_SYS_CTRL1, 0x1, 24), 312 .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23), 313 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 314 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), 315 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 316 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), 317 .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 318 .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 319 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 320 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 321 .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 322 .post_scl_factor = VOP_REG(RK3328_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 323 .post_scl_ctrl = VOP_REG(RK3328_POST_SCL_CTRL, 0x3, 0), 324 .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2), 325 .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10), 326 .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8), 327 .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18), 328 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), 329 .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), 330 .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4), 331 .dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8), 332 .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5), 333 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 334 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 335 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 336 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 337 .tve_dclk_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 24), 338 .tve_dclk_pol = VOP_REG(RK3328_SYS_CTRL, 0x1, 25), 339 .tve_sw_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 26), 340 .sw_uv_offset_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 27), 341 .sw_genlock = VOP_REG(RK3328_SYS_CTRL, 0x1, 28), 342 .sw_dac_sel = VOP_REG(RK3328_SYS_CTRL, 0x1, 29), 343 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), 344 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), 345 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), 346 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), 347 348 .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1), 349 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), 350 351 .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12), 352 .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20), 353 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), 354 .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0), 355 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), 356 357 .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22), 358 .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23), 359 360 .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0), 361 362 .bcsh_brightness = VOP_REG(RK3328_BCSH_BCS, 0xff, 0), 363 .bcsh_contrast = VOP_REG(RK3328_BCSH_BCS, 0x1ff, 8), 364 .bcsh_sat_con = VOP_REG(RK3328_BCSH_BCS, 0x3ff, 20), 365 .bcsh_out_mode = VOP_REG(RK3328_BCSH_BCS, 0x3, 30), 366 .bcsh_sin_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 0), 367 .bcsh_cos_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 16), 368 .bcsh_r2y_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 6), 369 .bcsh_r2y_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 4), 370 .bcsh_y2r_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 2), 371 .bcsh_y2r_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 0), 372 .bcsh_color_bar = VOP_REG(RK3328_BCSH_COLOR_BAR, 0xffffff, 8), 373 .bcsh_en = VOP_REG(RK3328_BCSH_COLOR_BAR, 0x1, 0), 374 .win_channel[0] = VOP_REG_VER(RK3328_WIN0_CTRL2, 0xff, 0, 3, 8, 8), 375 .win_channel[1] = VOP_REG_VER(RK3328_WIN1_CTRL2, 0xff, 0, 3, 8, 8), 376 .win_channel[2] = VOP_REG_VER(RK3328_WIN2_CTRL2, 0xff, 0, 3, 8, 8), 377 378 .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0), 379 }; 380 381 382 static const struct vop_line_flag rk3328_vop_line_flag = { 383 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), 384 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), 385 }; 386 387 const struct vop_data rk3328_vop = { 388 .version = VOP_VERSION(3, 8), 389 .max_output = {4096, 2160}, 390 .feature = VOP_FEATURE_OUTPUT_10BIT, 391 .ctrl = &rk3328_ctrl_data, 392 .win = &rk3288_win01_data, 393 .win_offset = 0xd0, 394 .line_flag = &rk3328_vop_line_flag, 395 .reg_len = RK3328_DSP_VACT_ST_END_F1 * 4, 396 }; 397 398 static const struct vop_scl_regs rk3036_win_scl = { 399 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 400 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 401 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 402 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 403 }; 404 405 static const struct vop_win rk3036_win0_data = { 406 .scl = &rk3036_win_scl, 407 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), 408 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), 409 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), 410 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), 411 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), 412 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), 413 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), 414 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), 415 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), 416 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), 417 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18), 418 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0) 419 }; 420 421 static const struct vop_ctrl rk3036_ctrl_data = { 422 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), 423 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), 424 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), 425 .dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7), 426 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), 427 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8), 428 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 429 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), 430 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 431 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), 432 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), 433 }; 434 435 static const struct vop_line_flag rk3036_vop_line_flag = { 436 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), 437 }; 438 439 const struct vop_data rk3036_vop = { 440 .version = VOP_VERSION(2, 2), 441 .max_output = {1920, 1080}, 442 .ctrl = &rk3036_ctrl_data, 443 .win = &rk3036_win0_data, 444 .line_flag = &rk3036_vop_line_flag, 445 .reg_len = RK3036_DSP_VACT_ST_END_F1 * 4, 446 }; 447 448 static const struct vop_scl_regs rk3366_lit_win_scl = { 449 .scale_yrgb_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 450 .scale_yrgb_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 451 .scale_cbcr_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 452 .scale_cbcr_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 453 }; 454 455 static const struct vop_win rk3366_win0_data = { 456 .scl = &rk3366_lit_win_scl, 457 458 .enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0), 459 .format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1), 460 .rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12), 461 .act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0), 462 .dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0), 463 .dsp_st = VOP_REG(RK3366_LIT_WIN0_DSP_ST, 0xffffffff, 0), 464 .yrgb_mst = VOP_REG(RK3366_LIT_WIN0_YRGB_MST0, 0xffffffff, 0), 465 .uv_mst = VOP_REG(RK3366_LIT_WIN0_CBR_MST0, 0xffffffff, 0), 466 .yrgb_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 0), 467 .uv_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 16), 468 469 .alpha_mode = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 1), 470 .alpha_en = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 0), 471 }; 472 473 static const struct vop_win rk3366_win1_data = { 474 .enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0), 475 .format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4), 476 .rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12), 477 .dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0), 478 .dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0), 479 .yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0), 480 .yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0), 481 482 .alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1), 483 .alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0), 484 }; 485 486 static const struct vop_ctrl px30_ctrl_data = { 487 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 488 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 489 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 490 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 491 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 492 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 493 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 494 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0), 495 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 496 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 497 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 22), 498 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 499 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13), 500 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 501 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 502 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 503 .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8), 504 .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10), 505 .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16), 506 .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18), 507 .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24), 508 .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26), 509 .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25), 510 .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17), 511 .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9), 512 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 513 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 514 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6), 515 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 516 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 517 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 518 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 519 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 520 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 521 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 522 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 523 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 524 525 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 526 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 527 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 528 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 529 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 530 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 531 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 532 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 533 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 534 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 535 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 536 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 537 538 .cabc_config_mode = VOP_REG(PX30_CABC_CTRL0, 0x3, 2), 539 .cabc_calc_pixel_num = VOP_REG(PX30_CABC_CTRL0, 0x7fffff, 4), 540 .cabc_handle_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 1), 541 .cabc_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 0), 542 .cabc_total_num = VOP_REG(PX30_CABC_CTRL1, 0x7fffff, 4), 543 .cabc_lut_en = VOP_REG(PX30_CABC_CTRL1, 0x1, 0), 544 .cabc_stage_up_mode = VOP_REG(PX30_CABC_CTRL2, 0x1, 19), 545 .cabc_stage_up = VOP_REG(PX30_CABC_CTRL2, 0x1ff, 8), 546 .cabc_stage_down = VOP_REG(PX30_CABC_CTRL2, 0xff, 0), 547 .cabc_global_dn = VOP_REG(PX30_CABC_CTRL3, 0xff, 0), 548 .cabc_global_dn_limit_en = VOP_REG(PX30_CABC_CTRL3, 0x1, 8), 549 550 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), 551 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), 552 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), 553 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), 554 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), 555 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), 556 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), 557 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), 558 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), 559 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), 560 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), 561 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, 562 0xffffffff, 0), 563 }; 564 565 static const struct vop_line_flag rk3366_vop_lite_line_flag = { 566 .line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0), 567 }; 568 569 static const struct vop_grf_ctrl px30_grf_ctrl = { 570 .grf_dclk_inv = VOP_REG(PX30_GRF_PD_VO_CON1, 0x1, 4), 571 }; 572 573 const struct vop_data px30_vop_lit = { 574 .version = VOP_VERSION(2, 5), 575 .max_output = {1920, 1080}, 576 .ctrl = &px30_ctrl_data, 577 .grf_ctrl = &px30_grf_ctrl, 578 .win = &rk3366_win1_data, 579 .line_flag = &rk3366_vop_lite_line_flag, 580 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 581 }; 582 583 const struct vop_data px30_vop_big = { 584 .version = VOP_VERSION(2, 6), 585 .max_output = {1920, 1080}, 586 .ctrl = &px30_ctrl_data, 587 .grf_ctrl = &px30_grf_ctrl, 588 .win = &rk3366_win0_data, 589 .line_flag = &rk3366_vop_lite_line_flag, 590 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 591 }; 592 593 static const struct vop_ctrl rk3308_ctrl_data = { 594 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 595 .axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16), 596 .axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12), 597 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 598 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 599 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 600 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 601 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 602 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 603 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 604 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 605 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 3), 606 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 607 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 608 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 609 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 610 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 611 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 612 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6), 613 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 614 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 615 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 616 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 617 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 618 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 619 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 620 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 621 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 622 623 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 624 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 625 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 626 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 627 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 628 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 629 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 630 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 631 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 632 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 633 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 634 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 635 636 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), 637 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), 638 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), 639 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), 640 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), 641 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), 642 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), 643 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), 644 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), 645 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), 646 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), 647 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, 648 0xffffffff, 0), 649 }; 650 651 const struct vop_data rk3308_vop = { 652 .version = VOP_VERSION(2, 7), 653 .max_output = {1920, 1080}, 654 .ctrl = &rk3308_ctrl_data, 655 .win = &rk3366_win0_data, 656 .line_flag = &rk3366_vop_lite_line_flag, 657 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 658 }; 659 660 const struct vop_data rv1108_vop = { 661 .version = VOP_VERSION(2, 4), 662 .max_output = {1920, 1080}, 663 .ctrl = &rk3308_ctrl_data, 664 .win = &rk3366_win0_data, 665 .line_flag = &rk3366_vop_lite_line_flag, 666 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 667 }; 668