1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <linux/list.h> 14 15 #include "rockchip_vop.h" 16 #include "rockchip_vop_reg.h" 17 18 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \ 19 _begin_minor, _end_minor) \ 20 {.offset = off, \ 21 .mask = _mask, \ 22 .shift = s, \ 23 .write_mask = _write_mask, \ 24 .major = _major, \ 25 .begin_minor = _begin_minor, \ 26 .end_minor = _end_minor,} 27 28 #define VOP_REG(off, _mask, s) \ 29 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1) 30 31 #define VOP_REG_MASK(off, _mask, s) \ 32 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1) 33 34 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \ 35 VOP_REG_VER_MASK(off, _mask, s, false, \ 36 _major, _begin_minor, _end_minor) 37 38 static const struct vop_scl_extension rk3288_win_full_scl_ext = { 39 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), 40 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), 41 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28), 42 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26), 43 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24), 44 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23), 45 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22), 46 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20), 47 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18), 48 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16), 49 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15), 50 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12), 51 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8), 52 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7), 53 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6), 54 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5), 55 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4), 56 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2), 57 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1), 58 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0), 59 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5), 60 }; 61 62 static const struct vop_scl_regs rk3288_win_full_scl = { 63 .ext = &rk3288_win_full_scl_ext, 64 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 65 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 66 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 67 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 68 }; 69 70 static const struct vop_win rk3288_win01_data = { 71 .scl = &rk3288_win_full_scl, 72 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), 73 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), 74 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), 75 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1), 76 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), 77 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), 78 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0), 79 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0), 80 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0), 81 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0), 82 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), 83 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0), 84 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0), 85 }; 86 87 static const struct vop_ctrl rk3288_ctrl_data = { 88 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22), 89 .axi_outstanding_max_num = VOP_REG(RK3288_SYS_CTRL1, 0x1f, 13), 90 .axi_max_outstanding_en = VOP_REG(RK3288_SYS_CTRL1, 0x1, 12), 91 .reg_done_frm = VOP_REG_VER(RK3288_SYS_CTRL1, 0x1, 24, 3, 7, -1), 92 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 93 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), 94 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 95 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), 96 .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 97 .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 98 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 99 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 100 .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 101 .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 102 .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0), 103 104 .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10), 105 .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), 106 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8), 107 .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1), 108 .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1), 109 .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1), 110 .core_dclk_div = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 4, 3, 4, -1), 111 .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1), 112 .dclk_ddr = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 8, 3, 4, -1), 113 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 114 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 115 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 116 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 117 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 118 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), 119 .data01_swap = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 17, 3, 5, -1), 120 .dclk_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x1, 7, 3, 0, 1), 121 .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1), 122 .dp_dclk_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x1, 19, 3, 5, -1), 123 .dp_pin_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x7, 16, 3, 5, -1), 124 .rgb_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 19, 3, 2, -1), 125 .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 16, 3, 2, -1), 126 .tve_dclk_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 24), 127 .tve_dclk_pol = VOP_REG(RK3288_SYS_CTRL, 0x1, 25), 128 .tve_sw_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 26), 129 .sw_uv_offset_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 27), 130 .sw_genlock = VOP_REG(RK3288_SYS_CTRL, 0x1, 28), 131 .hdmi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 23, 3, 2, -1), 132 .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 20, 3, 2, -1), 133 .edp_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 27, 3, 2, -1), 134 .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 24, 3, 2, -1), 135 .mipi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 31, 3, 2, -1), 136 .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 28, 3, 2, -1), 137 138 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1), 139 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), 140 141 .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1), 142 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), 143 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20), 144 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), 145 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0), 146 .update_gamma_lut = VOP_REG_VER(RK3288_DSP_CTRL1, 0x1, 7, 3, 5, -1), 147 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), 148 149 .bcsh_brightness = VOP_REG(RK3288_BCSH_BCS, 0xff, 0), 150 .bcsh_contrast = VOP_REG(RK3288_BCSH_BCS, 0x1ff, 8), 151 .bcsh_sat_con = VOP_REG(RK3288_BCSH_BCS, 0x3ff, 20), 152 .bcsh_out_mode = VOP_REG(RK3288_BCSH_BCS, 0x3, 0), 153 .bcsh_sin_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 0), 154 .bcsh_cos_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 16), 155 .bcsh_r2y_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 6, 3, 1, -1), 156 .bcsh_r2y_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 4, 3, 1, -1), 157 .bcsh_y2r_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x3, 2, 3, 1, -1), 158 .bcsh_y2r_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 0, 3, 1, -1), 159 .bcsh_color_bar = VOP_REG(RK3288_BCSH_COLOR_BAR, 0xffffff, 8), 160 .bcsh_en = VOP_REG(RK3288_BCSH_COLOR_BAR, 0x1, 0), 161 162 .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22), 163 .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23), 164 165 .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), 166 167 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0), 168 .win_gate[0] = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), 169 .win_gate[1] = VOP_REG(RK3288_WIN3_CTRL0, 0x1, 0), 170 }; 171 172 static const struct vop_line_flag rk3288_vop_line_flag = { 173 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), 174 }; 175 176 static const struct vop_grf_ctrl rk3288_vop_big_grf_ctrl = { 177 .grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 12), 178 }; 179 180 static const struct vop_grf_ctrl rk3288_vop_lit_grf_ctrl = { 181 .grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 14), 182 }; 183 184 const struct vop_data rk3288_vop_big = { 185 .version = VOP_VERSION(3, 1), 186 .max_output = {3840, 2160}, 187 .feature = VOP_FEATURE_OUTPUT_10BIT, 188 .ctrl = &rk3288_ctrl_data, 189 .grf_ctrl = &rk3288_vop_big_grf_ctrl, 190 .win = &rk3288_win01_data, 191 .line_flag = &rk3288_vop_line_flag, 192 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 193 }; 194 195 const struct vop_data rk3288_vop_lit = { 196 .version = VOP_VERSION(3, 1), 197 .max_output = {2560, 1600}, 198 .feature = VOP_FEATURE_OUTPUT_10BIT, 199 .ctrl = &rk3288_ctrl_data, 200 .grf_ctrl = &rk3288_vop_lit_grf_ctrl, 201 .win = &rk3288_win01_data, 202 .line_flag = &rk3288_vop_line_flag, 203 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 204 }; 205 206 static const struct vop_line_flag rk3368_vop_line_flag = { 207 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), 208 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), 209 }; 210 211 static const struct vop_grf_ctrl rk3368_vop_grf_ctrl = { 212 .grf_dclk_inv = VOP_REG(RK3368_GRF_SOC_CON6, 0x1, 5), 213 }; 214 215 const struct vop_data rk3368_vop = { 216 .version = VOP_VERSION(3, 2), 217 .max_output = {4096, 2160}, 218 .ctrl = &rk3288_ctrl_data, 219 .grf_ctrl = &rk3368_vop_grf_ctrl, 220 .win = &rk3288_win01_data, 221 .line_flag = &rk3368_vop_line_flag, 222 .reg_len = RK3368_DSP_VACT_ST_END_F1 * 4, 223 }; 224 225 static const struct vop_line_flag rk3366_vop_line_flag = { 226 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), 227 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), 228 }; 229 230 const struct vop_data rk3366_vop = { 231 .version = VOP_VERSION(3, 4), 232 .max_output = {4096, 2160}, 233 .ctrl = &rk3288_ctrl_data, 234 .win = &rk3288_win01_data, 235 .line_flag = &rk3366_vop_line_flag, 236 .reg_len = RK3366_DSP_VACT_ST_END_F1 * 4, 237 }; 238 239 static const uint32_t vop_csc_r2y_bt601[] = { 240 0x02590132, 0xff530075, 0x0200fead, 0xfe530200, 241 0x0000ffad, 0x00000200, 0x00080200, 0x00080200, 242 }; 243 244 static const uint32_t vop_csc_r2y_bt601_12_235[] = { 245 0x02040107, 0xff680064, 0x01c2fed6, 0xffb7fe87, 246 0x0000ffb7, 0x00010200, 0x00080200, 0x00080200, 247 }; 248 249 static const uint32_t vop_csc_r2y_bt709[] = { 250 0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2, 251 0x0000ffd7, 0x00010200, 0x00080200, 0x00080200, 252 }; 253 254 static const uint32_t vop_csc_r2y_bt2020[] = { 255 0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1, 256 0x0000ffdc, 0x00010200, 0x00080200, 0x00080200, 257 }; 258 259 static const struct vop_csc_table rk3399_csc_table = { 260 .r2y_bt601 = vop_csc_r2y_bt601, 261 .r2y_bt601_12_235 = vop_csc_r2y_bt601_12_235, 262 .r2y_bt709 = vop_csc_r2y_bt709, 263 .r2y_bt2020 = vop_csc_r2y_bt2020, 264 }; 265 266 static const struct vop_csc rk3399_win0_csc = { 267 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0), 268 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1), 269 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2), 270 .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R, 271 .r2r_offset = RK3399_WIN0_YUV2YUV_3X3, 272 .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y, 273 }; 274 275 const struct vop_data rk3399_vop_big = { 276 .version = VOP_VERSION(3, 5), 277 .max_output = {4096, 2160}, 278 .feature = VOP_FEATURE_OUTPUT_10BIT, 279 .ctrl = &rk3288_ctrl_data, 280 .win = &rk3288_win01_data, 281 .line_flag = &rk3366_vop_line_flag, 282 .csc_table = &rk3399_csc_table, 283 .win_csc = &rk3399_win0_csc, 284 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 285 }; 286 287 const struct vop_data rk3399_vop_lit = { 288 .version = VOP_VERSION(3, 6), 289 .max_output = {2560, 1600}, 290 .ctrl = &rk3288_ctrl_data, 291 .win = &rk3288_win01_data, 292 .line_flag = &rk3366_vop_line_flag, 293 .csc_table = &rk3399_csc_table, 294 .win_csc = &rk3399_win0_csc, 295 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 296 }; 297 298 const struct vop_data rk322x_vop = { 299 .version = VOP_VERSION(3, 7), 300 .max_output = {4096, 2160}, 301 .feature = VOP_FEATURE_OUTPUT_10BIT, 302 .ctrl = &rk3288_ctrl_data, 303 .win = &rk3288_win01_data, 304 .line_flag = &rk3366_vop_line_flag, 305 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 306 }; 307 308 static const struct vop_ctrl rk3328_ctrl_data = { 309 .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22), 310 .axi_outstanding_max_num = VOP_REG(RK3328_SYS_CTRL1, 0x1f, 13), 311 .axi_max_outstanding_en = VOP_REG(RK3328_SYS_CTRL1, 0x1, 12), 312 .reg_done_frm = VOP_REG(RK3328_SYS_CTRL1, 0x1, 24), 313 .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23), 314 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 315 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), 316 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 317 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), 318 .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 319 .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 320 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 321 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 322 .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 323 .post_scl_factor = VOP_REG(RK3328_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 324 .post_scl_ctrl = VOP_REG(RK3328_POST_SCL_CTRL, 0x3, 0), 325 .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2), 326 .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10), 327 .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8), 328 .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18), 329 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), 330 .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), 331 .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4), 332 .dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8), 333 .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5), 334 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 335 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 336 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 337 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 338 .tve_dclk_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 24), 339 .tve_dclk_pol = VOP_REG(RK3328_SYS_CTRL, 0x1, 25), 340 .tve_sw_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 26), 341 .sw_uv_offset_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 27), 342 .sw_genlock = VOP_REG(RK3328_SYS_CTRL, 0x1, 28), 343 .sw_dac_sel = VOP_REG(RK3328_SYS_CTRL, 0x1, 29), 344 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), 345 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), 346 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), 347 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), 348 349 .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1), 350 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), 351 352 .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12), 353 .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20), 354 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), 355 .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0), 356 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), 357 358 .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22), 359 .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23), 360 361 .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0), 362 363 .bcsh_brightness = VOP_REG(RK3328_BCSH_BCS, 0xff, 0), 364 .bcsh_contrast = VOP_REG(RK3328_BCSH_BCS, 0x1ff, 8), 365 .bcsh_sat_con = VOP_REG(RK3328_BCSH_BCS, 0x3ff, 20), 366 .bcsh_out_mode = VOP_REG(RK3328_BCSH_BCS, 0x3, 30), 367 .bcsh_sin_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 0), 368 .bcsh_cos_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 16), 369 .bcsh_r2y_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 6), 370 .bcsh_r2y_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 4), 371 .bcsh_y2r_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 2), 372 .bcsh_y2r_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 0), 373 .bcsh_color_bar = VOP_REG(RK3328_BCSH_COLOR_BAR, 0xffffff, 8), 374 .bcsh_en = VOP_REG(RK3328_BCSH_COLOR_BAR, 0x1, 0), 375 .win_channel[0] = VOP_REG_VER(RK3328_WIN0_CTRL2, 0xff, 0, 3, 8, 8), 376 .win_channel[1] = VOP_REG_VER(RK3328_WIN1_CTRL2, 0xff, 0, 3, 8, 8), 377 .win_channel[2] = VOP_REG_VER(RK3328_WIN2_CTRL2, 0xff, 0, 3, 8, 8), 378 379 .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0), 380 }; 381 382 383 static const struct vop_line_flag rk3328_vop_line_flag = { 384 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), 385 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), 386 }; 387 388 const struct vop_data rk3328_vop = { 389 .version = VOP_VERSION(3, 8), 390 .max_output = {4096, 2160}, 391 .feature = VOP_FEATURE_OUTPUT_10BIT, 392 .ctrl = &rk3328_ctrl_data, 393 .win = &rk3288_win01_data, 394 .win_offset = 0xd0, 395 .line_flag = &rk3328_vop_line_flag, 396 .reg_len = RK3328_DSP_VACT_ST_END_F1 * 4, 397 }; 398 399 static const struct vop_scl_regs rk3036_win_scl = { 400 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 401 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 402 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 403 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 404 }; 405 406 static const struct vop_win rk3036_win0_data = { 407 .scl = &rk3036_win_scl, 408 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), 409 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), 410 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), 411 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), 412 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), 413 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), 414 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), 415 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), 416 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), 417 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), 418 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18), 419 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0) 420 }; 421 422 static const struct vop_ctrl rk3036_ctrl_data = { 423 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), 424 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), 425 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), 426 .dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7), 427 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), 428 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8), 429 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 430 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), 431 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 432 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), 433 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), 434 }; 435 436 static const struct vop_line_flag rk3036_vop_line_flag = { 437 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), 438 }; 439 440 const struct vop_data rk3036_vop = { 441 .version = VOP_VERSION(2, 2), 442 .max_output = {1920, 1080}, 443 .ctrl = &rk3036_ctrl_data, 444 .win = &rk3036_win0_data, 445 .line_flag = &rk3036_vop_line_flag, 446 .reg_len = RK3036_DSP_VACT_ST_END_F1 * 4, 447 }; 448 449 static const struct vop_scl_regs rk3366_lit_win_scl = { 450 .scale_yrgb_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 451 .scale_yrgb_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 452 .scale_cbcr_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 453 .scale_cbcr_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 454 }; 455 456 static const struct vop_win rk3366_win0_data = { 457 .scl = &rk3366_lit_win_scl, 458 459 .enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0), 460 .format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1), 461 .rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12), 462 .act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0), 463 .dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0), 464 .dsp_st = VOP_REG(RK3366_LIT_WIN0_DSP_ST, 0xffffffff, 0), 465 .yrgb_mst = VOP_REG(RK3366_LIT_WIN0_YRGB_MST0, 0xffffffff, 0), 466 .uv_mst = VOP_REG(RK3366_LIT_WIN0_CBR_MST0, 0xffffffff, 0), 467 .yrgb_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 0), 468 .uv_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 16), 469 470 .alpha_mode = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 1), 471 .alpha_en = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 0), 472 }; 473 474 static const struct vop_win rk3366_win1_data = { 475 .enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0), 476 .format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4), 477 .rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12), 478 .dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0), 479 .dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0), 480 .yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0), 481 .yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0), 482 483 .alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1), 484 .alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0), 485 }; 486 487 static const struct vop_ctrl px30_ctrl_data = { 488 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 489 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 490 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 491 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 492 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 493 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 494 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 495 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0), 496 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 497 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 498 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 22), 499 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 500 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13), 501 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 502 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 503 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 504 .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8), 505 .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10), 506 .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16), 507 .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18), 508 .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24), 509 .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26), 510 .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25), 511 .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17), 512 .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9), 513 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 514 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 515 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6), 516 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 517 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 518 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 519 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 520 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 521 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 522 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 523 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 524 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 525 526 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 527 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 528 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 529 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 530 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 531 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 532 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 533 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 534 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 535 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 536 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 537 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 538 539 .cabc_config_mode = VOP_REG(PX30_CABC_CTRL0, 0x3, 2), 540 .cabc_calc_pixel_num = VOP_REG(PX30_CABC_CTRL0, 0x7fffff, 4), 541 .cabc_handle_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 1), 542 .cabc_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 0), 543 .cabc_total_num = VOP_REG(PX30_CABC_CTRL1, 0x7fffff, 4), 544 .cabc_lut_en = VOP_REG(PX30_CABC_CTRL1, 0x1, 0), 545 .cabc_stage_up_mode = VOP_REG(PX30_CABC_CTRL2, 0x1, 19), 546 .cabc_stage_up = VOP_REG(PX30_CABC_CTRL2, 0x1ff, 8), 547 .cabc_stage_down = VOP_REG(PX30_CABC_CTRL2, 0xff, 0), 548 .cabc_global_dn = VOP_REG(PX30_CABC_CTRL3, 0xff, 0), 549 .cabc_global_dn_limit_en = VOP_REG(PX30_CABC_CTRL3, 0x1, 8), 550 551 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), 552 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), 553 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), 554 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), 555 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), 556 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), 557 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), 558 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), 559 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), 560 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), 561 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), 562 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, 563 0xffffffff, 0), 564 }; 565 566 static const struct vop_line_flag rk3366_vop_lite_line_flag = { 567 .line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0), 568 }; 569 570 static const struct vop_grf_ctrl px30_grf_ctrl = { 571 .grf_dclk_inv = VOP_REG(PX30_GRF_PD_VO_CON1, 0x1, 4), 572 }; 573 574 const struct vop_data px30_vop_lit = { 575 .version = VOP_VERSION(2, 5), 576 .max_output = {1920, 1080}, 577 .ctrl = &px30_ctrl_data, 578 .grf_ctrl = &px30_grf_ctrl, 579 .win = &rk3366_win1_data, 580 .line_flag = &rk3366_vop_lite_line_flag, 581 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 582 }; 583 584 const struct vop_data px30_vop_big = { 585 .version = VOP_VERSION(2, 6), 586 .max_output = {1920, 1080}, 587 .ctrl = &px30_ctrl_data, 588 .grf_ctrl = &px30_grf_ctrl, 589 .win = &rk3366_win0_data, 590 .line_flag = &rk3366_vop_lite_line_flag, 591 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 592 }; 593 594 static const struct vop_ctrl rk3308_ctrl_data = { 595 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 596 .axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16), 597 .axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12), 598 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 599 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 600 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 601 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 602 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 603 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 604 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 605 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 606 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 3), 607 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 608 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 609 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 610 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 611 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 612 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 613 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6), 614 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 615 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 616 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 617 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 618 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 619 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 620 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 621 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 622 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 623 624 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 625 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 626 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 627 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 628 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 629 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 630 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 631 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 632 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 633 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 634 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 635 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 636 637 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), 638 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), 639 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), 640 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), 641 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), 642 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), 643 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), 644 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), 645 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), 646 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), 647 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), 648 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, 649 0xffffffff, 0), 650 }; 651 652 const struct vop_data rk3308_vop = { 653 .version = VOP_VERSION(2, 7), 654 .max_output = {1920, 1080}, 655 .ctrl = &rk3308_ctrl_data, 656 .win = &rk3366_win0_data, 657 .line_flag = &rk3366_vop_lite_line_flag, 658 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 659 }; 660 661 const struct vop_data rv1108_vop = { 662 .version = VOP_VERSION(2, 4), 663 .max_output = {1920, 1080}, 664 .ctrl = &rk3308_ctrl_data, 665 .win = &rk3366_win0_data, 666 .line_flag = &rk3366_vop_lite_line_flag, 667 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 668 }; 669