1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <linux/list.h> 14 15 #include "rockchip_vop.h" 16 #include "rockchip_vop_reg.h" 17 18 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \ 19 _begin_minor, _end_minor) \ 20 {.offset = off, \ 21 .mask = _mask, \ 22 .shift = s, \ 23 .write_mask = _write_mask, \ 24 .major = _major, \ 25 .begin_minor = _begin_minor, \ 26 .end_minor = _end_minor,} 27 28 #define VOP_REG(off, _mask, s) \ 29 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1) 30 31 #define VOP_REG_MASK(off, _mask, s) \ 32 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1) 33 34 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \ 35 VOP_REG_VER_MASK(off, _mask, s, false, \ 36 _major, _begin_minor, _end_minor) 37 38 static const struct vop_scl_extension rk3288_win_full_scl_ext = { 39 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), 40 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), 41 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28), 42 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26), 43 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24), 44 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23), 45 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22), 46 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20), 47 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18), 48 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16), 49 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15), 50 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12), 51 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8), 52 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7), 53 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6), 54 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5), 55 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4), 56 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2), 57 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1), 58 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0), 59 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5), 60 }; 61 62 static const struct vop_scl_regs rk3288_win_full_scl = { 63 .ext = &rk3288_win_full_scl_ext, 64 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 65 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 66 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 67 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 68 }; 69 70 static const struct vop_win rk3288_win01_data = { 71 .scl = &rk3288_win_full_scl, 72 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), 73 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), 74 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), 75 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1), 76 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), 77 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), 78 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0), 79 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0), 80 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0), 81 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0), 82 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), 83 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0), 84 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0), 85 }; 86 87 static const struct vop_ctrl rk3288_ctrl_data = { 88 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22), 89 .axi_outstanding_max_num = VOP_REG(RK3288_SYS_CTRL1, 0x1f, 13), 90 .axi_max_outstanding_en = VOP_REG(RK3288_SYS_CTRL1, 0x1, 12), 91 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 92 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), 93 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 94 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), 95 .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 96 .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 97 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 98 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 99 .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 100 .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 101 .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0), 102 103 .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10), 104 .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), 105 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8), 106 .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1), 107 .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1), 108 .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1), 109 .core_dclk_div = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 4, 3, 4, -1), 110 .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1), 111 .dclk_ddr = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 8, 3, 4, -1), 112 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 113 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 114 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 115 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 116 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 117 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), 118 .data01_swap = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 17, 3, 5, -1), 119 .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1), 120 .dp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1), 121 .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1), 122 .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1), 123 .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1), 124 .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1), 125 126 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1), 127 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), 128 129 .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1), 130 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), 131 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20), 132 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), 133 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0), 134 .update_gamma_lut = VOP_REG_VER(RK3288_DSP_CTRL1, 0x1, 7, 3, 5, -1), 135 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), 136 137 .bcsh_brightness = VOP_REG(RK3288_BCSH_BCS, 0xff, 0), 138 .bcsh_contrast = VOP_REG(RK3288_BCSH_BCS, 0x1ff, 8), 139 .bcsh_sat_con = VOP_REG(RK3288_BCSH_BCS, 0x3ff, 20), 140 .bcsh_out_mode = VOP_REG(RK3288_BCSH_BCS, 0x3, 0), 141 .bcsh_sin_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 0), 142 .bcsh_cos_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 16), 143 .bcsh_r2y_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 6, 3, 1, -1), 144 .bcsh_r2y_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 4, 3, 1, -1), 145 .bcsh_y2r_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x3, 2, 3, 1, -1), 146 .bcsh_y2r_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 0, 3, 1, -1), 147 .bcsh_color_bar = VOP_REG(RK3288_BCSH_COLOR_BAR, 0xffffff, 8), 148 .bcsh_en = VOP_REG(RK3288_BCSH_COLOR_BAR, 0x1, 0), 149 150 .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22), 151 .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23), 152 153 .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), 154 155 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0), 156 .win_gate[0] = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), 157 .win_gate[1] = VOP_REG(RK3288_WIN3_CTRL0, 0x1, 0), 158 }; 159 160 static const struct vop_line_flag rk3288_vop_line_flag = { 161 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), 162 }; 163 164 const struct vop_data rk3288_vop_big = { 165 .version = VOP_VERSION(3, 1), 166 .max_output = {3840, 2160}, 167 .feature = VOP_FEATURE_OUTPUT_10BIT, 168 .ctrl = &rk3288_ctrl_data, 169 .win = &rk3288_win01_data, 170 .line_flag = &rk3288_vop_line_flag, 171 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 172 }; 173 174 const struct vop_data rk3288_vop_lit = { 175 .version = VOP_VERSION(3, 1), 176 .max_output = {2560, 1600}, 177 .feature = VOP_FEATURE_OUTPUT_10BIT, 178 .ctrl = &rk3288_ctrl_data, 179 .win = &rk3288_win01_data, 180 .line_flag = &rk3288_vop_line_flag, 181 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 182 }; 183 184 static const struct vop_line_flag rk3368_vop_line_flag = { 185 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), 186 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), 187 }; 188 189 const struct vop_data rk3368_vop = { 190 .version = VOP_VERSION(3, 2), 191 .max_output = {4096, 2160}, 192 .ctrl = &rk3288_ctrl_data, 193 .win = &rk3288_win01_data, 194 .line_flag = &rk3368_vop_line_flag, 195 .reg_len = RK3368_DSP_VACT_ST_END_F1 * 4, 196 }; 197 198 static const struct vop_line_flag rk3366_vop_line_flag = { 199 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), 200 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), 201 }; 202 203 const struct vop_data rk3366_vop = { 204 .version = VOP_VERSION(3, 4), 205 .max_output = {4096, 2160}, 206 .ctrl = &rk3288_ctrl_data, 207 .win = &rk3288_win01_data, 208 .line_flag = &rk3366_vop_line_flag, 209 .reg_len = RK3366_DSP_VACT_ST_END_F1 * 4, 210 }; 211 212 const struct vop_data rk3399_vop_big = { 213 .version = VOP_VERSION(3, 5), 214 .max_output = {4096, 2160}, 215 .feature = VOP_FEATURE_OUTPUT_10BIT, 216 .ctrl = &rk3288_ctrl_data, 217 .win = &rk3288_win01_data, 218 .line_flag = &rk3366_vop_line_flag, 219 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 220 }; 221 222 const struct vop_data rk3399_vop_lit = { 223 .version = VOP_VERSION(3, 6), 224 .max_output = {2560, 1600}, 225 .ctrl = &rk3288_ctrl_data, 226 .win = &rk3288_win01_data, 227 .line_flag = &rk3366_vop_line_flag, 228 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 229 }; 230 231 const struct vop_data rk322x_vop = { 232 .version = VOP_VERSION(3, 7), 233 .max_output = {4096, 2160}, 234 .feature = VOP_FEATURE_OUTPUT_10BIT, 235 .ctrl = &rk3288_ctrl_data, 236 .win = &rk3288_win01_data, 237 .line_flag = &rk3366_vop_line_flag, 238 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 239 }; 240 241 static const struct vop_ctrl rk3328_ctrl_data = { 242 .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22), 243 .axi_outstanding_max_num = VOP_REG(RK3328_SYS_CTRL1, 0x1f, 13), 244 .axi_max_outstanding_en = VOP_REG(RK3328_SYS_CTRL1, 0x1, 12), 245 .reg_done_frm = VOP_REG(RK3328_SYS_CTRL1, 0x1, 24), 246 .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23), 247 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 248 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), 249 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 250 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), 251 .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 252 .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 253 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 254 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 255 .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 256 .post_scl_factor = VOP_REG(RK3328_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 257 .post_scl_ctrl = VOP_REG(RK3328_POST_SCL_CTRL, 0x3, 0), 258 .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2), 259 .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10), 260 .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8), 261 .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18), 262 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), 263 .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), 264 .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4), 265 .dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8), 266 .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5), 267 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 268 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 269 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 270 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 271 .tve_dclk_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 24), 272 .tve_dclk_pol = VOP_REG(RK3328_SYS_CTRL, 0x1, 25), 273 .tve_sw_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 26), 274 .sw_uv_offset_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 27), 275 .sw_genlock = VOP_REG(RK3328_SYS_CTRL, 0x1, 28), 276 .sw_dac_sel = VOP_REG(RK3328_SYS_CTRL, 0x1, 29), 277 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), 278 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), 279 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), 280 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), 281 282 .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1), 283 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), 284 285 .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12), 286 .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20), 287 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), 288 .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0), 289 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), 290 291 .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22), 292 .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23), 293 294 .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0), 295 296 .bcsh_brightness = VOP_REG(RK3328_BCSH_BCS, 0xff, 0), 297 .bcsh_contrast = VOP_REG(RK3328_BCSH_BCS, 0x1ff, 8), 298 .bcsh_sat_con = VOP_REG(RK3328_BCSH_BCS, 0x3ff, 20), 299 .bcsh_out_mode = VOP_REG(RK3328_BCSH_BCS, 0x3, 30), 300 .bcsh_sin_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 0), 301 .bcsh_cos_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 16), 302 .bcsh_r2y_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 6), 303 .bcsh_r2y_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 4), 304 .bcsh_y2r_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 2), 305 .bcsh_y2r_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 0), 306 .bcsh_color_bar = VOP_REG(RK3328_BCSH_COLOR_BAR, 0xffffff, 8), 307 .bcsh_en = VOP_REG(RK3328_BCSH_COLOR_BAR, 0x1, 0), 308 .win_channel[0] = VOP_REG_VER(RK3328_WIN0_CTRL2, 0xff, 0, 3, 8, 8), 309 .win_channel[1] = VOP_REG_VER(RK3328_WIN1_CTRL2, 0xff, 0, 3, 8, 8), 310 .win_channel[2] = VOP_REG_VER(RK3328_WIN2_CTRL2, 0xff, 0, 3, 8, 8), 311 312 .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0), 313 }; 314 315 316 static const struct vop_line_flag rk3328_vop_line_flag = { 317 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), 318 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), 319 }; 320 321 const struct vop_data rk3328_vop = { 322 .version = VOP_VERSION(3, 8), 323 .max_output = {4096, 2160}, 324 .feature = VOP_FEATURE_OUTPUT_10BIT, 325 .ctrl = &rk3328_ctrl_data, 326 .win = &rk3288_win01_data, 327 .win_offset = 0xd0, 328 .line_flag = &rk3328_vop_line_flag, 329 .reg_len = RK3328_DSP_VACT_ST_END_F1 * 4, 330 }; 331 332 static const struct vop_scl_regs rk3036_win_scl = { 333 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 334 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 335 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 336 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 337 }; 338 339 static const struct vop_win rk3036_win0_data = { 340 .scl = &rk3036_win_scl, 341 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), 342 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), 343 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), 344 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), 345 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), 346 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), 347 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), 348 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), 349 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), 350 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), 351 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18), 352 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0) 353 }; 354 355 static const struct vop_ctrl rk3036_ctrl_data = { 356 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), 357 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), 358 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), 359 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), 360 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8), 361 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 362 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), 363 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 364 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), 365 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), 366 }; 367 368 static const struct vop_line_flag rk3036_vop_line_flag = { 369 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), 370 }; 371 372 const struct vop_data rk3036_vop = { 373 .version = VOP_VERSION(2, 2), 374 .max_output = {1920, 1080}, 375 .ctrl = &rk3036_ctrl_data, 376 .win = &rk3036_win0_data, 377 .line_flag = &rk3036_vop_line_flag, 378 .reg_len = RK3036_DSP_VACT_ST_END_F1 * 4, 379 }; 380 381 static const struct vop_scl_regs rk3366_lit_win_scl = { 382 .scale_yrgb_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 383 .scale_yrgb_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 384 .scale_cbcr_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 385 .scale_cbcr_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 386 }; 387 388 static const struct vop_win rk3366_win0_data = { 389 .scl = &rk3366_lit_win_scl, 390 391 .enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0), 392 .format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1), 393 .rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12), 394 .act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0), 395 .dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0), 396 .dsp_st = VOP_REG(RK3366_LIT_WIN0_DSP_ST, 0xffffffff, 0), 397 .yrgb_mst = VOP_REG(RK3366_LIT_WIN0_YRGB_MST0, 0xffffffff, 0), 398 .uv_mst = VOP_REG(RK3366_LIT_WIN0_CBR_MST0, 0xffffffff, 0), 399 .yrgb_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 0), 400 .uv_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 16), 401 402 .alpha_mode = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 1), 403 .alpha_en = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 0), 404 }; 405 406 static const struct vop_win rk3366_win1_data = { 407 .enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0), 408 .format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4), 409 .rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12), 410 .dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0), 411 .dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0), 412 .yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0), 413 .yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0), 414 415 .alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1), 416 .alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0), 417 }; 418 419 static const struct vop_ctrl px30_ctrl_data = { 420 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 421 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 422 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 423 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 424 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 425 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 426 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 427 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0), 428 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 429 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 430 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 22), 431 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 432 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13), 433 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 434 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 435 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 436 .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8), 437 .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10), 438 .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16), 439 .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18), 440 .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24), 441 .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26), 442 .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25), 443 .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17), 444 .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9), 445 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 446 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 447 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6), 448 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 449 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 450 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 451 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 452 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 453 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 454 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 455 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 456 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 457 458 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 459 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 460 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 461 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 462 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 463 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 464 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 465 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 466 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 467 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 468 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 469 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 470 471 .cabc_config_mode = VOP_REG(PX30_CABC_CTRL0, 0x3, 2), 472 .cabc_calc_pixel_num = VOP_REG(PX30_CABC_CTRL0, 0x7fffff, 4), 473 .cabc_handle_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 1), 474 .cabc_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 0), 475 .cabc_total_num = VOP_REG(PX30_CABC_CTRL1, 0x7fffff, 4), 476 .cabc_lut_en = VOP_REG(PX30_CABC_CTRL1, 0x1, 0), 477 .cabc_stage_up_mode = VOP_REG(PX30_CABC_CTRL2, 0x1, 19), 478 .cabc_stage_up = VOP_REG(PX30_CABC_CTRL2, 0x1ff, 8), 479 .cabc_stage_down = VOP_REG(PX30_CABC_CTRL2, 0xff, 0), 480 .cabc_global_dn = VOP_REG(PX30_CABC_CTRL3, 0xff, 0), 481 .cabc_global_dn_limit_en = VOP_REG(PX30_CABC_CTRL3, 0x1, 8), 482 }; 483 484 static const struct vop_line_flag rk3366_vop_lite_line_flag = { 485 .line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0), 486 }; 487 488 const struct vop_data px30_vop_lit = { 489 .version = VOP_VERSION(2, 5), 490 .max_output = {1920, 1080}, 491 .ctrl = &px30_ctrl_data, 492 .win = &rk3366_win1_data, 493 .line_flag = &rk3366_vop_lite_line_flag, 494 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 495 }; 496 497 const struct vop_data px30_vop_big = { 498 .version = VOP_VERSION(2, 6), 499 .max_output = {1920, 1080}, 500 .ctrl = &px30_ctrl_data, 501 .win = &rk3366_win0_data, 502 .line_flag = &rk3366_vop_lite_line_flag, 503 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 504 }; 505