1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <linux/list.h> 14 15 #include "rockchip_vop.h" 16 #include "rockchip_vop_reg.h" 17 18 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \ 19 _begin_minor, _end_minor) \ 20 {.offset = off, \ 21 .mask = _mask, \ 22 .shift = s, \ 23 .write_mask = _write_mask, \ 24 .major = _major, \ 25 .begin_minor = _begin_minor, \ 26 .end_minor = _end_minor,} 27 28 #define VOP_REG(off, _mask, s) \ 29 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1) 30 31 #define VOP_REG_MASK(off, _mask, s) \ 32 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1) 33 34 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \ 35 VOP_REG_VER_MASK(off, _mask, s, false, \ 36 _major, _begin_minor, _end_minor) 37 38 static const struct vop_scl_extension rk3288_win_full_scl_ext = { 39 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), 40 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), 41 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28), 42 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26), 43 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24), 44 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23), 45 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22), 46 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20), 47 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18), 48 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16), 49 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15), 50 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12), 51 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8), 52 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7), 53 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6), 54 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5), 55 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4), 56 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2), 57 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1), 58 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0), 59 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5), 60 }; 61 62 static const struct vop_scl_regs rk3288_win_full_scl = { 63 .ext = &rk3288_win_full_scl_ext, 64 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 65 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 66 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 67 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 68 }; 69 70 static const struct vop_win rk3288_win01_data = { 71 .scl = &rk3288_win_full_scl, 72 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), 73 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), 74 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), 75 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1), 76 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), 77 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), 78 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0), 79 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0), 80 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0), 81 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0), 82 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), 83 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0), 84 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0), 85 }; 86 87 static const struct vop_ctrl rk3288_ctrl_data = { 88 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22), 89 .axi_outstanding_max_num = VOP_REG(RK3288_SYS_CTRL1, 0x1f, 13), 90 .axi_max_outstanding_en = VOP_REG(RK3288_SYS_CTRL1, 0x1, 12), 91 .reg_done_frm = VOP_REG_VER(RK3288_SYS_CTRL1, 0x1, 24, 3, 7, -1), 92 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 93 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), 94 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 95 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), 96 .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 97 .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 98 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 99 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 100 .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 101 .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 102 .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0), 103 104 .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10), 105 .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), 106 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8), 107 .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1), 108 .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1), 109 .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1), 110 .core_dclk_div = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 4, 3, 4, -1), 111 .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1), 112 .dclk_ddr = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 8, 3, 4, -1), 113 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 114 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 115 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 116 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 117 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 118 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), 119 .data01_swap = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 17, 3, 5, -1), 120 .dclk_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x1, 7, 3, 0, 1), 121 .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1), 122 .dp_dclk_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x1, 19, 3, 5, -1), 123 .dp_pin_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x7, 16, 3, 5, -1), 124 .rgb_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 19, 3, 2, -1), 125 .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 16, 3, 2, -1), 126 .tve_dclk_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 24), 127 .tve_dclk_pol = VOP_REG(RK3288_SYS_CTRL, 0x1, 25), 128 .tve_sw_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 26), 129 .sw_uv_offset_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 27), 130 .sw_genlock = VOP_REG(RK3288_SYS_CTRL, 0x1, 28), 131 .hdmi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 23, 3, 2, -1), 132 .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 20, 3, 2, -1), 133 .edp_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 27, 3, 2, -1), 134 .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 24, 3, 2, -1), 135 .mipi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 31, 3, 2, -1), 136 .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 28, 3, 2, -1), 137 138 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1), 139 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), 140 141 .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1), 142 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), 143 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20), 144 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), 145 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0), 146 .update_gamma_lut = VOP_REG_VER(RK3288_DSP_CTRL1, 0x1, 7, 3, 5, -1), 147 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), 148 149 .bcsh_brightness = VOP_REG(RK3288_BCSH_BCS, 0xff, 0), 150 .bcsh_contrast = VOP_REG(RK3288_BCSH_BCS, 0x1ff, 8), 151 .bcsh_sat_con = VOP_REG(RK3288_BCSH_BCS, 0x3ff, 20), 152 .bcsh_out_mode = VOP_REG(RK3288_BCSH_BCS, 0x3, 0), 153 .bcsh_sin_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 0), 154 .bcsh_cos_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 16), 155 .bcsh_r2y_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 6, 3, 1, -1), 156 .bcsh_r2y_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 4, 3, 1, -1), 157 .bcsh_y2r_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x3, 2, 3, 1, -1), 158 .bcsh_y2r_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 0, 3, 1, -1), 159 .bcsh_color_bar = VOP_REG(RK3288_BCSH_COLOR_BAR, 0xffffff, 8), 160 .bcsh_en = VOP_REG(RK3288_BCSH_COLOR_BAR, 0x1, 0), 161 162 .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22), 163 .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23), 164 165 .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), 166 167 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0), 168 .win_gate[0] = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), 169 .win_gate[1] = VOP_REG(RK3288_WIN3_CTRL0, 0x1, 0), 170 171 .mcu_pix_total = VOP_REG(RK3288_MCU_CTRL, 0x3f, 0), 172 .mcu_cs_pst = VOP_REG(RK3288_MCU_CTRL, 0xf, 6), 173 .mcu_cs_pend = VOP_REG(RK3288_MCU_CTRL, 0x3f, 10), 174 .mcu_rw_pst = VOP_REG(RK3288_MCU_CTRL, 0xf, 16), 175 .mcu_rw_pend = VOP_REG(RK3288_MCU_CTRL, 0x3f, 20), 176 .mcu_clk_sel = VOP_REG(RK3288_MCU_CTRL, 0x1, 26), 177 .mcu_hold_mode = VOP_REG(RK3288_MCU_CTRL, 0x1, 27), 178 .mcu_frame_st = VOP_REG(RK3288_MCU_CTRL, 0x1, 28), 179 .mcu_rs = VOP_REG(RK3288_MCU_CTRL, 0x1, 29), 180 .mcu_bypass = VOP_REG(RK3288_MCU_CTRL, 0x1, 30), 181 .mcu_type = VOP_REG(RK3288_MCU_CTRL, 0x1, 31), 182 .mcu_rw_bypass_port = VOP_REG(RK3288_MCU_BYPASS_WPORT, 0xffffffff, 0), 183 }; 184 185 static const struct vop_line_flag rk3288_vop_line_flag = { 186 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), 187 }; 188 189 static const struct vop_grf_ctrl rk3288_vop_big_grf_ctrl = { 190 .grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 13), 191 }; 192 193 static const struct vop_grf_ctrl rk3288_vop_lit_grf_ctrl = { 194 .grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 15), 195 }; 196 197 const struct vop_data rk3288_vop_big = { 198 .version = VOP_VERSION(3, 1), 199 .max_output = {3840, 2160}, 200 .feature = VOP_FEATURE_OUTPUT_10BIT, 201 .ctrl = &rk3288_ctrl_data, 202 .grf_ctrl = &rk3288_vop_big_grf_ctrl, 203 .win = &rk3288_win01_data, 204 .line_flag = &rk3288_vop_line_flag, 205 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 206 }; 207 208 const struct vop_data rk3288_vop_lit = { 209 .version = VOP_VERSION(3, 1), 210 .max_output = {2560, 1600}, 211 .feature = VOP_FEATURE_OUTPUT_10BIT, 212 .ctrl = &rk3288_ctrl_data, 213 .grf_ctrl = &rk3288_vop_lit_grf_ctrl, 214 .win = &rk3288_win01_data, 215 .line_flag = &rk3288_vop_line_flag, 216 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 217 }; 218 219 static const struct vop_win rk3368_win23_data = { 220 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4), 221 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5), 222 .ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15), 223 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20), 224 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0), 225 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0), 226 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0), 227 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0), 228 .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xffff, 0), 229 .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xffffffff, 0), 230 }; 231 232 static const struct vop_line_flag rk3368_vop_line_flag = { 233 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), 234 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), 235 }; 236 237 static const struct vop_grf_ctrl rk3368_vop_grf_ctrl = { 238 .grf_dclk_inv = VOP_REG(RK3368_GRF_SOC_CON6, 0x1, 5), 239 }; 240 241 const struct vop_data rk3368_vop = { 242 .version = VOP_VERSION(3, 2), 243 .max_output = {4096, 2160}, 244 .ctrl = &rk3288_ctrl_data, 245 .grf_ctrl = &rk3368_vop_grf_ctrl, 246 .win = &rk3288_win01_data, 247 .line_flag = &rk3368_vop_line_flag, 248 .reg_len = RK3368_DSP_VACT_ST_END_F1 * 4, 249 }; 250 251 static const struct vop_line_flag rk3366_vop_line_flag = { 252 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), 253 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), 254 }; 255 256 const struct vop_data rk3366_vop = { 257 .version = VOP_VERSION(3, 4), 258 .max_output = {4096, 2160}, 259 .ctrl = &rk3288_ctrl_data, 260 .win = &rk3288_win01_data, 261 .line_flag = &rk3366_vop_line_flag, 262 .reg_len = RK3366_DSP_VACT_ST_END_F1 * 4, 263 }; 264 265 static const uint32_t vop_csc_r2y_bt601[] = { 266 0x02590132, 0xff530075, 0x0200fead, 0xfe530200, 267 0x0000ffad, 0x00000200, 0x00080200, 0x00080200, 268 }; 269 270 static const uint32_t vop_csc_r2y_bt601_12_235[] = { 271 0x02040107, 0xff680064, 0x01c2fed6, 0xfe8701c2, 272 0x0000ffb7, 0x00010200, 0x00080200, 0x00080200, 273 }; 274 275 static const uint32_t vop_csc_r2y_bt709[] = { 276 0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2, 277 0x0000ffd7, 0x00010200, 0x00080200, 0x00080200, 278 }; 279 280 static const uint32_t vop_csc_r2y_bt2020[] = { 281 0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1, 282 0x0000ffdc, 0x00010200, 0x00080200, 0x00080200, 283 }; 284 285 static const struct vop_csc_table rk3399_csc_table = { 286 .r2y_bt601 = vop_csc_r2y_bt601, 287 .r2y_bt601_12_235 = vop_csc_r2y_bt601_12_235, 288 .r2y_bt709 = vop_csc_r2y_bt709, 289 .r2y_bt2020 = vop_csc_r2y_bt2020, 290 }; 291 292 static const struct vop_csc rk3399_win0_csc = { 293 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0), 294 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1), 295 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2), 296 .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R, 297 .r2r_offset = RK3399_WIN0_YUV2YUV_3X3, 298 .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y, 299 }; 300 301 static const struct vop_csc rk3399_win2_csc = { 302 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 16), 303 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 18), 304 .r2r_offset = RK3399_WIN2_YUV2YUV_3X3, 305 306 }; 307 308 const struct vop_data rk3399_vop_big = { 309 .version = VOP_VERSION(3, 5), 310 .max_output = {4096, 2160}, 311 .feature = VOP_FEATURE_OUTPUT_10BIT, 312 .ctrl = &rk3288_ctrl_data, 313 .win = &rk3288_win01_data, 314 .line_flag = &rk3366_vop_line_flag, 315 .csc_table = &rk3399_csc_table, 316 .win_csc = &rk3399_win0_csc, 317 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 318 }; 319 320 const struct vop_data rk3399_vop_lit = { 321 .version = VOP_VERSION(3, 6), 322 .max_output = {2560, 1600}, 323 .ctrl = &rk3288_ctrl_data, 324 .win = &rk3368_win23_data, 325 .line_flag = &rk3366_vop_line_flag, 326 .csc_table = &rk3399_csc_table, 327 .win_csc = &rk3399_win2_csc, 328 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 329 }; 330 331 const struct vop_data rk322x_vop = { 332 .version = VOP_VERSION(3, 7), 333 .max_output = {4096, 2160}, 334 .feature = VOP_FEATURE_OUTPUT_10BIT, 335 .ctrl = &rk3288_ctrl_data, 336 .win = &rk3288_win01_data, 337 .line_flag = &rk3366_vop_line_flag, 338 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 339 }; 340 341 static const struct vop_ctrl rk3328_ctrl_data = { 342 .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22), 343 .axi_outstanding_max_num = VOP_REG(RK3328_SYS_CTRL1, 0x1f, 13), 344 .axi_max_outstanding_en = VOP_REG(RK3328_SYS_CTRL1, 0x1, 12), 345 .reg_done_frm = VOP_REG(RK3328_SYS_CTRL1, 0x1, 24), 346 .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23), 347 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 348 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), 349 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 350 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), 351 .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 352 .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 353 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 354 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 355 .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 356 .post_scl_factor = VOP_REG(RK3328_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 357 .post_scl_ctrl = VOP_REG(RK3328_POST_SCL_CTRL, 0x3, 0), 358 .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2), 359 .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10), 360 .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8), 361 .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18), 362 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), 363 .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), 364 .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4), 365 .dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8), 366 .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5), 367 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 368 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 369 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 370 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 371 .tve_dclk_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 24), 372 .tve_dclk_pol = VOP_REG(RK3328_SYS_CTRL, 0x1, 25), 373 .tve_sw_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 26), 374 .sw_uv_offset_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 27), 375 .sw_genlock = VOP_REG(RK3328_SYS_CTRL, 0x1, 28), 376 .sw_dac_sel = VOP_REG(RK3328_SYS_CTRL, 0x1, 29), 377 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), 378 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), 379 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), 380 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), 381 382 .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1), 383 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), 384 385 .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12), 386 .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20), 387 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), 388 .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0), 389 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), 390 391 .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22), 392 .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23), 393 394 .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0), 395 396 .bcsh_brightness = VOP_REG(RK3328_BCSH_BCS, 0xff, 0), 397 .bcsh_contrast = VOP_REG(RK3328_BCSH_BCS, 0x1ff, 8), 398 .bcsh_sat_con = VOP_REG(RK3328_BCSH_BCS, 0x3ff, 20), 399 .bcsh_out_mode = VOP_REG(RK3328_BCSH_BCS, 0x3, 30), 400 .bcsh_sin_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 0), 401 .bcsh_cos_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 16), 402 .bcsh_r2y_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 6), 403 .bcsh_r2y_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 4), 404 .bcsh_y2r_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 2), 405 .bcsh_y2r_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 0), 406 .bcsh_color_bar = VOP_REG(RK3328_BCSH_COLOR_BAR, 0xffffff, 8), 407 .bcsh_en = VOP_REG(RK3328_BCSH_COLOR_BAR, 0x1, 0), 408 .win_channel[0] = VOP_REG_VER(RK3328_WIN0_CTRL2, 0xff, 0, 3, 8, 8), 409 .win_channel[1] = VOP_REG_VER(RK3328_WIN1_CTRL2, 0xff, 0, 3, 8, 8), 410 .win_channel[2] = VOP_REG_VER(RK3328_WIN2_CTRL2, 0xff, 0, 3, 8, 8), 411 412 .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0), 413 }; 414 415 416 static const struct vop_line_flag rk3328_vop_line_flag = { 417 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), 418 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), 419 }; 420 421 const struct vop_data rk3328_vop = { 422 .version = VOP_VERSION(3, 8), 423 .max_output = {4096, 2160}, 424 .feature = VOP_FEATURE_OUTPUT_10BIT, 425 .ctrl = &rk3328_ctrl_data, 426 .win = &rk3288_win01_data, 427 .win_offset = 0xd0, 428 .line_flag = &rk3328_vop_line_flag, 429 .reg_len = RK3328_DSP_VACT_ST_END_F1 * 4, 430 }; 431 432 static const struct vop_win rk3126_win1_data = { 433 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), 434 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), 435 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), 436 .dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0), 437 .dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0), 438 .yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0), 439 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), 440 }; 441 442 static const struct vop_ctrl rk3036_ctrl_data = { 443 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), 444 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), 445 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), 446 .dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7), 447 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), 448 .dither_down = VOP_REG(RK3036_DSP_CTRL0, 0x3, 10), 449 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8), 450 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 451 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), 452 .hdmi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 22), 453 .hdmi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 23), 454 .hdmi_pin_pol = VOP_REG(RK3036_INT_SCALER, 0x7, 4), 455 .rgb_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 24), 456 .rgb_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 25), 457 .lvds_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 26), 458 .lvds_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 27), 459 .mipi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 28), 460 .mipi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 29), 461 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 462 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), 463 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), 464 }; 465 466 static const struct vop_line_flag rk3036_vop_line_flag = { 467 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), 468 }; 469 470 const struct vop_data rk3036_vop = { 471 .version = VOP_VERSION(2, 2), 472 .max_output = {1920, 1080}, 473 .ctrl = &rk3036_ctrl_data, 474 .win = &rk3126_win1_data, 475 .line_flag = &rk3036_vop_line_flag, 476 .reg_len = RK3036_DSP_VACT_ST_END_F1 * 4, 477 }; 478 479 static const struct vop_scl_regs rk3366_lit_win_scl = { 480 .scale_yrgb_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 481 .scale_yrgb_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 482 .scale_cbcr_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 483 .scale_cbcr_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 484 }; 485 486 static const struct vop_win rk3366_win0_data = { 487 .scl = &rk3366_lit_win_scl, 488 489 .enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0), 490 .format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1), 491 .rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12), 492 .act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0), 493 .dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0), 494 .dsp_st = VOP_REG(RK3366_LIT_WIN0_DSP_ST, 0xffffffff, 0), 495 .yrgb_mst = VOP_REG(RK3366_LIT_WIN0_YRGB_MST0, 0xffffffff, 0), 496 .uv_mst = VOP_REG(RK3366_LIT_WIN0_CBR_MST0, 0xffffffff, 0), 497 .yrgb_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 0), 498 .uv_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 16), 499 500 .alpha_mode = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 1), 501 .alpha_en = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 0), 502 }; 503 504 static const struct vop_win rk3366_win1_data = { 505 .enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0), 506 .format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4), 507 .rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12), 508 .dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0), 509 .dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0), 510 .yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0), 511 .yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0), 512 513 .alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1), 514 .alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0), 515 }; 516 517 static const struct vop_ctrl px30_ctrl_data = { 518 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 519 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 520 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 521 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 522 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 523 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 524 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 525 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0), 526 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 527 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 528 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 22), 529 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 530 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13), 531 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 532 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 533 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 534 .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8), 535 .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10), 536 .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16), 537 .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18), 538 .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24), 539 .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26), 540 .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25), 541 .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17), 542 .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9), 543 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 544 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 545 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6), 546 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 547 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 548 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 549 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 550 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 551 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 552 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 553 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 554 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 555 556 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 557 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 558 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 559 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 560 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 561 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 562 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 563 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 564 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 565 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 566 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 567 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 568 569 .cabc_config_mode = VOP_REG(PX30_CABC_CTRL0, 0x3, 2), 570 .cabc_calc_pixel_num = VOP_REG(PX30_CABC_CTRL0, 0x7fffff, 4), 571 .cabc_handle_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 1), 572 .cabc_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 0), 573 .cabc_total_num = VOP_REG(PX30_CABC_CTRL1, 0x7fffff, 4), 574 .cabc_lut_en = VOP_REG(PX30_CABC_CTRL1, 0x1, 0), 575 .cabc_stage_up_mode = VOP_REG(PX30_CABC_CTRL2, 0x1, 19), 576 .cabc_stage_up = VOP_REG(PX30_CABC_CTRL2, 0x1ff, 8), 577 .cabc_stage_down = VOP_REG(PX30_CABC_CTRL2, 0xff, 0), 578 .cabc_global_dn = VOP_REG(PX30_CABC_CTRL3, 0xff, 0), 579 .cabc_global_dn_limit_en = VOP_REG(PX30_CABC_CTRL3, 0x1, 8), 580 581 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), 582 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), 583 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), 584 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), 585 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), 586 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), 587 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), 588 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), 589 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), 590 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), 591 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), 592 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, 593 0xffffffff, 0), 594 }; 595 596 static const struct vop_line_flag rk3366_vop_lite_line_flag = { 597 .line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0), 598 }; 599 600 static const struct vop_grf_ctrl px30_grf_ctrl = { 601 .grf_dclk_inv = VOP_REG(PX30_GRF_PD_VO_CON1, 0x1, 4), 602 }; 603 604 const struct vop_data px30_vop_lit = { 605 .version = VOP_VERSION(2, 5), 606 .max_output = {1920, 1080}, 607 .ctrl = &px30_ctrl_data, 608 .grf_ctrl = &px30_grf_ctrl, 609 .win = &rk3366_win1_data, 610 .line_flag = &rk3366_vop_lite_line_flag, 611 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 612 }; 613 614 const struct vop_data px30_vop_big = { 615 .version = VOP_VERSION(2, 6), 616 .max_output = {1920, 1080}, 617 .ctrl = &px30_ctrl_data, 618 .grf_ctrl = &px30_grf_ctrl, 619 .win = &rk3366_win1_data, 620 .line_flag = &rk3366_vop_lite_line_flag, 621 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 622 }; 623 624 static const struct vop_ctrl rk3308_ctrl_data = { 625 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 626 .axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16), 627 .axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12), 628 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 629 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 630 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 631 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 632 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 633 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 634 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 635 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 636 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 3), 637 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 638 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 639 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 640 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 641 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 642 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 643 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6), 644 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 645 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 646 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 647 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 648 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 649 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 650 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 651 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 652 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 653 654 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 655 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 656 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 657 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 658 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 659 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 660 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 661 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 662 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 663 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 664 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 665 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 666 667 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), 668 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), 669 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), 670 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), 671 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), 672 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), 673 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), 674 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), 675 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), 676 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), 677 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), 678 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, 679 0xffffffff, 0), 680 }; 681 682 const struct vop_data rk3308_vop = { 683 .version = VOP_VERSION(2, 7), 684 .max_output = {1920, 1080}, 685 .ctrl = &rk3308_ctrl_data, 686 .win = &rk3366_win0_data, 687 .line_flag = &rk3366_vop_lite_line_flag, 688 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 689 }; 690 691 static const struct vop_grf_ctrl rk1808_grf_ctrl = { 692 .grf_dclk_inv = VOP_REG(RK1808_GRF_PD_VO_CON1, 0x1, 4), 693 }; 694 695 const struct vop_data rk1808_vop = { 696 .version = VOP_VERSION(2, 8), 697 .max_output = {1920, 1080}, 698 .ctrl = &px30_ctrl_data, 699 .grf_ctrl = &rk1808_grf_ctrl, 700 .win = &rk3366_win1_data, 701 .line_flag = &rk3366_vop_lite_line_flag, 702 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 703 }; 704 705 const struct vop_data rv1108_vop = { 706 .version = VOP_VERSION(2, 4), 707 .max_output = {1920, 1080}, 708 .ctrl = &rk3308_ctrl_data, 709 .win = &rk3366_win0_data, 710 .line_flag = &rk3366_vop_lite_line_flag, 711 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 712 }; 713 714 static const struct vop_win rv1126_win2_data = { 715 .gate = VOP_REG(RV1126_WIN2_CTRL0, 0x1, 0), 716 .enable = VOP_REG(RV1126_WIN2_CTRL0, 0x1, 4), 717 .format = VOP_REG(RV1126_WIN2_CTRL0, 0x3, 5), 718 .rb_swap = VOP_REG(RV1126_WIN2_CTRL0, 0x1, 20), 719 .dsp_info = VOP_REG(RV1126_WIN2_DSP_INFO0, 0x0fff0fff, 0), 720 .dsp_st = VOP_REG(RV1126_WIN2_DSP_ST0, 0x1fff1fff, 0), 721 .yrgb_mst = VOP_REG(RV1126_WIN2_MST0, 0xffffffff, 0), 722 .yrgb_vir = VOP_REG(RV1126_WIN2_VIR0_1, 0x1fff, 0), 723 }; 724 725 static const struct vop_ctrl rv1126_ctrl_data = { 726 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 727 .axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16), 728 .axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12), 729 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 730 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 731 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 732 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 733 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 734 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 735 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0), 736 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 737 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 738 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 22), 739 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 740 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13), 741 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 742 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 743 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 744 .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8), 745 .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10), 746 .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16), 747 .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18), 748 .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24), 749 .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26), 750 .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25), 751 .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17), 752 .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9), 753 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 754 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8), 755 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 756 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 757 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 758 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 759 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 760 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 761 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 762 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 763 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 764 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 765 766 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 767 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 768 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 769 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 770 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 771 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 772 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 773 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 774 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 775 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 776 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 777 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 778 779 .mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0), 780 .mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6), 781 .mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10), 782 .mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16), 783 .mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20), 784 .mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26), 785 .mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27), 786 .mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28), 787 .mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29), 788 .mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30), 789 .mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31), 790 .mcu_rw_bypass_port = VOP_REG(RK3366_LIT_MCU_RW_BYPASS_PORT, 791 0xffffffff, 0), 792 }; 793 794 static const struct vop_grf_ctrl rv1126_grf_ctrl = { 795 .grf_dclk_inv = VOP_REG(0x1026c, 0x1, 2), 796 }; 797 798 const struct vop_data rv1126_vop = { 799 .version = VOP_VERSION(2, 7), 800 .max_output = {1920, 1080}, 801 .ctrl = &rv1126_ctrl_data, 802 .grf_ctrl = &rv1126_grf_ctrl, 803 .win = &rv1126_win2_data, 804 .line_flag = &rk3366_vop_lite_line_flag, 805 .reg_len = RK3366_LIT_FLAG_REG * 4, 806 }; 807