1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <linux/list.h> 14 15 #include "rockchip_vop.h" 16 #include "rockchip_vop_reg.h" 17 18 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \ 19 _begin_minor, _end_minor) \ 20 {.offset = off, \ 21 .mask = _mask, \ 22 .shift = s, \ 23 .write_mask = _write_mask, \ 24 .major = _major, \ 25 .begin_minor = _begin_minor, \ 26 .end_minor = _end_minor,} 27 28 #define VOP_REG(off, _mask, s) \ 29 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1) 30 31 #define VOP_REG_MASK(off, _mask, s) \ 32 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1) 33 34 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \ 35 VOP_REG_VER_MASK(off, _mask, s, false, \ 36 _major, _begin_minor, _end_minor) 37 38 static const struct vop_scl_extension rk3288_win_full_scl_ext = { 39 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), 40 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), 41 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28), 42 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26), 43 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24), 44 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23), 45 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22), 46 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20), 47 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18), 48 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16), 49 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15), 50 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12), 51 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8), 52 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7), 53 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6), 54 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5), 55 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4), 56 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2), 57 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1), 58 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0), 59 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5), 60 }; 61 62 static const struct vop_scl_regs rk3288_win_full_scl = { 63 .ext = &rk3288_win_full_scl_ext, 64 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 65 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 66 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 67 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 68 }; 69 70 static const struct vop_win rk3288_win01_data = { 71 .scl = &rk3288_win_full_scl, 72 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), 73 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), 74 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), 75 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1), 76 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), 77 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), 78 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0), 79 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0), 80 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0), 81 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0), 82 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), 83 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0), 84 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0), 85 }; 86 87 static const struct vop_ctrl rk3288_ctrl_data = { 88 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22), 89 .axi_outstanding_max_num = VOP_REG(RK3288_SYS_CTRL1, 0x1f, 13), 90 .axi_max_outstanding_en = VOP_REG(RK3288_SYS_CTRL1, 0x1, 12), 91 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 92 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), 93 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 94 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), 95 .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 96 .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 97 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 98 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 99 .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 100 .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 101 .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0), 102 103 .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10), 104 .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), 105 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8), 106 .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1), 107 .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1), 108 .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1), 109 .core_dclk_div = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 4, 3, 4, -1), 110 .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1), 111 .dclk_ddr = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 8, 3, 4, -1), 112 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 113 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 114 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 115 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 116 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 117 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), 118 .data01_swap = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 17, 3, 5, -1), 119 .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1), 120 .dp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1), 121 .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1), 122 .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1), 123 .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1), 124 .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1), 125 126 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1), 127 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), 128 129 .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1), 130 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), 131 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20), 132 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), 133 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0), 134 .update_gamma_lut = VOP_REG_VER(RK3288_DSP_CTRL1, 0x1, 7, 3, 5, -1), 135 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), 136 137 .bcsh_brightness = VOP_REG(RK3288_BCSH_BCS, 0xff, 0), 138 .bcsh_contrast = VOP_REG(RK3288_BCSH_BCS, 0x1ff, 8), 139 .bcsh_sat_con = VOP_REG(RK3288_BCSH_BCS, 0x3ff, 20), 140 .bcsh_out_mode = VOP_REG(RK3288_BCSH_BCS, 0x3, 0), 141 .bcsh_sin_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 0), 142 .bcsh_cos_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 16), 143 .bcsh_r2y_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 6, 3, 1, -1), 144 .bcsh_r2y_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 4, 3, 1, -1), 145 .bcsh_y2r_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x3, 2, 3, 1, -1), 146 .bcsh_y2r_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 0, 3, 1, -1), 147 .bcsh_color_bar = VOP_REG(RK3288_BCSH_COLOR_BAR, 0xffffff, 8), 148 .bcsh_en = VOP_REG(RK3288_BCSH_COLOR_BAR, 0x1, 0), 149 150 .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22), 151 .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23), 152 153 .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), 154 155 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0), 156 .win_gate[0] = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), 157 .win_gate[1] = VOP_REG(RK3288_WIN3_CTRL0, 0x1, 0), 158 }; 159 160 static const struct vop_line_flag rk3288_vop_line_flag = { 161 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), 162 }; 163 164 const struct vop_data rk3288_vop = { 165 .version = VOP_VERSION(3, 1), 166 .feature = VOP_FEATURE_OUTPUT_10BIT, 167 .ctrl = &rk3288_ctrl_data, 168 .win = &rk3288_win01_data, 169 .line_flag = &rk3288_vop_line_flag, 170 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 171 }; 172 173 static const struct vop_line_flag rk3368_vop_line_flag = { 174 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), 175 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), 176 }; 177 178 const struct vop_data rk3368_vop = { 179 .version = VOP_VERSION(3, 2), 180 .ctrl = &rk3288_ctrl_data, 181 .win = &rk3288_win01_data, 182 .line_flag = &rk3368_vop_line_flag, 183 .reg_len = RK3368_DSP_VACT_ST_END_F1 * 4, 184 }; 185 186 static const struct vop_line_flag rk3366_vop_line_flag = { 187 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), 188 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), 189 }; 190 191 const struct vop_data rk3366_vop = { 192 .version = VOP_VERSION(3, 4), 193 .ctrl = &rk3288_ctrl_data, 194 .win = &rk3288_win01_data, 195 .line_flag = &rk3366_vop_line_flag, 196 .reg_len = RK3366_DSP_VACT_ST_END_F1 * 4, 197 }; 198 199 const struct vop_data rk3399_vop_big = { 200 .version = VOP_VERSION(3, 5), 201 .feature = VOP_FEATURE_OUTPUT_10BIT, 202 .ctrl = &rk3288_ctrl_data, 203 .win = &rk3288_win01_data, 204 .line_flag = &rk3366_vop_line_flag, 205 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 206 }; 207 208 const struct vop_data rk3399_vop_lit = { 209 .version = VOP_VERSION(3, 6), 210 .ctrl = &rk3288_ctrl_data, 211 .win = &rk3288_win01_data, 212 .line_flag = &rk3366_vop_line_flag, 213 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 214 }; 215 216 const struct vop_data rk322x_vop = { 217 .version = VOP_VERSION(3, 7), 218 .feature = VOP_FEATURE_OUTPUT_10BIT, 219 .ctrl = &rk3288_ctrl_data, 220 .win = &rk3288_win01_data, 221 .line_flag = &rk3366_vop_line_flag, 222 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 223 }; 224 225 static const struct vop_ctrl rk3328_ctrl_data = { 226 .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22), 227 .axi_outstanding_max_num = VOP_REG(RK3328_SYS_CTRL1, 0x1f, 13), 228 .axi_max_outstanding_en = VOP_REG(RK3328_SYS_CTRL1, 0x1, 12), 229 .reg_done_frm = VOP_REG(RK3328_SYS_CTRL1, 0x1, 24), 230 .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23), 231 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 232 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), 233 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 234 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), 235 .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 236 .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 237 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 238 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 239 .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 240 .post_scl_factor = VOP_REG(RK3328_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 241 .post_scl_ctrl = VOP_REG(RK3328_POST_SCL_CTRL, 0x3, 0), 242 .dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2), 243 .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10), 244 .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8), 245 .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18), 246 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), 247 .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), 248 .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4), 249 .dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8), 250 .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5), 251 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 252 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 253 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 254 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 255 .tve_dclk_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 24), 256 .tve_dclk_pol = VOP_REG(RK3328_SYS_CTRL, 0x1, 25), 257 .tve_sw_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 26), 258 .sw_uv_offset_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 27), 259 .sw_genlock = VOP_REG(RK3328_SYS_CTRL, 0x1, 28), 260 .sw_dac_sel = VOP_REG(RK3328_SYS_CTRL, 0x1, 29), 261 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), 262 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), 263 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), 264 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), 265 266 .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1), 267 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), 268 269 .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12), 270 .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20), 271 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), 272 .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0), 273 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), 274 275 .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22), 276 .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23), 277 278 .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0), 279 280 .bcsh_brightness = VOP_REG(RK3328_BCSH_BCS, 0xff, 0), 281 .bcsh_contrast = VOP_REG(RK3328_BCSH_BCS, 0x1ff, 8), 282 .bcsh_sat_con = VOP_REG(RK3328_BCSH_BCS, 0x3ff, 20), 283 .bcsh_out_mode = VOP_REG(RK3328_BCSH_BCS, 0x3, 30), 284 .bcsh_sin_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 0), 285 .bcsh_cos_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 16), 286 .bcsh_r2y_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 6), 287 .bcsh_r2y_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 4), 288 .bcsh_y2r_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 2), 289 .bcsh_y2r_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 0), 290 .bcsh_color_bar = VOP_REG(RK3328_BCSH_COLOR_BAR, 0xffffff, 8), 291 .bcsh_en = VOP_REG(RK3328_BCSH_COLOR_BAR, 0x1, 0), 292 .win_channel[0] = VOP_REG_VER(RK3328_WIN0_CTRL2, 0xff, 0, 3, 8, 8), 293 .win_channel[1] = VOP_REG_VER(RK3328_WIN1_CTRL2, 0xff, 0, 3, 8, 8), 294 .win_channel[2] = VOP_REG_VER(RK3328_WIN2_CTRL2, 0xff, 0, 3, 8, 8), 295 296 .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0), 297 }; 298 299 300 static const struct vop_line_flag rk3328_vop_line_flag = { 301 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), 302 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), 303 }; 304 305 const struct vop_data rk3328_vop = { 306 .version = VOP_VERSION(3, 8), 307 .feature = VOP_FEATURE_OUTPUT_10BIT, 308 .ctrl = &rk3328_ctrl_data, 309 .win = &rk3288_win01_data, 310 .win_offset = 0xd0, 311 .line_flag = &rk3328_vop_line_flag, 312 .reg_len = RK3328_DSP_VACT_ST_END_F1 * 4, 313 }; 314 315 static const struct vop_scl_regs rk3036_win_scl = { 316 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 317 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 318 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 319 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 320 }; 321 322 static const struct vop_win rk3036_win0_data = { 323 .scl = &rk3036_win_scl, 324 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), 325 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), 326 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), 327 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), 328 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), 329 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), 330 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), 331 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), 332 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), 333 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), 334 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18), 335 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0) 336 }; 337 338 static const struct vop_ctrl rk3036_ctrl_data = { 339 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), 340 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), 341 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), 342 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), 343 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8), 344 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 345 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), 346 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 347 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), 348 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), 349 }; 350 351 static const struct vop_line_flag rk3036_vop_line_flag = { 352 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), 353 }; 354 355 const struct vop_data rk3036_vop = { 356 .version = VOP_VERSION(2, 2), 357 .ctrl = &rk3036_ctrl_data, 358 .win = &rk3036_win0_data, 359 .line_flag = &rk3036_vop_line_flag, 360 .reg_len = RK3036_DSP_VACT_ST_END_F1 * 4, 361 }; 362 363 static const struct vop_scl_regs rk3366_lit_win_scl = { 364 .scale_yrgb_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 365 .scale_yrgb_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 366 .scale_cbcr_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 367 .scale_cbcr_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 368 }; 369 370 static const struct vop_win rk3366_win0_data = { 371 .scl = &rk3366_lit_win_scl, 372 373 .enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0), 374 .format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1), 375 .rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12), 376 .act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0), 377 .dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0), 378 .dsp_st = VOP_REG(RK3366_LIT_WIN0_DSP_ST, 0xffffffff, 0), 379 .yrgb_mst = VOP_REG(RK3366_LIT_WIN0_YRGB_MST0, 0xffffffff, 0), 380 .uv_mst = VOP_REG(RK3366_LIT_WIN0_CBR_MST0, 0xffffffff, 0), 381 .yrgb_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 0), 382 .uv_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 16), 383 384 .alpha_mode = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 1), 385 .alpha_en = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 0), 386 }; 387 388 static const struct vop_win rk3366_win1_data = { 389 .enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0), 390 .format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4), 391 .rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12), 392 .dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0), 393 .dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0), 394 .yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0), 395 .yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0), 396 397 .alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1), 398 .alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0), 399 }; 400 401 static const struct vop_ctrl px30_ctrl_data = { 402 .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1), 403 .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0), 404 .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0), 405 .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0), 406 .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0), 407 .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0), 408 .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0), 409 .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0), 410 .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13), 411 .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0), 412 .dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 22), 413 .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4), 414 .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13), 415 .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14), 416 .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0), 417 .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2), 418 .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8), 419 .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10), 420 .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16), 421 .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18), 422 .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24), 423 .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26), 424 .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25), 425 .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17), 426 .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9), 427 .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1), 428 .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2), 429 .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6), 430 .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9), 431 .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5), 432 .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15), 433 .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14), 434 .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3), 435 .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5), 436 .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16), 437 .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0), 438 .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0), 439 440 .bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0), 441 .bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1), 442 .bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2), 443 .bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4), 444 .bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6), 445 .bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7), 446 .bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0), 447 .bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0), 448 .bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8), 449 .bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20), 450 .bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0), 451 .bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16), 452 453 .cabc_config_mode = VOP_REG(PX30_CABC_CTRL0, 0x3, 2), 454 .cabc_calc_pixel_num = VOP_REG(PX30_CABC_CTRL0, 0x7fffff, 4), 455 .cabc_handle_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 1), 456 .cabc_en = VOP_REG(PX30_CABC_CTRL0, 0x1, 0), 457 .cabc_total_num = VOP_REG(PX30_CABC_CTRL1, 0x7fffff, 4), 458 .cabc_lut_en = VOP_REG(PX30_CABC_CTRL1, 0x1, 0), 459 .cabc_stage_up_mode = VOP_REG(PX30_CABC_CTRL2, 0x1, 19), 460 .cabc_stage_up = VOP_REG(PX30_CABC_CTRL2, 0x1ff, 8), 461 .cabc_stage_down = VOP_REG(PX30_CABC_CTRL2, 0xff, 0), 462 .cabc_global_dn = VOP_REG(PX30_CABC_CTRL3, 0xff, 0), 463 .cabc_global_dn_limit_en = VOP_REG(PX30_CABC_CTRL3, 0x1, 8), 464 }; 465 466 static const struct vop_line_flag rk3366_vop_lite_line_flag = { 467 .line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0), 468 }; 469 470 const struct vop_data px30_vop_lit = { 471 .version = VOP_VERSION(2, 5), 472 .ctrl = &px30_ctrl_data, 473 .win = &rk3366_win1_data, 474 .line_flag = &rk3366_vop_lite_line_flag, 475 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 476 }; 477 478 const struct vop_data px30_vop_big = { 479 .version = VOP_VERSION(2, 6), 480 .ctrl = &px30_ctrl_data, 481 .win = &rk3366_win0_data, 482 .line_flag = &rk3366_vop_lite_line_flag, 483 .reg_len = RK3366_LIT_FRC_LOWER01_0 * 4, 484 }; 485