1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <asm/io.h> 15 #include <linux/list.h> 16 17 #include "rockchip_vop.h" 18 #include "rockchip_vop_reg.h" 19 20 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \ 21 _begin_minor, _end_minor) \ 22 {.offset = off, \ 23 .mask = _mask, \ 24 .shift = s, \ 25 .write_mask = _write_mask, \ 26 .major = _major, \ 27 .begin_minor = _begin_minor, \ 28 .end_minor = _end_minor,} 29 30 #define VOP_REG(off, _mask, s) \ 31 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1) 32 33 #define VOP_REG_MASK(off, _mask, s) \ 34 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1) 35 36 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \ 37 VOP_REG_VER_MASK(off, _mask, s, false, \ 38 _major, _begin_minor, _end_minor) 39 40 static const struct vop_scl_extension rk3288_win_full_scl_ext = { 41 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), 42 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), 43 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28), 44 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26), 45 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24), 46 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23), 47 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22), 48 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20), 49 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18), 50 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16), 51 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15), 52 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12), 53 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8), 54 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7), 55 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6), 56 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5), 57 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4), 58 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2), 59 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1), 60 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0), 61 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5), 62 }; 63 64 static const struct vop_scl_regs rk3288_win_full_scl = { 65 .ext = &rk3288_win_full_scl_ext, 66 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 67 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 68 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 69 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 70 }; 71 72 static const struct vop_win rk3288_win01_data = { 73 .scl = &rk3288_win_full_scl, 74 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), 75 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), 76 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), 77 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1), 78 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), 79 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), 80 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0), 81 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0), 82 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0), 83 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0), 84 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), 85 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0), 86 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0), 87 }; 88 89 static const struct vop_ctrl rk3288_ctrl_data = { 90 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22), 91 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 92 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), 93 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 94 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), 95 .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 96 .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 97 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 98 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 99 .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 100 .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 101 .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0), 102 103 .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10), 104 .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), 105 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8), 106 .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1), 107 .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1), 108 .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1), 109 .core_dclk_div = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 4, 3, 4, -1), 110 .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1), 111 .dclk_ddr = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 8, 3, 4, -1), 112 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 113 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 114 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 115 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 116 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 117 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), 118 .data01_swap = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 17, 3, 5, -1), 119 .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1), 120 .dp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1), 121 .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1), 122 .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1), 123 .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1), 124 .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1), 125 126 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1), 127 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), 128 129 .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1), 130 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), 131 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20), 132 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), 133 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0), 134 .update_gamma_lut = VOP_REG_VER(RK3288_DSP_CTRL1, 0x1, 7, 3, 5, -1), 135 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), 136 137 .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22), 138 .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23), 139 140 .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), 141 142 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0), 143 .win_gate[0] = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), 144 .win_gate[1] = VOP_REG(RK3288_WIN3_CTRL0, 0x1, 0), 145 }; 146 147 static const struct vop_line_flag rk3288_vop_line_flag = { 148 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), 149 }; 150 151 const struct vop_data rk3288_vop = { 152 .version = VOP_VERSION(3, 1), 153 .feature = VOP_FEATURE_OUTPUT_10BIT, 154 .ctrl = &rk3288_ctrl_data, 155 .win = &rk3288_win01_data, 156 .line_flag = &rk3288_vop_line_flag, 157 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 158 }; 159 160 static const struct vop_line_flag rk3368_vop_line_flag = { 161 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), 162 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), 163 }; 164 165 const struct vop_data rk3368_vop = { 166 .version = VOP_VERSION(3, 2), 167 .ctrl = &rk3288_ctrl_data, 168 .win = &rk3288_win01_data, 169 .line_flag = &rk3368_vop_line_flag, 170 .reg_len = RK3368_DSP_VACT_ST_END_F1 * 4, 171 }; 172 173 static const struct vop_line_flag rk3366_vop_line_flag = { 174 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), 175 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), 176 }; 177 178 const struct vop_data rk3366_vop = { 179 .version = VOP_VERSION(3, 4), 180 .ctrl = &rk3288_ctrl_data, 181 .win = &rk3288_win01_data, 182 .line_flag = &rk3366_vop_line_flag, 183 .reg_len = RK3366_DSP_VACT_ST_END_F1 * 4, 184 }; 185 186 const struct vop_data rk3399_vop_big = { 187 .version = VOP_VERSION(3, 5), 188 .feature = VOP_FEATURE_OUTPUT_10BIT, 189 .ctrl = &rk3288_ctrl_data, 190 .win = &rk3288_win01_data, 191 .line_flag = &rk3366_vop_line_flag, 192 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 193 }; 194 195 const struct vop_data rk3399_vop_lit = { 196 .version = VOP_VERSION(3, 6), 197 .ctrl = &rk3288_ctrl_data, 198 .win = &rk3288_win01_data, 199 .line_flag = &rk3366_vop_line_flag, 200 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 201 }; 202 203 const struct vop_data rk322x_vop = { 204 .version = VOP_VERSION(3, 7), 205 .feature = VOP_FEATURE_OUTPUT_10BIT, 206 .ctrl = &rk3288_ctrl_data, 207 .win = &rk3288_win01_data, 208 .line_flag = &rk3366_vop_line_flag, 209 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 210 }; 211 212 static const struct vop_ctrl rk3328_ctrl_data = { 213 .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22), 214 .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23), 215 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 216 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), 217 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 218 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), 219 .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 220 .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 221 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 222 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 223 .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 224 .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10), 225 .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8), 226 .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18), 227 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), 228 .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), 229 .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4), 230 .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5), 231 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 232 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 233 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 234 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 235 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), 236 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), 237 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), 238 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), 239 240 .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1), 241 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), 242 243 .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12), 244 .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20), 245 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), 246 .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0), 247 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), 248 249 .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22), 250 .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23), 251 252 .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0), 253 254 .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0), 255 }; 256 257 258 static const struct vop_line_flag rk3328_vop_line_flag = { 259 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), 260 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), 261 }; 262 263 const struct vop_data rk3328_vop = { 264 .version = VOP_VERSION(3, 8), 265 .feature = VOP_FEATURE_OUTPUT_10BIT, 266 .ctrl = &rk3328_ctrl_data, 267 .win = &rk3288_win01_data, 268 .win_offset = 0xd0, 269 .line_flag = &rk3328_vop_line_flag, 270 .reg_len = RK3328_DSP_VACT_ST_END_F1 * 4, 271 }; 272 273 static const struct vop_scl_regs rk3036_win_scl = { 274 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 275 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 276 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 277 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 278 }; 279 280 static const struct vop_win rk3036_win0_data = { 281 .scl = &rk3036_win_scl, 282 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), 283 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), 284 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), 285 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), 286 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), 287 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), 288 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), 289 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), 290 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), 291 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), 292 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18), 293 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0) 294 }; 295 296 static const struct vop_ctrl rk3036_ctrl_data = { 297 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), 298 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), 299 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), 300 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), 301 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8), 302 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 303 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), 304 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 305 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), 306 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), 307 }; 308 309 static const struct vop_line_flag rk3036_vop_line_flag = { 310 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), 311 }; 312 313 const struct vop_data rk3036_vop = { 314 .version = VOP_VERSION(2, 2), 315 .ctrl = &rk3036_ctrl_data, 316 .win = &rk3036_win0_data, 317 .line_flag = &rk3036_vop_line_flag, 318 .reg_len = RK3036_DSP_VACT_ST_END_F1 * 4, 319 }; 320