1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <asm/unaligned.h> 12 #include <asm/io.h> 13 #include <linux/list.h> 14 15 #include "rockchip_vop.h" 16 #include "rockchip_vop_reg.h" 17 18 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \ 19 _begin_minor, _end_minor) \ 20 {.offset = off, \ 21 .mask = _mask, \ 22 .shift = s, \ 23 .write_mask = _write_mask, \ 24 .major = _major, \ 25 .begin_minor = _begin_minor, \ 26 .end_minor = _end_minor,} 27 28 #define VOP_REG(off, _mask, s) \ 29 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1) 30 31 #define VOP_REG_MASK(off, _mask, s) \ 32 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1) 33 34 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \ 35 VOP_REG_VER_MASK(off, _mask, s, false, \ 36 _major, _begin_minor, _end_minor) 37 38 static const struct vop_scl_extension rk3288_win_full_scl_ext = { 39 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), 40 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), 41 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28), 42 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26), 43 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24), 44 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23), 45 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22), 46 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20), 47 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18), 48 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16), 49 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15), 50 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12), 51 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8), 52 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7), 53 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6), 54 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5), 55 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4), 56 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2), 57 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1), 58 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0), 59 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5), 60 }; 61 62 static const struct vop_scl_regs rk3288_win_full_scl = { 63 .ext = &rk3288_win_full_scl_ext, 64 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 65 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 66 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 67 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 68 }; 69 70 static const struct vop_win rk3288_win01_data = { 71 .scl = &rk3288_win_full_scl, 72 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0), 73 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1), 74 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12), 75 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1), 76 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0), 77 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0), 78 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0), 79 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0), 80 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0), 81 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0), 82 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16), 83 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0), 84 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0), 85 }; 86 87 static const struct vop_ctrl rk3288_ctrl_data = { 88 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22), 89 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 90 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0), 91 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 92 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0), 93 .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 94 .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 95 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 96 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 97 .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 98 .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0), 99 .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0), 100 101 .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10), 102 .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23), 103 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8), 104 .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1), 105 .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1), 106 .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1), 107 .core_dclk_div = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 4, 3, 4, -1), 108 .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1), 109 .dclk_ddr = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 8, 3, 4, -1), 110 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 111 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 112 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 113 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 114 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 115 .mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3), 116 .data01_swap = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 17, 3, 5, -1), 117 .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1), 118 .dp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1), 119 .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1), 120 .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1), 121 .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1), 122 .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1), 123 124 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1), 125 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6), 126 127 .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1), 128 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12), 129 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20), 130 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18), 131 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0), 132 .update_gamma_lut = VOP_REG_VER(RK3288_DSP_CTRL1, 0x1, 7, 3, 5, -1), 133 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0), 134 135 .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22), 136 .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23), 137 138 .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0), 139 140 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0), 141 .win_gate[0] = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0), 142 .win_gate[1] = VOP_REG(RK3288_WIN3_CTRL0, 0x1, 0), 143 }; 144 145 static const struct vop_line_flag rk3288_vop_line_flag = { 146 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12), 147 }; 148 149 const struct vop_data rk3288_vop = { 150 .version = VOP_VERSION(3, 1), 151 .feature = VOP_FEATURE_OUTPUT_10BIT, 152 .ctrl = &rk3288_ctrl_data, 153 .win = &rk3288_win01_data, 154 .line_flag = &rk3288_vop_line_flag, 155 .reg_len = RK3288_DSP_VACT_ST_END_F1 * 4, 156 }; 157 158 static const struct vop_line_flag rk3368_vop_line_flag = { 159 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), 160 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), 161 }; 162 163 const struct vop_data rk3368_vop = { 164 .version = VOP_VERSION(3, 2), 165 .ctrl = &rk3288_ctrl_data, 166 .win = &rk3288_win01_data, 167 .line_flag = &rk3368_vop_line_flag, 168 .reg_len = RK3368_DSP_VACT_ST_END_F1 * 4, 169 }; 170 171 static const struct vop_line_flag rk3366_vop_line_flag = { 172 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), 173 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), 174 }; 175 176 const struct vop_data rk3366_vop = { 177 .version = VOP_VERSION(3, 4), 178 .ctrl = &rk3288_ctrl_data, 179 .win = &rk3288_win01_data, 180 .line_flag = &rk3366_vop_line_flag, 181 .reg_len = RK3366_DSP_VACT_ST_END_F1 * 4, 182 }; 183 184 const struct vop_data rk3399_vop_big = { 185 .version = VOP_VERSION(3, 5), 186 .feature = VOP_FEATURE_OUTPUT_10BIT, 187 .ctrl = &rk3288_ctrl_data, 188 .win = &rk3288_win01_data, 189 .line_flag = &rk3366_vop_line_flag, 190 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 191 }; 192 193 const struct vop_data rk3399_vop_lit = { 194 .version = VOP_VERSION(3, 6), 195 .ctrl = &rk3288_ctrl_data, 196 .win = &rk3288_win01_data, 197 .line_flag = &rk3366_vop_line_flag, 198 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 199 }; 200 201 const struct vop_data rk322x_vop = { 202 .version = VOP_VERSION(3, 7), 203 .feature = VOP_FEATURE_OUTPUT_10BIT, 204 .ctrl = &rk3288_ctrl_data, 205 .win = &rk3288_win01_data, 206 .line_flag = &rk3366_vop_line_flag, 207 .reg_len = RK3399_DSP_VACT_ST_END_F1 * 4, 208 }; 209 210 static const struct vop_ctrl rk3328_ctrl_data = { 211 .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22), 212 .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23), 213 .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 214 .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), 215 .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 216 .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), 217 .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0), 218 .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0), 219 .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 220 .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 221 .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0), 222 .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10), 223 .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8), 224 .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18), 225 .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), 226 .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16), 227 .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4), 228 .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5), 229 .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 230 .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 231 .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 232 .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 233 .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), 234 .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), 235 .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), 236 .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), 237 238 .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1), 239 .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), 240 241 .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12), 242 .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20), 243 .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), 244 .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0), 245 .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), 246 247 .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22), 248 .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23), 249 250 .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0), 251 252 .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0), 253 }; 254 255 256 static const struct vop_line_flag rk3328_vop_line_flag = { 257 .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), 258 .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), 259 }; 260 261 const struct vop_data rk3328_vop = { 262 .version = VOP_VERSION(3, 8), 263 .feature = VOP_FEATURE_OUTPUT_10BIT, 264 .ctrl = &rk3328_ctrl_data, 265 .win = &rk3288_win01_data, 266 .win_offset = 0xd0, 267 .line_flag = &rk3328_vop_line_flag, 268 .reg_len = RK3328_DSP_VACT_ST_END_F1 * 4, 269 }; 270 271 static const struct vop_scl_regs rk3036_win_scl = { 272 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), 273 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), 274 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), 275 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), 276 }; 277 278 static const struct vop_win rk3036_win0_data = { 279 .scl = &rk3036_win_scl, 280 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), 281 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), 282 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), 283 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), 284 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), 285 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), 286 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), 287 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), 288 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), 289 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), 290 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18), 291 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0) 292 }; 293 294 static const struct vop_ctrl rk3036_ctrl_data = { 295 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), 296 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), 297 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24), 298 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), 299 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8), 300 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 301 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), 302 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 303 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), 304 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), 305 }; 306 307 static const struct vop_line_flag rk3036_vop_line_flag = { 308 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12), 309 }; 310 311 const struct vop_data rk3036_vop = { 312 .version = VOP_VERSION(2, 2), 313 .ctrl = &rk3036_ctrl_data, 314 .win = &rk3036_win0_data, 315 .line_flag = &rk3036_vop_line_flag, 316 .reg_len = RK3036_DSP_VACT_ST_END_F1 * 4, 317 }; 318