1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <asm/io.h> 15 #include <linux/list.h> 16 #include <linux/media-bus-format.h> 17 #include <clk.h> 18 #include <asm/arch/clock.h> 19 #include <linux/err.h> 20 #include <dm/device.h> 21 #include <dm/read.h> 22 #include <syscon.h> 23 24 #include "rockchip_display.h" 25 #include "rockchip_crtc.h" 26 #include "rockchip_connector.h" 27 #include "rockchip_vop.h" 28 29 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 30 { 31 return us * mode->clock / mode->htotal / 1000; 32 } 33 34 static int to_vop_csc_mode(int csc_mode) 35 { 36 switch (csc_mode) { 37 case V4L2_COLORSPACE_SMPTE170M: 38 return CSC_BT601L; 39 case V4L2_COLORSPACE_REC709: 40 case V4L2_COLORSPACE_DEFAULT: 41 return CSC_BT709L; 42 case V4L2_COLORSPACE_JPEG: 43 return CSC_BT601F; 44 case V4L2_COLORSPACE_BT2020: 45 return CSC_BT2020; 46 default: 47 return CSC_BT709L; 48 } 49 } 50 51 static bool is_yuv_output(uint32_t bus_format) 52 { 53 switch (bus_format) { 54 case MEDIA_BUS_FMT_YUV8_1X24: 55 case MEDIA_BUS_FMT_YUV10_1X30: 56 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 57 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 58 return true; 59 default: 60 return false; 61 } 62 } 63 64 static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode) 65 { 66 /* 67 * FIXME: 68 * 69 * There is no media type for YUV444 output, 70 * so when out_mode is AAAA or P888, assume output is YUV444 on 71 * yuv format. 72 * 73 * From H/W testing, YUV444 mode need a rb swap. 74 */ 75 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 76 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 77 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 78 output_mode == ROCKCHIP_OUT_MODE_P888)) 79 return true; 80 else 81 return false; 82 } 83 84 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) 85 { 86 struct crtc_state *crtc_state = &state->crtc_state; 87 struct connector_state *conn_state = &state->conn_state; 88 u32 *lut = conn_state->gamma.lut; 89 fdt_size_t lut_size; 90 int i, lut_len; 91 u32 *lut_regs; 92 93 if (!conn_state->gamma.lut) 94 return 0; 95 96 i = dev_read_stringlist_search(crtc_state->dev, "reg-names", "gamma_lut"); 97 if (i < 0) { 98 printf("Warning: vop not support gamma\n"); 99 return 0; 100 } 101 lut_regs = (u32 *)dev_read_addr_size(crtc_state->dev, "reg", &lut_size); 102 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 103 printf("failed to get gamma lut register\n"); 104 return 0; 105 } 106 lut_len = lut_size / 4; 107 if (lut_len != 256 && lut_len != 1024) { 108 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 109 return 0; 110 } 111 112 if (conn_state->gamma.size != lut_len) { 113 int size = conn_state->gamma.size; 114 u32 j, r, g, b, color; 115 116 for (i = 0; i < lut_len; i++) { 117 j = i * size / lut_len; 118 r = lut[j] / size / size * lut_len / size; 119 g = lut[j] / size % size * lut_len / size; 120 b = lut[j] % size * lut_len / size; 121 color = r * lut_len * lut_len + g * lut_len + b; 122 123 writel(color, lut_regs + (i << 2)); 124 } 125 } else { 126 for (i = 0; i < lut_len; i++) 127 writel(lut[i], lut_regs + (i << 2)); 128 } 129 130 VOP_CTRL_SET(vop, dsp_lut_en, 1); 131 VOP_CTRL_SET(vop, update_gamma_lut, 1); 132 133 return 0; 134 } 135 136 static void vop_post_config(struct display_state *state, struct vop *vop) 137 { 138 struct connector_state *conn_state = &state->conn_state; 139 struct drm_display_mode *mode = &conn_state->mode; 140 u16 vtotal = mode->crtc_vtotal; 141 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 142 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 143 u16 hdisplay = mode->crtc_hdisplay; 144 u16 vdisplay = mode->crtc_vdisplay; 145 u16 hsize = hdisplay * (conn_state->overscan.left_margin + conn_state->overscan.right_margin) / 200; 146 u16 vsize = vdisplay * (conn_state->overscan.top_margin + conn_state->overscan.bottom_margin) / 200; 147 u16 hact_end, vact_end; 148 u32 val; 149 150 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 151 vsize = round_down(vsize, 2); 152 153 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 154 hact_end = hact_st + hsize; 155 val = hact_st << 16; 156 val |= hact_end; 157 158 VOP_CTRL_SET(vop, hpost_st_end, val); 159 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 160 vact_end = vact_st + vsize; 161 val = vact_st << 16; 162 val |= vact_end; 163 VOP_CTRL_SET(vop, vpost_st_end, val); 164 val = scl_cal_scale2(vdisplay, vsize) << 16; 165 val |= scl_cal_scale2(hdisplay, hsize); 166 VOP_CTRL_SET(vop, post_scl_factor, val); 167 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 168 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 169 VOP_CTRL_SET(vop, post_scl_ctrl, 170 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 171 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 172 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 173 u16 vact_st_f1 = vtotal + vact_st + 1; 174 u16 vact_end_f1 = vact_st_f1 + vsize; 175 176 val = vact_st_f1 << 16 | vact_end_f1; 177 VOP_CTRL_SET(vop, vpost_st_end_f1, val); 178 } 179 } 180 181 static int rockchip_vop_init(struct display_state *state) 182 { 183 struct crtc_state *crtc_state = &state->crtc_state; 184 struct connector_state *conn_state = &state->conn_state; 185 struct drm_display_mode *mode = &conn_state->mode; 186 const struct rockchip_crtc *crtc = crtc_state->crtc; 187 const struct vop_data *vop_data = crtc->data; 188 struct vop *vop; 189 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 190 u16 hdisplay = mode->crtc_hdisplay; 191 u16 htotal = mode->crtc_htotal; 192 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 193 u16 hact_end = hact_st + hdisplay; 194 u16 vdisplay = mode->crtc_vdisplay; 195 u16 vtotal = mode->crtc_vtotal; 196 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 197 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 198 u16 vact_end = vact_st + vdisplay; 199 struct clk dclk; 200 u32 val, act_end; 201 int ret; 202 bool yuv_overlay = false, post_r2y_en = false, post_y2r_en = false; 203 u16 post_csc_mode; 204 bool dclk_inv; 205 206 vop = malloc(sizeof(*vop)); 207 if (!vop) 208 return -ENOMEM; 209 memset(vop, 0, sizeof(*vop)); 210 211 crtc_state->private = vop; 212 vop->regs = dev_read_addr_ptr(crtc_state->dev); 213 vop->regsbak = malloc(vop_data->reg_len); 214 vop->win = vop_data->win; 215 vop->win_offset = vop_data->win_offset; 216 vop->ctrl = vop_data->ctrl; 217 vop->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 218 if (vop->grf <= 0) 219 printf("%s: Get syscon grf failed (ret=%p)\n", 220 __func__, vop->grf); 221 222 vop->grf_ctrl = vop_data->grf_ctrl; 223 vop->line_flag = vop_data->line_flag; 224 vop->version = vop_data->version; 225 vop->max_output = vop_data->max_output; 226 227 /* 228 * TODO: 229 * Set Dclk pll parent 230 */ 231 232 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &dclk); 233 if (!ret) 234 ret = clk_set_rate(&dclk, mode->clock * 1000); 235 if (IS_ERR_VALUE(ret)) { 236 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret); 237 return ret; 238 } 239 240 memcpy(vop->regsbak, vop->regs, vop_data->reg_len); 241 242 rockchip_vop_init_gamma(vop, state); 243 244 VOP_CTRL_SET(vop, global_regdone_en, 1); 245 VOP_CTRL_SET(vop, axi_outstanding_max_num, 30); 246 VOP_CTRL_SET(vop, axi_max_outstanding_en, 1); 247 VOP_CTRL_SET(vop, reg_done_frm, 1); 248 VOP_CTRL_SET(vop, win_gate[0], 1); 249 VOP_CTRL_SET(vop, win_gate[1], 1); 250 VOP_CTRL_SET(vop, win_channel[0], 0x12); 251 VOP_CTRL_SET(vop, win_channel[1], 0x34); 252 VOP_CTRL_SET(vop, win_channel[2], 0x56); 253 VOP_CTRL_SET(vop, dsp_blank, 0); 254 255 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 256 VOP_CTRL_SET(vop, dclk_pol, dclk_inv); 257 258 val = 0x8; 259 val |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 260 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 261 VOP_CTRL_SET(vop, pin_pol, val); 262 263 switch (conn_state->type) { 264 case DRM_MODE_CONNECTOR_LVDS: 265 VOP_CTRL_SET(vop, rgb_en, 1); 266 VOP_CTRL_SET(vop, rgb_pin_pol, val); 267 VOP_CTRL_SET(vop, rgb_dclk_pol, dclk_inv); 268 VOP_CTRL_SET(vop, lvds_en, 1); 269 VOP_CTRL_SET(vop, lvds_pin_pol, val); 270 VOP_CTRL_SET(vop, lvds_dclk_pol, dclk_inv); 271 if (!IS_ERR_OR_NULL(vop->grf)) 272 VOP_GRF_SET(vop, grf_dclk_inv, !dclk_inv); 273 break; 274 case DRM_MODE_CONNECTOR_eDP: 275 VOP_CTRL_SET(vop, edp_en, 1); 276 VOP_CTRL_SET(vop, edp_pin_pol, val); 277 VOP_CTRL_SET(vop, edp_dclk_pol, dclk_inv); 278 break; 279 case DRM_MODE_CONNECTOR_HDMIA: 280 VOP_CTRL_SET(vop, hdmi_en, 1); 281 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 282 VOP_CTRL_SET(vop, hdmi_dclk_pol, 1); 283 break; 284 case DRM_MODE_CONNECTOR_DSI: 285 VOP_CTRL_SET(vop, mipi_en, 1); 286 VOP_CTRL_SET(vop, mipi_pin_pol, val); 287 VOP_CTRL_SET(vop, mipi_dclk_pol, dclk_inv); 288 VOP_CTRL_SET(vop, mipi_dual_channel_en, 289 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL)); 290 VOP_CTRL_SET(vop, data01_swap, 291 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_LINK)); 292 break; 293 case DRM_MODE_CONNECTOR_DisplayPort: 294 VOP_CTRL_SET(vop, dp_dclk_pol, 0); 295 VOP_CTRL_SET(vop, dp_pin_pol, val); 296 VOP_CTRL_SET(vop, dp_en, 1); 297 break; 298 case DRM_MODE_CONNECTOR_TV: 299 if (vdisplay == CVBS_PAL_VDISPLAY) 300 VOP_CTRL_SET(vop, tve_sw_mode, 1); 301 else 302 VOP_CTRL_SET(vop, tve_sw_mode, 0); 303 VOP_CTRL_SET(vop, tve_dclk_pol, 1); 304 VOP_CTRL_SET(vop, tve_dclk_en, 1); 305 /* use the same pol reg with hdmi */ 306 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 307 VOP_CTRL_SET(vop, sw_genlock, 1); 308 VOP_CTRL_SET(vop, sw_uv_offset_en, 1); 309 VOP_CTRL_SET(vop, dither_up, 1); 310 break; 311 default: 312 printf("unsupport connector_type[%d]\n", conn_state->type); 313 } 314 315 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 316 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 317 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 318 319 switch (conn_state->bus_format) { 320 case MEDIA_BUS_FMT_RGB565_1X16: 321 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565); 322 break; 323 case MEDIA_BUS_FMT_RGB666_1X18: 324 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 325 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666); 326 break; 327 case MEDIA_BUS_FMT_YUV8_1X24: 328 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 329 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1); 330 break; 331 case MEDIA_BUS_FMT_YUV10_1X30: 332 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 333 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 334 break; 335 case MEDIA_BUS_FMT_RGB888_1X24: 336 default: 337 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 338 break; 339 } 340 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 341 val |= PRE_DITHER_DOWN_EN(0); 342 else 343 val |= PRE_DITHER_DOWN_EN(1); 344 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO); 345 VOP_CTRL_SET(vop, dither_down, val); 346 347 VOP_CTRL_SET(vop, dclk_ddr, 348 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 349 VOP_CTRL_SET(vop, hdmi_dclk_out_en, 350 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 351 352 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 353 VOP_CTRL_SET(vop, dsp_data_swap, DSP_RB_SWAP); 354 else 355 VOP_CTRL_SET(vop, dsp_data_swap, 0); 356 357 VOP_CTRL_SET(vop, out_mode, conn_state->output_mode); 358 359 if (VOP_CTRL_SUPPORT(vop, overlay_mode)) { 360 yuv_overlay = is_yuv_output(conn_state->bus_format); 361 VOP_CTRL_SET(vop, overlay_mode, yuv_overlay); 362 } 363 /* 364 * todo: r2y for win csc 365 */ 366 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(conn_state->bus_format)); 367 368 if (yuv_overlay) { 369 if (!is_yuv_output(conn_state->bus_format)) 370 post_y2r_en = true; 371 } else { 372 if (is_yuv_output(conn_state->bus_format)) 373 post_r2y_en = true; 374 } 375 376 post_csc_mode = to_vop_csc_mode(conn_state->color_space); 377 VOP_CTRL_SET(vop, bcsh_r2y_en, post_r2y_en); 378 VOP_CTRL_SET(vop, bcsh_y2r_en, post_y2r_en); 379 VOP_CTRL_SET(vop, bcsh_r2y_csc_mode, post_csc_mode); 380 VOP_CTRL_SET(vop, bcsh_y2r_csc_mode, post_csc_mode); 381 382 /* 383 * Background color is 10bit depth if vop version >= 3.5 384 */ 385 if (!is_yuv_output(conn_state->bus_format)) 386 val = 0; 387 else if (VOP_MAJOR(vop->version) == 3 && 388 VOP_MINOR(vop->version) >= 5) 389 val = 0x20010200; 390 else 391 val = 0x801080; 392 VOP_CTRL_SET(vop, dsp_background, val); 393 394 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 395 val = hact_st << 16; 396 val |= hact_end; 397 VOP_CTRL_SET(vop, hact_st_end, val); 398 val = vact_st << 16; 399 val |= vact_end; 400 VOP_CTRL_SET(vop, vact_st_end, val); 401 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 402 u16 vact_st_f1 = vtotal + vact_st + 1; 403 u16 vact_end_f1 = vact_st_f1 + vdisplay; 404 405 val = vact_st_f1 << 16 | vact_end_f1; 406 VOP_CTRL_SET(vop, vact_st_end_f1, val); 407 408 val = vtotal << 16 | (vtotal + vsync_len); 409 VOP_CTRL_SET(vop, vs_st_end_f1, val); 410 VOP_CTRL_SET(vop, dsp_interlace, 1); 411 VOP_CTRL_SET(vop, p2i_en, 1); 412 vtotal += vtotal + 1; 413 act_end = vact_end_f1; 414 } else { 415 VOP_CTRL_SET(vop, dsp_interlace, 0); 416 VOP_CTRL_SET(vop, p2i_en, 0); 417 act_end = vact_end; 418 } 419 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 420 vop_post_config(state, vop); 421 VOP_CTRL_SET(vop, core_dclk_div, 422 !!(mode->flags & DRM_MODE_FLAG_DBLCLK)); 423 424 VOP_CTRL_SET(vop, standby, 1); 425 VOP_LINE_FLAG_SET(vop, line_flag_num[0], act_end - 3); 426 VOP_LINE_FLAG_SET(vop, line_flag_num[1], 427 act_end - us_to_vertical_line(mode, 1000)); 428 vop_cfg_done(vop); 429 430 return 0; 431 } 432 433 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 434 uint32_t dst, bool is_horizontal, 435 int vsu_mode, int *vskiplines) 436 { 437 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 438 439 if (is_horizontal) { 440 if (mode == SCALE_UP) 441 val = GET_SCL_FT_BIC(src, dst); 442 else if (mode == SCALE_DOWN) 443 val = GET_SCL_FT_BILI_DN(src, dst); 444 } else { 445 if (mode == SCALE_UP) { 446 if (vsu_mode == SCALE_UP_BIL) 447 val = GET_SCL_FT_BILI_UP(src, dst); 448 else 449 val = GET_SCL_FT_BIC(src, dst); 450 } else if (mode == SCALE_DOWN) { 451 if (vskiplines) { 452 *vskiplines = scl_get_vskiplines(src, dst); 453 val = scl_get_bili_dn_vskip(src, dst, 454 *vskiplines); 455 } else { 456 val = GET_SCL_FT_BILI_DN(src, dst); 457 } 458 } 459 } 460 461 return val; 462 } 463 464 static void scl_vop_cal_scl_fac(struct vop *vop, 465 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 466 uint32_t dst_h, uint32_t pixel_format) 467 { 468 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 469 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 470 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 471 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 472 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 473 bool is_yuv = false; 474 uint16_t cbcr_src_w = src_w / hsub; 475 uint16_t cbcr_src_h = src_h / vsub; 476 uint16_t vsu_mode; 477 uint16_t lb_mode; 478 uint32_t val; 479 int vskiplines = 0; 480 481 if (!vop->win->scl) 482 return; 483 484 if (dst_w > vop->max_output.width) { 485 printf("Maximum destination width %d exceeded\n", 486 vop->max_output.width); 487 return; 488 } 489 490 if (!vop->win->scl->ext) { 491 VOP_SCL_SET(vop, scale_yrgb_x, 492 scl_cal_scale2(src_w, dst_w)); 493 VOP_SCL_SET(vop, scale_yrgb_y, 494 scl_cal_scale2(src_h, dst_h)); 495 if (is_yuv) { 496 VOP_SCL_SET(vop, scale_cbcr_x, 497 scl_cal_scale2(src_w, dst_w)); 498 VOP_SCL_SET(vop, scale_cbcr_y, 499 scl_cal_scale2(src_h, dst_h)); 500 } 501 return; 502 } 503 504 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 505 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 506 507 if (is_yuv) { 508 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 509 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 510 if (cbcr_hor_scl_mode == SCALE_DOWN) 511 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 512 else 513 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 514 } else { 515 if (yrgb_hor_scl_mode == SCALE_DOWN) 516 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 517 else 518 lb_mode = scl_vop_cal_lb_mode(src_w, false); 519 } 520 521 VOP_SCL_SET_EXT(vop, lb_mode, lb_mode); 522 if (lb_mode == LB_RGB_3840X2) { 523 if (yrgb_ver_scl_mode != SCALE_NONE) { 524 printf("ERROR : not allow yrgb ver scale\n"); 525 return; 526 } 527 if (cbcr_ver_scl_mode != SCALE_NONE) { 528 printf("ERROR : not allow cbcr ver scale\n"); 529 return; 530 } 531 vsu_mode = SCALE_UP_BIL; 532 } else if (lb_mode == LB_RGB_2560X4) { 533 vsu_mode = SCALE_UP_BIL; 534 } else { 535 vsu_mode = SCALE_UP_BIC; 536 } 537 538 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 539 true, 0, NULL); 540 VOP_SCL_SET(vop, scale_yrgb_x, val); 541 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 542 false, vsu_mode, &vskiplines); 543 VOP_SCL_SET(vop, scale_yrgb_y, val); 544 545 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt4, vskiplines == 4); 546 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt2, vskiplines == 2); 547 548 VOP_SCL_SET_EXT(vop, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 549 VOP_SCL_SET_EXT(vop, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 550 VOP_SCL_SET_EXT(vop, yrgb_hsd_mode, SCALE_DOWN_BIL); 551 VOP_SCL_SET_EXT(vop, yrgb_vsd_mode, SCALE_DOWN_BIL); 552 VOP_SCL_SET_EXT(vop, yrgb_vsu_mode, vsu_mode); 553 if (is_yuv) { 554 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 555 dst_w, true, 0, NULL); 556 VOP_SCL_SET(vop, scale_cbcr_x, val); 557 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 558 dst_h, false, vsu_mode, &vskiplines); 559 VOP_SCL_SET(vop, scale_cbcr_y, val); 560 561 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt4, vskiplines == 4); 562 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt2, vskiplines == 2); 563 VOP_SCL_SET_EXT(vop, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 564 VOP_SCL_SET_EXT(vop, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 565 VOP_SCL_SET_EXT(vop, cbcr_hsd_mode, SCALE_DOWN_BIL); 566 VOP_SCL_SET_EXT(vop, cbcr_vsd_mode, SCALE_DOWN_BIL); 567 VOP_SCL_SET_EXT(vop, cbcr_vsu_mode, vsu_mode); 568 } 569 } 570 571 static int rockchip_vop_set_plane(struct display_state *state) 572 { 573 struct crtc_state *crtc_state = &state->crtc_state; 574 struct connector_state *conn_state = &state->conn_state; 575 struct drm_display_mode *mode = &conn_state->mode; 576 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 577 struct vop *vop = crtc_state->private; 578 int src_w = crtc_state->src_w; 579 int src_h = crtc_state->src_h; 580 int crtc_x = crtc_state->crtc_x; 581 int crtc_y = crtc_state->crtc_y; 582 int crtc_w = crtc_state->crtc_w; 583 int crtc_h = crtc_state->crtc_h; 584 int xvir = crtc_state->xvir; 585 586 act_info = (src_h - 1) << 16; 587 act_info |= (src_w - 1) & 0xffff; 588 589 dsp_info = (crtc_h - 1) << 16; 590 dsp_info |= (crtc_w - 1) & 0xffff; 591 592 dsp_stx = crtc_x + mode->htotal - mode->hsync_start; 593 dsp_sty = crtc_y + mode->vtotal - mode->vsync_start; 594 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 595 596 if (crtc_state->ymirror) { 597 if (VOP_WIN_SUPPORT(vop, vop->win, ymirror)) 598 crtc_state->dma_addr += (src_h - 1) * xvir * 4; 599 else 600 crtc_state->ymirror = 0; 601 } 602 VOP_WIN_SET(vop, ymirror, crtc_state->ymirror); 603 VOP_WIN_SET(vop, format, crtc_state->format); 604 VOP_WIN_SET(vop, yrgb_vir, xvir); 605 VOP_WIN_SET(vop, yrgb_mst, crtc_state->dma_addr); 606 607 scl_vop_cal_scl_fac(vop, src_w, src_h, crtc_w, crtc_h, 608 crtc_state->format); 609 610 VOP_WIN_SET(vop, act_info, act_info); 611 VOP_WIN_SET(vop, dsp_info, dsp_info); 612 VOP_WIN_SET(vop, dsp_st, dsp_st); 613 VOP_WIN_SET(vop, rb_swap, crtc_state->rb_swap); 614 615 VOP_WIN_SET(vop, src_alpha_ctl, 0); 616 617 VOP_WIN_SET(vop, enable, 1); 618 vop_cfg_done(vop); 619 620 return 0; 621 } 622 623 static int rockchip_vop_prepare(struct display_state *state) 624 { 625 return 0; 626 } 627 628 static int rockchip_vop_enable(struct display_state *state) 629 { 630 struct crtc_state *crtc_state = &state->crtc_state; 631 struct vop *vop = crtc_state->private; 632 633 VOP_CTRL_SET(vop, standby, 0); 634 vop_cfg_done(vop); 635 636 return 0; 637 } 638 639 static int rockchip_vop_disable(struct display_state *state) 640 { 641 struct crtc_state *crtc_state = &state->crtc_state; 642 struct vop *vop = crtc_state->private; 643 644 VOP_CTRL_SET(vop, standby, 1); 645 vop_cfg_done(vop); 646 return 0; 647 } 648 649 static int rockchip_vop_fixup_dts(struct display_state *state, void *blob) 650 { 651 #if 0 652 struct crtc_state *crtc_state = &state->crtc_state; 653 struct panel_state *pstate = &state->panel_state; 654 uint32_t phandle; 655 char path[100]; 656 int ret, dsp_lut_node; 657 658 if (!ofnode_valid(pstate->dsp_lut_node)) 659 return 0; 660 ret = fdt_get_path(state->blob, pstate->dsp_lut_node, path, sizeof(path)); 661 if (ret < 0) { 662 printf("failed to get dsp_lut path[%s], ret=%d\n", 663 path, ret); 664 return ret; 665 } 666 667 dsp_lut_node = fdt_path_offset(blob, path); 668 phandle = fdt_get_phandle(blob, dsp_lut_node); 669 if (!phandle) { 670 phandle = fdt_alloc_phandle(blob); 671 if (!phandle) { 672 printf("failed to alloc phandle\n"); 673 return -ENOMEM; 674 } 675 676 fdt_set_phandle(blob, dsp_lut_node, phandle); 677 } 678 679 ret = fdt_get_path(state->blob, crtc_state->node, path, sizeof(path)); 680 if (ret < 0) { 681 printf("failed to get route path[%s], ret=%d\n", 682 path, ret); 683 return ret; 684 } 685 686 do_fixup_by_path_u32(blob, path, "dsp-lut", phandle, 1); 687 #endif 688 return 0; 689 } 690 691 const struct rockchip_crtc_funcs rockchip_vop_funcs = { 692 .init = rockchip_vop_init, 693 .set_plane = rockchip_vop_set_plane, 694 .prepare = rockchip_vop_prepare, 695 .enable = rockchip_vop_enable, 696 .disable = rockchip_vop_disable, 697 .fixup_dts = rockchip_vop_fixup_dts, 698 }; 699