1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <asm/io.h> 15 #include <linux/list.h> 16 #include <linux/media-bus-format.h> 17 #include <clk.h> 18 #include <asm/arch/clock.h> 19 #include <linux/err.h> 20 #include <dm/device.h> 21 #include <dm/read.h> 22 #include <syscon.h> 23 24 #include "rockchip_display.h" 25 #include "rockchip_crtc.h" 26 #include "rockchip_connector.h" 27 #include "rockchip_vop.h" 28 29 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 30 { 31 return us * mode->clock / mode->htotal / 1000; 32 } 33 34 static int to_vop_csc_mode(int csc_mode) 35 { 36 switch (csc_mode) { 37 case V4L2_COLORSPACE_SMPTE170M: 38 return CSC_BT601L; 39 case V4L2_COLORSPACE_REC709: 40 case V4L2_COLORSPACE_DEFAULT: 41 return CSC_BT709L; 42 case V4L2_COLORSPACE_JPEG: 43 return CSC_BT601F; 44 case V4L2_COLORSPACE_BT2020: 45 return CSC_BT2020; 46 default: 47 return CSC_BT709L; 48 } 49 } 50 51 static bool is_yuv_output(uint32_t bus_format) 52 { 53 switch (bus_format) { 54 case MEDIA_BUS_FMT_YUV8_1X24: 55 case MEDIA_BUS_FMT_YUV10_1X30: 56 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 57 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 58 return true; 59 default: 60 return false; 61 } 62 } 63 64 static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode) 65 { 66 /* 67 * FIXME: 68 * 69 * There is no media type for YUV444 output, 70 * so when out_mode is AAAA or P888, assume output is YUV444 on 71 * yuv format. 72 * 73 * From H/W testing, YUV444 mode need a rb swap. 74 */ 75 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 76 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 77 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 78 output_mode == ROCKCHIP_OUT_MODE_P888)) 79 return true; 80 else 81 return false; 82 } 83 84 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) 85 { 86 struct crtc_state *crtc_state = &state->crtc_state; 87 struct connector_state *conn_state = &state->conn_state; 88 u32 *lut = conn_state->gamma.lut; 89 fdt_size_t lut_size; 90 int i, lut_len; 91 u32 *lut_regs; 92 93 if (!conn_state->gamma.lut) 94 return 0; 95 96 i = dev_read_stringlist_search(crtc_state->dev, "reg-names", "gamma_lut"); 97 if (i < 0) { 98 printf("Warning: vop not support gamma\n"); 99 return 0; 100 } 101 lut_regs = (u32 *)dev_read_addr_size(crtc_state->dev, "reg", &lut_size); 102 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 103 printf("failed to get gamma lut register\n"); 104 return 0; 105 } 106 lut_len = lut_size / 4; 107 if (lut_len != 256 && lut_len != 1024) { 108 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 109 return 0; 110 } 111 112 if (conn_state->gamma.size != lut_len) { 113 int size = conn_state->gamma.size; 114 u32 j, r, g, b, color; 115 116 for (i = 0; i < lut_len; i++) { 117 j = i * size / lut_len; 118 r = lut[j] / size / size * lut_len / size; 119 g = lut[j] / size % size * lut_len / size; 120 b = lut[j] % size * lut_len / size; 121 color = r * lut_len * lut_len + g * lut_len + b; 122 123 writel(color, lut_regs + (i << 2)); 124 } 125 } else { 126 for (i = 0; i < lut_len; i++) 127 writel(lut[i], lut_regs + (i << 2)); 128 } 129 130 VOP_CTRL_SET(vop, dsp_lut_en, 1); 131 VOP_CTRL_SET(vop, update_gamma_lut, 1); 132 133 return 0; 134 } 135 136 static void vop_post_config(struct display_state *state, struct vop *vop) 137 { 138 struct connector_state *conn_state = &state->conn_state; 139 struct drm_display_mode *mode = &conn_state->mode; 140 u16 vtotal = mode->crtc_vtotal; 141 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 142 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 143 u16 hdisplay = mode->crtc_hdisplay; 144 u16 vdisplay = mode->crtc_vdisplay; 145 u16 hsize = hdisplay * (conn_state->overscan.left_margin + conn_state->overscan.right_margin) / 200; 146 u16 vsize = vdisplay * (conn_state->overscan.top_margin + conn_state->overscan.bottom_margin) / 200; 147 u16 hact_end, vact_end; 148 u32 val; 149 150 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 151 vsize = round_down(vsize, 2); 152 153 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 154 hact_end = hact_st + hsize; 155 val = hact_st << 16; 156 val |= hact_end; 157 158 VOP_CTRL_SET(vop, hpost_st_end, val); 159 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 160 vact_end = vact_st + vsize; 161 val = vact_st << 16; 162 val |= vact_end; 163 VOP_CTRL_SET(vop, vpost_st_end, val); 164 val = scl_cal_scale2(vdisplay, vsize) << 16; 165 val |= scl_cal_scale2(hdisplay, hsize); 166 VOP_CTRL_SET(vop, post_scl_factor, val); 167 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 168 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 169 VOP_CTRL_SET(vop, post_scl_ctrl, 170 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 171 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 172 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 173 u16 vact_st_f1 = vtotal + vact_st + 1; 174 u16 vact_end_f1 = vact_st_f1 + vsize; 175 176 val = vact_st_f1 << 16 | vact_end_f1; 177 VOP_CTRL_SET(vop, vpost_st_end_f1, val); 178 } 179 } 180 181 static int rockchip_vop_init(struct display_state *state) 182 { 183 struct crtc_state *crtc_state = &state->crtc_state; 184 struct connector_state *conn_state = &state->conn_state; 185 struct drm_display_mode *mode = &conn_state->mode; 186 const struct rockchip_crtc *crtc = crtc_state->crtc; 187 const struct vop_data *vop_data = crtc->data; 188 struct vop *vop; 189 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 190 u16 hdisplay = mode->crtc_hdisplay; 191 u16 htotal = mode->crtc_htotal; 192 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 193 u16 hact_end = hact_st + hdisplay; 194 u16 vdisplay = mode->crtc_vdisplay; 195 u16 vtotal = mode->crtc_vtotal; 196 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 197 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 198 u16 vact_end = vact_st + vdisplay; 199 struct clk dclk, aclk; 200 u32 val, act_end; 201 int ret; 202 bool yuv_overlay = false, post_r2y_en = false, post_y2r_en = false; 203 u16 post_csc_mode; 204 bool dclk_inv; 205 206 vop = malloc(sizeof(*vop)); 207 if (!vop) 208 return -ENOMEM; 209 memset(vop, 0, sizeof(*vop)); 210 211 crtc_state->private = vop; 212 vop->regs = dev_read_addr_ptr(crtc_state->dev); 213 vop->regsbak = malloc(vop_data->reg_len); 214 vop->win = vop_data->win; 215 vop->win_offset = vop_data->win_offset; 216 vop->ctrl = vop_data->ctrl; 217 vop->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 218 if (vop->grf <= 0) 219 printf("%s: Get syscon grf failed (ret=%p)\n", 220 __func__, vop->grf); 221 222 vop->grf_ctrl = vop_data->grf_ctrl; 223 vop->line_flag = vop_data->line_flag; 224 vop->version = vop_data->version; 225 vop->max_output = vop_data->max_output; 226 227 /* 228 * TODO: 229 * Set Dclk pll parent 230 */ 231 232 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &dclk); 233 if (!ret) 234 ret = clk_set_rate(&dclk, mode->clock * 1000); 235 if (IS_ERR_VALUE(ret)) { 236 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret); 237 return ret; 238 } 239 240 ret = clk_get_by_name(crtc_state->dev, "aclk_vop", &aclk); 241 if (!ret) 242 ret = clk_set_rate(&aclk, 400 * 1000 * 1000); 243 if (IS_ERR_VALUE(ret)) 244 printf("%s: Failed to set aclk: ret=%d\n", __func__, ret); 245 246 memcpy(vop->regsbak, vop->regs, vop_data->reg_len); 247 248 rockchip_vop_init_gamma(vop, state); 249 250 VOP_CTRL_SET(vop, global_regdone_en, 1); 251 VOP_CTRL_SET(vop, axi_outstanding_max_num, 30); 252 VOP_CTRL_SET(vop, axi_max_outstanding_en, 1); 253 VOP_CTRL_SET(vop, reg_done_frm, 1); 254 VOP_CTRL_SET(vop, win_gate[0], 1); 255 VOP_CTRL_SET(vop, win_gate[1], 1); 256 VOP_CTRL_SET(vop, win_channel[0], 0x12); 257 VOP_CTRL_SET(vop, win_channel[1], 0x34); 258 VOP_CTRL_SET(vop, win_channel[2], 0x56); 259 VOP_CTRL_SET(vop, dsp_blank, 0); 260 261 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 262 VOP_CTRL_SET(vop, dclk_pol, dclk_inv); 263 264 val = 0x8; 265 val |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 266 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 267 VOP_CTRL_SET(vop, pin_pol, val); 268 269 switch (conn_state->type) { 270 case DRM_MODE_CONNECTOR_LVDS: 271 VOP_CTRL_SET(vop, rgb_en, 1); 272 VOP_CTRL_SET(vop, rgb_pin_pol, val); 273 VOP_CTRL_SET(vop, rgb_dclk_pol, dclk_inv); 274 VOP_CTRL_SET(vop, lvds_en, 1); 275 VOP_CTRL_SET(vop, lvds_pin_pol, val); 276 VOP_CTRL_SET(vop, lvds_dclk_pol, dclk_inv); 277 if (!IS_ERR_OR_NULL(vop->grf)) 278 VOP_GRF_SET(vop, grf_dclk_inv, !dclk_inv); 279 break; 280 case DRM_MODE_CONNECTOR_eDP: 281 VOP_CTRL_SET(vop, edp_en, 1); 282 VOP_CTRL_SET(vop, edp_pin_pol, val); 283 VOP_CTRL_SET(vop, edp_dclk_pol, dclk_inv); 284 break; 285 case DRM_MODE_CONNECTOR_HDMIA: 286 VOP_CTRL_SET(vop, hdmi_en, 1); 287 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 288 VOP_CTRL_SET(vop, hdmi_dclk_pol, 1); 289 break; 290 case DRM_MODE_CONNECTOR_DSI: 291 VOP_CTRL_SET(vop, mipi_en, 1); 292 VOP_CTRL_SET(vop, mipi_pin_pol, val); 293 VOP_CTRL_SET(vop, mipi_dclk_pol, dclk_inv); 294 VOP_CTRL_SET(vop, mipi_dual_channel_en, 295 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL)); 296 VOP_CTRL_SET(vop, data01_swap, 297 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_LINK)); 298 break; 299 case DRM_MODE_CONNECTOR_DisplayPort: 300 VOP_CTRL_SET(vop, dp_dclk_pol, 0); 301 VOP_CTRL_SET(vop, dp_pin_pol, val); 302 VOP_CTRL_SET(vop, dp_en, 1); 303 break; 304 case DRM_MODE_CONNECTOR_TV: 305 if (vdisplay == CVBS_PAL_VDISPLAY) 306 VOP_CTRL_SET(vop, tve_sw_mode, 1); 307 else 308 VOP_CTRL_SET(vop, tve_sw_mode, 0); 309 VOP_CTRL_SET(vop, tve_dclk_pol, 1); 310 VOP_CTRL_SET(vop, tve_dclk_en, 1); 311 /* use the same pol reg with hdmi */ 312 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 313 VOP_CTRL_SET(vop, sw_genlock, 1); 314 VOP_CTRL_SET(vop, sw_uv_offset_en, 1); 315 VOP_CTRL_SET(vop, dither_up, 1); 316 break; 317 default: 318 printf("unsupport connector_type[%d]\n", conn_state->type); 319 } 320 321 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 322 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 323 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 324 325 switch (conn_state->bus_format) { 326 case MEDIA_BUS_FMT_RGB565_1X16: 327 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565); 328 break; 329 case MEDIA_BUS_FMT_RGB666_1X18: 330 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 331 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666); 332 break; 333 case MEDIA_BUS_FMT_YUV8_1X24: 334 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 335 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1); 336 break; 337 case MEDIA_BUS_FMT_YUV10_1X30: 338 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 339 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 340 break; 341 case MEDIA_BUS_FMT_RGB888_1X24: 342 default: 343 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 344 break; 345 } 346 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 347 val |= PRE_DITHER_DOWN_EN(0); 348 else 349 val |= PRE_DITHER_DOWN_EN(1); 350 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO); 351 VOP_CTRL_SET(vop, dither_down, val); 352 353 VOP_CTRL_SET(vop, dclk_ddr, 354 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 355 VOP_CTRL_SET(vop, hdmi_dclk_out_en, 356 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 357 358 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 359 VOP_CTRL_SET(vop, dsp_data_swap, DSP_RB_SWAP); 360 else 361 VOP_CTRL_SET(vop, dsp_data_swap, 0); 362 363 VOP_CTRL_SET(vop, out_mode, conn_state->output_mode); 364 365 if (VOP_CTRL_SUPPORT(vop, overlay_mode)) { 366 yuv_overlay = is_yuv_output(conn_state->bus_format); 367 VOP_CTRL_SET(vop, overlay_mode, yuv_overlay); 368 } 369 /* 370 * todo: r2y for win csc 371 */ 372 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(conn_state->bus_format)); 373 374 if (yuv_overlay) { 375 if (!is_yuv_output(conn_state->bus_format)) 376 post_y2r_en = true; 377 } else { 378 if (is_yuv_output(conn_state->bus_format)) 379 post_r2y_en = true; 380 } 381 382 post_csc_mode = to_vop_csc_mode(conn_state->color_space); 383 VOP_CTRL_SET(vop, bcsh_r2y_en, post_r2y_en); 384 VOP_CTRL_SET(vop, bcsh_y2r_en, post_y2r_en); 385 VOP_CTRL_SET(vop, bcsh_r2y_csc_mode, post_csc_mode); 386 VOP_CTRL_SET(vop, bcsh_y2r_csc_mode, post_csc_mode); 387 388 /* 389 * Background color is 10bit depth if vop version >= 3.5 390 */ 391 if (!is_yuv_output(conn_state->bus_format)) 392 val = 0; 393 else if (VOP_MAJOR(vop->version) == 3 && 394 VOP_MINOR(vop->version) >= 5) 395 val = 0x20010200; 396 else 397 val = 0x801080; 398 VOP_CTRL_SET(vop, dsp_background, val); 399 400 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 401 val = hact_st << 16; 402 val |= hact_end; 403 VOP_CTRL_SET(vop, hact_st_end, val); 404 val = vact_st << 16; 405 val |= vact_end; 406 VOP_CTRL_SET(vop, vact_st_end, val); 407 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 408 u16 vact_st_f1 = vtotal + vact_st + 1; 409 u16 vact_end_f1 = vact_st_f1 + vdisplay; 410 411 val = vact_st_f1 << 16 | vact_end_f1; 412 VOP_CTRL_SET(vop, vact_st_end_f1, val); 413 414 val = vtotal << 16 | (vtotal + vsync_len); 415 VOP_CTRL_SET(vop, vs_st_end_f1, val); 416 VOP_CTRL_SET(vop, dsp_interlace, 1); 417 VOP_CTRL_SET(vop, p2i_en, 1); 418 vtotal += vtotal + 1; 419 act_end = vact_end_f1; 420 } else { 421 VOP_CTRL_SET(vop, dsp_interlace, 0); 422 VOP_CTRL_SET(vop, p2i_en, 0); 423 act_end = vact_end; 424 } 425 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 426 vop_post_config(state, vop); 427 VOP_CTRL_SET(vop, core_dclk_div, 428 !!(mode->flags & DRM_MODE_FLAG_DBLCLK)); 429 430 VOP_CTRL_SET(vop, standby, 1); 431 VOP_LINE_FLAG_SET(vop, line_flag_num[0], act_end - 3); 432 VOP_LINE_FLAG_SET(vop, line_flag_num[1], 433 act_end - us_to_vertical_line(mode, 1000)); 434 vop_cfg_done(vop); 435 436 return 0; 437 } 438 439 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 440 uint32_t dst, bool is_horizontal, 441 int vsu_mode, int *vskiplines) 442 { 443 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 444 445 if (is_horizontal) { 446 if (mode == SCALE_UP) 447 val = GET_SCL_FT_BIC(src, dst); 448 else if (mode == SCALE_DOWN) 449 val = GET_SCL_FT_BILI_DN(src, dst); 450 } else { 451 if (mode == SCALE_UP) { 452 if (vsu_mode == SCALE_UP_BIL) 453 val = GET_SCL_FT_BILI_UP(src, dst); 454 else 455 val = GET_SCL_FT_BIC(src, dst); 456 } else if (mode == SCALE_DOWN) { 457 if (vskiplines) { 458 *vskiplines = scl_get_vskiplines(src, dst); 459 val = scl_get_bili_dn_vskip(src, dst, 460 *vskiplines); 461 } else { 462 val = GET_SCL_FT_BILI_DN(src, dst); 463 } 464 } 465 } 466 467 return val; 468 } 469 470 static void scl_vop_cal_scl_fac(struct vop *vop, 471 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 472 uint32_t dst_h, uint32_t pixel_format) 473 { 474 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 475 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 476 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 477 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 478 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 479 bool is_yuv = false; 480 uint16_t cbcr_src_w = src_w / hsub; 481 uint16_t cbcr_src_h = src_h / vsub; 482 uint16_t vsu_mode; 483 uint16_t lb_mode; 484 uint32_t val; 485 int vskiplines = 0; 486 487 if (!vop->win->scl) 488 return; 489 490 if (dst_w > vop->max_output.width) { 491 printf("Maximum destination width %d exceeded\n", 492 vop->max_output.width); 493 return; 494 } 495 496 if (!vop->win->scl->ext) { 497 VOP_SCL_SET(vop, scale_yrgb_x, 498 scl_cal_scale2(src_w, dst_w)); 499 VOP_SCL_SET(vop, scale_yrgb_y, 500 scl_cal_scale2(src_h, dst_h)); 501 if (is_yuv) { 502 VOP_SCL_SET(vop, scale_cbcr_x, 503 scl_cal_scale2(src_w, dst_w)); 504 VOP_SCL_SET(vop, scale_cbcr_y, 505 scl_cal_scale2(src_h, dst_h)); 506 } 507 return; 508 } 509 510 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 511 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 512 513 if (is_yuv) { 514 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 515 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 516 if (cbcr_hor_scl_mode == SCALE_DOWN) 517 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 518 else 519 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 520 } else { 521 if (yrgb_hor_scl_mode == SCALE_DOWN) 522 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 523 else 524 lb_mode = scl_vop_cal_lb_mode(src_w, false); 525 } 526 527 VOP_SCL_SET_EXT(vop, lb_mode, lb_mode); 528 if (lb_mode == LB_RGB_3840X2) { 529 if (yrgb_ver_scl_mode != SCALE_NONE) { 530 printf("ERROR : not allow yrgb ver scale\n"); 531 return; 532 } 533 if (cbcr_ver_scl_mode != SCALE_NONE) { 534 printf("ERROR : not allow cbcr ver scale\n"); 535 return; 536 } 537 vsu_mode = SCALE_UP_BIL; 538 } else if (lb_mode == LB_RGB_2560X4) { 539 vsu_mode = SCALE_UP_BIL; 540 } else { 541 vsu_mode = SCALE_UP_BIC; 542 } 543 544 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 545 true, 0, NULL); 546 VOP_SCL_SET(vop, scale_yrgb_x, val); 547 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 548 false, vsu_mode, &vskiplines); 549 VOP_SCL_SET(vop, scale_yrgb_y, val); 550 551 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt4, vskiplines == 4); 552 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt2, vskiplines == 2); 553 554 VOP_SCL_SET_EXT(vop, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 555 VOP_SCL_SET_EXT(vop, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 556 VOP_SCL_SET_EXT(vop, yrgb_hsd_mode, SCALE_DOWN_BIL); 557 VOP_SCL_SET_EXT(vop, yrgb_vsd_mode, SCALE_DOWN_BIL); 558 VOP_SCL_SET_EXT(vop, yrgb_vsu_mode, vsu_mode); 559 if (is_yuv) { 560 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 561 dst_w, true, 0, NULL); 562 VOP_SCL_SET(vop, scale_cbcr_x, val); 563 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 564 dst_h, false, vsu_mode, &vskiplines); 565 VOP_SCL_SET(vop, scale_cbcr_y, val); 566 567 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt4, vskiplines == 4); 568 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt2, vskiplines == 2); 569 VOP_SCL_SET_EXT(vop, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 570 VOP_SCL_SET_EXT(vop, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 571 VOP_SCL_SET_EXT(vop, cbcr_hsd_mode, SCALE_DOWN_BIL); 572 VOP_SCL_SET_EXT(vop, cbcr_vsd_mode, SCALE_DOWN_BIL); 573 VOP_SCL_SET_EXT(vop, cbcr_vsu_mode, vsu_mode); 574 } 575 } 576 577 static int rockchip_vop_set_plane(struct display_state *state) 578 { 579 struct crtc_state *crtc_state = &state->crtc_state; 580 struct connector_state *conn_state = &state->conn_state; 581 struct drm_display_mode *mode = &conn_state->mode; 582 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 583 struct vop *vop = crtc_state->private; 584 int src_w = crtc_state->src_w; 585 int src_h = crtc_state->src_h; 586 int crtc_x = crtc_state->crtc_x; 587 int crtc_y = crtc_state->crtc_y; 588 int crtc_w = crtc_state->crtc_w; 589 int crtc_h = crtc_state->crtc_h; 590 int xvir = crtc_state->xvir; 591 592 act_info = (src_h - 1) << 16; 593 act_info |= (src_w - 1) & 0xffff; 594 595 dsp_info = (crtc_h - 1) << 16; 596 dsp_info |= (crtc_w - 1) & 0xffff; 597 598 dsp_stx = crtc_x + mode->htotal - mode->hsync_start; 599 dsp_sty = crtc_y + mode->vtotal - mode->vsync_start; 600 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 601 602 if (crtc_state->ymirror) { 603 if (VOP_WIN_SUPPORT(vop, vop->win, ymirror)) 604 crtc_state->dma_addr += (src_h - 1) * xvir * 4; 605 else 606 crtc_state->ymirror = 0; 607 } 608 VOP_WIN_SET(vop, ymirror, crtc_state->ymirror); 609 VOP_WIN_SET(vop, format, crtc_state->format); 610 VOP_WIN_SET(vop, yrgb_vir, xvir); 611 VOP_WIN_SET(vop, yrgb_mst, crtc_state->dma_addr); 612 613 scl_vop_cal_scl_fac(vop, src_w, src_h, crtc_w, crtc_h, 614 crtc_state->format); 615 616 VOP_WIN_SET(vop, act_info, act_info); 617 VOP_WIN_SET(vop, dsp_info, dsp_info); 618 VOP_WIN_SET(vop, dsp_st, dsp_st); 619 VOP_WIN_SET(vop, rb_swap, crtc_state->rb_swap); 620 621 VOP_WIN_SET(vop, src_alpha_ctl, 0); 622 623 VOP_WIN_SET(vop, enable, 1); 624 vop_cfg_done(vop); 625 626 return 0; 627 } 628 629 static int rockchip_vop_prepare(struct display_state *state) 630 { 631 return 0; 632 } 633 634 static int rockchip_vop_enable(struct display_state *state) 635 { 636 struct crtc_state *crtc_state = &state->crtc_state; 637 struct vop *vop = crtc_state->private; 638 639 VOP_CTRL_SET(vop, standby, 0); 640 vop_cfg_done(vop); 641 642 return 0; 643 } 644 645 static int rockchip_vop_disable(struct display_state *state) 646 { 647 struct crtc_state *crtc_state = &state->crtc_state; 648 struct vop *vop = crtc_state->private; 649 650 VOP_CTRL_SET(vop, standby, 1); 651 vop_cfg_done(vop); 652 return 0; 653 } 654 655 static int rockchip_vop_fixup_dts(struct display_state *state, void *blob) 656 { 657 #if 0 658 struct crtc_state *crtc_state = &state->crtc_state; 659 struct panel_state *pstate = &state->panel_state; 660 uint32_t phandle; 661 char path[100]; 662 int ret, dsp_lut_node; 663 664 if (!ofnode_valid(pstate->dsp_lut_node)) 665 return 0; 666 ret = fdt_get_path(state->blob, pstate->dsp_lut_node, path, sizeof(path)); 667 if (ret < 0) { 668 printf("failed to get dsp_lut path[%s], ret=%d\n", 669 path, ret); 670 return ret; 671 } 672 673 dsp_lut_node = fdt_path_offset(blob, path); 674 phandle = fdt_get_phandle(blob, dsp_lut_node); 675 if (!phandle) { 676 phandle = fdt_alloc_phandle(blob); 677 if (!phandle) { 678 printf("failed to alloc phandle\n"); 679 return -ENOMEM; 680 } 681 682 fdt_set_phandle(blob, dsp_lut_node, phandle); 683 } 684 685 ret = fdt_get_path(state->blob, crtc_state->node, path, sizeof(path)); 686 if (ret < 0) { 687 printf("failed to get route path[%s], ret=%d\n", 688 path, ret); 689 return ret; 690 } 691 692 do_fixup_by_path_u32(blob, path, "dsp-lut", phandle, 1); 693 #endif 694 return 0; 695 } 696 697 const struct rockchip_crtc_funcs rockchip_vop_funcs = { 698 .init = rockchip_vop_init, 699 .set_plane = rockchip_vop_set_plane, 700 .prepare = rockchip_vop_prepare, 701 .enable = rockchip_vop_enable, 702 .disable = rockchip_vop_disable, 703 .fixup_dts = rockchip_vop_fixup_dts, 704 }; 705