1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <asm/io.h> 15 #include <linux/list.h> 16 #include <linux/media-bus-format.h> 17 #include <clk.h> 18 #include <asm/arch/clock.h> 19 #include <linux/err.h> 20 #include <dm/device.h> 21 #include <dm/read.h> 22 #include <syscon.h> 23 24 #include "rockchip_display.h" 25 #include "rockchip_crtc.h" 26 #include "rockchip_connector.h" 27 #include "rockchip_vop.h" 28 29 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 30 { 31 return us * mode->clock / mode->htotal / 1000; 32 } 33 34 static int to_vop_csc_mode(int csc_mode) 35 { 36 switch (csc_mode) { 37 case V4L2_COLORSPACE_SMPTE170M: 38 return CSC_BT601L; 39 case V4L2_COLORSPACE_REC709: 40 case V4L2_COLORSPACE_DEFAULT: 41 return CSC_BT709L; 42 case V4L2_COLORSPACE_JPEG: 43 return CSC_BT601F; 44 case V4L2_COLORSPACE_BT2020: 45 return CSC_BT2020; 46 default: 47 return CSC_BT709L; 48 } 49 } 50 51 static bool is_yuv_output(uint32_t bus_format) 52 { 53 switch (bus_format) { 54 case MEDIA_BUS_FMT_YUV8_1X24: 55 case MEDIA_BUS_FMT_YUV10_1X30: 56 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 57 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 58 return true; 59 default: 60 return false; 61 } 62 } 63 64 static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode) 65 { 66 /* 67 * FIXME: 68 * 69 * There is no media type for YUV444 output, 70 * so when out_mode is AAAA or P888, assume output is YUV444 on 71 * yuv format. 72 * 73 * From H/W testing, YUV444 mode need a rb swap. 74 */ 75 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 76 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 77 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 78 output_mode == ROCKCHIP_OUT_MODE_P888)) 79 return true; 80 else 81 return false; 82 } 83 84 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) 85 { 86 struct crtc_state *crtc_state = &state->crtc_state; 87 struct connector_state *conn_state = &state->conn_state; 88 u32 *lut = conn_state->gamma.lut; 89 fdt_size_t lut_size; 90 int i, lut_len; 91 u32 *lut_regs; 92 93 if (!conn_state->gamma.lut) 94 return 0; 95 96 i = dev_read_stringlist_search(crtc_state->dev, "reg-names", "gamma_lut"); 97 if (i < 0) { 98 printf("Warning: vop not support gamma\n"); 99 return 0; 100 } 101 lut_regs = (u32 *)dev_read_addr_size(crtc_state->dev, "reg", &lut_size); 102 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 103 printf("failed to get gamma lut register\n"); 104 return 0; 105 } 106 lut_len = lut_size / 4; 107 if (lut_len != 256 && lut_len != 1024) { 108 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 109 return 0; 110 } 111 112 if (conn_state->gamma.size != lut_len) { 113 int size = conn_state->gamma.size; 114 u32 j, r, g, b, color; 115 116 for (i = 0; i < lut_len; i++) { 117 j = i * size / lut_len; 118 r = lut[j] / size / size * lut_len / size; 119 g = lut[j] / size % size * lut_len / size; 120 b = lut[j] % size * lut_len / size; 121 color = r * lut_len * lut_len + g * lut_len + b; 122 123 writel(color, lut_regs + (i << 2)); 124 } 125 } else { 126 for (i = 0; i < lut_len; i++) 127 writel(lut[i], lut_regs + (i << 2)); 128 } 129 130 VOP_CTRL_SET(vop, dsp_lut_en, 1); 131 VOP_CTRL_SET(vop, update_gamma_lut, 1); 132 133 return 0; 134 } 135 136 static void vop_post_config(struct display_state *state, struct vop *vop) 137 { 138 struct connector_state *conn_state = &state->conn_state; 139 struct drm_display_mode *mode = &conn_state->mode; 140 u16 vtotal = mode->crtc_vtotal; 141 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 142 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 143 u16 hdisplay = mode->crtc_hdisplay; 144 u16 vdisplay = mode->crtc_vdisplay; 145 u16 hsize = hdisplay * (conn_state->overscan.left_margin + conn_state->overscan.right_margin) / 200; 146 u16 vsize = vdisplay * (conn_state->overscan.top_margin + conn_state->overscan.bottom_margin) / 200; 147 u16 hact_end, vact_end; 148 u32 val; 149 150 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 151 vsize = round_down(vsize, 2); 152 153 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 154 hact_end = hact_st + hsize; 155 val = hact_st << 16; 156 val |= hact_end; 157 158 VOP_CTRL_SET(vop, hpost_st_end, val); 159 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 160 vact_end = vact_st + vsize; 161 val = vact_st << 16; 162 val |= vact_end; 163 VOP_CTRL_SET(vop, vpost_st_end, val); 164 val = scl_cal_scale2(vdisplay, vsize) << 16; 165 val |= scl_cal_scale2(hdisplay, hsize); 166 VOP_CTRL_SET(vop, post_scl_factor, val); 167 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 168 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 169 VOP_CTRL_SET(vop, post_scl_ctrl, 170 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 171 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 172 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 173 u16 vact_st_f1 = vtotal + vact_st + 1; 174 u16 vact_end_f1 = vact_st_f1 + vsize; 175 176 val = vact_st_f1 << 16 | vact_end_f1; 177 VOP_CTRL_SET(vop, vpost_st_end_f1, val); 178 } 179 } 180 181 static void vop_mcu_mode(struct display_state *state, struct vop *vop) 182 { 183 struct crtc_state *crtc_state = &state->crtc_state; 184 185 VOP_CTRL_SET(vop, mcu_clk_sel, 1); 186 VOP_CTRL_SET(vop, mcu_type, 1); 187 188 VOP_CTRL_SET(vop, mcu_hold_mode, 1); 189 VOP_CTRL_SET(vop, mcu_pix_total, crtc_state->mcu_timing.mcu_pix_total); 190 VOP_CTRL_SET(vop, mcu_cs_pst, crtc_state->mcu_timing.mcu_cs_pst); 191 VOP_CTRL_SET(vop, mcu_cs_pend, crtc_state->mcu_timing.mcu_cs_pend); 192 VOP_CTRL_SET(vop, mcu_rw_pst, crtc_state->mcu_timing.mcu_rw_pst); 193 VOP_CTRL_SET(vop, mcu_rw_pend, crtc_state->mcu_timing.mcu_rw_pend); 194 } 195 196 static int rockchip_vop_preinit(struct display_state *state) 197 { 198 const struct vop_data *vop_data = state->crtc_state.crtc->data; 199 200 state->crtc_state.max_output = vop_data->max_output; 201 202 return 0; 203 } 204 205 static int rockchip_vop_init(struct display_state *state) 206 { 207 struct crtc_state *crtc_state = &state->crtc_state; 208 struct connector_state *conn_state = &state->conn_state; 209 struct drm_display_mode *mode = &conn_state->mode; 210 const struct rockchip_crtc *crtc = crtc_state->crtc; 211 const struct vop_data *vop_data = crtc->data; 212 struct vop *vop; 213 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 214 u16 hdisplay = mode->crtc_hdisplay; 215 u16 htotal = mode->crtc_htotal; 216 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 217 u16 hact_end = hact_st + hdisplay; 218 u16 vdisplay = mode->crtc_vdisplay; 219 u16 vtotal = mode->crtc_vtotal; 220 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 221 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 222 u16 vact_end = vact_st + vdisplay; 223 struct clk dclk; 224 u32 val, act_end; 225 int ret; 226 bool yuv_overlay = false, post_r2y_en = false, post_y2r_en = false; 227 u16 post_csc_mode; 228 bool dclk_inv; 229 230 vop = malloc(sizeof(*vop)); 231 if (!vop) 232 return -ENOMEM; 233 memset(vop, 0, sizeof(*vop)); 234 235 crtc_state->private = vop; 236 vop->regs = dev_read_addr_ptr(crtc_state->dev); 237 vop->regsbak = malloc(vop_data->reg_len); 238 vop->win = vop_data->win; 239 vop->win_offset = vop_data->win_offset; 240 vop->ctrl = vop_data->ctrl; 241 vop->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 242 if (vop->grf <= 0) 243 printf("%s: Get syscon grf failed (ret=%p)\n", 244 __func__, vop->grf); 245 246 vop->grf_ctrl = vop_data->grf_ctrl; 247 vop->line_flag = vop_data->line_flag; 248 vop->csc_table = vop_data->csc_table; 249 vop->win_csc = vop_data->win_csc; 250 vop->version = vop_data->version; 251 252 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 253 ret = clk_set_defaults(crtc_state->dev); 254 if (ret) 255 debug("%s clk_set_defaults failed %d\n", __func__, ret); 256 257 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &dclk); 258 if (!ret) 259 ret = clk_set_rate(&dclk, mode->clock * 1000); 260 if (IS_ERR_VALUE(ret)) { 261 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret); 262 return ret; 263 } 264 265 memcpy(vop->regsbak, vop->regs, vop_data->reg_len); 266 267 rockchip_vop_init_gamma(vop, state); 268 269 VOP_CTRL_SET(vop, global_regdone_en, 1); 270 VOP_CTRL_SET(vop, axi_outstanding_max_num, 30); 271 VOP_CTRL_SET(vop, axi_max_outstanding_en, 1); 272 VOP_CTRL_SET(vop, reg_done_frm, 1); 273 VOP_CTRL_SET(vop, win_gate[0], 1); 274 VOP_CTRL_SET(vop, win_gate[1], 1); 275 VOP_CTRL_SET(vop, win_channel[0], 0x12); 276 VOP_CTRL_SET(vop, win_channel[1], 0x34); 277 VOP_CTRL_SET(vop, win_channel[2], 0x56); 278 VOP_CTRL_SET(vop, dsp_blank, 0); 279 280 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 281 VOP_CTRL_SET(vop, dclk_pol, dclk_inv); 282 283 val = 0x8; 284 val |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 285 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 286 VOP_CTRL_SET(vop, pin_pol, val); 287 288 switch (conn_state->type) { 289 case DRM_MODE_CONNECTOR_LVDS: 290 VOP_CTRL_SET(vop, rgb_en, 1); 291 VOP_CTRL_SET(vop, rgb_pin_pol, val); 292 VOP_CTRL_SET(vop, rgb_dclk_pol, dclk_inv); 293 VOP_CTRL_SET(vop, lvds_en, 1); 294 VOP_CTRL_SET(vop, lvds_pin_pol, val); 295 VOP_CTRL_SET(vop, lvds_dclk_pol, dclk_inv); 296 if (!IS_ERR_OR_NULL(vop->grf)) 297 VOP_GRF_SET(vop, grf_dclk_inv, !dclk_inv); 298 break; 299 case DRM_MODE_CONNECTOR_eDP: 300 VOP_CTRL_SET(vop, edp_en, 1); 301 VOP_CTRL_SET(vop, edp_pin_pol, val); 302 VOP_CTRL_SET(vop, edp_dclk_pol, dclk_inv); 303 break; 304 case DRM_MODE_CONNECTOR_HDMIA: 305 VOP_CTRL_SET(vop, hdmi_en, 1); 306 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 307 VOP_CTRL_SET(vop, hdmi_dclk_pol, 1); 308 break; 309 case DRM_MODE_CONNECTOR_DSI: 310 VOP_CTRL_SET(vop, mipi_en, 1); 311 VOP_CTRL_SET(vop, mipi_pin_pol, val); 312 VOP_CTRL_SET(vop, mipi_dclk_pol, dclk_inv); 313 VOP_CTRL_SET(vop, mipi_dual_channel_en, 314 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL)); 315 VOP_CTRL_SET(vop, data01_swap, 316 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_LINK) || 317 crtc_state->dual_channel_swap); 318 break; 319 case DRM_MODE_CONNECTOR_DisplayPort: 320 VOP_CTRL_SET(vop, dp_dclk_pol, 0); 321 VOP_CTRL_SET(vop, dp_pin_pol, val); 322 VOP_CTRL_SET(vop, dp_en, 1); 323 break; 324 case DRM_MODE_CONNECTOR_TV: 325 if (vdisplay == CVBS_PAL_VDISPLAY) 326 VOP_CTRL_SET(vop, tve_sw_mode, 1); 327 else 328 VOP_CTRL_SET(vop, tve_sw_mode, 0); 329 VOP_CTRL_SET(vop, tve_dclk_pol, 1); 330 VOP_CTRL_SET(vop, tve_dclk_en, 1); 331 /* use the same pol reg with hdmi */ 332 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 333 VOP_CTRL_SET(vop, sw_genlock, 1); 334 VOP_CTRL_SET(vop, sw_uv_offset_en, 1); 335 VOP_CTRL_SET(vop, dither_up, 1); 336 break; 337 default: 338 printf("unsupport connector_type[%d]\n", conn_state->type); 339 } 340 341 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 342 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 343 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 344 345 switch (conn_state->bus_format) { 346 case MEDIA_BUS_FMT_RGB565_1X16: 347 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565); 348 break; 349 case MEDIA_BUS_FMT_RGB666_1X18: 350 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 351 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 352 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: 353 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666); 354 break; 355 case MEDIA_BUS_FMT_YUV8_1X24: 356 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 357 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1); 358 break; 359 case MEDIA_BUS_FMT_YUV10_1X30: 360 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 361 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 362 break; 363 case MEDIA_BUS_FMT_RGB888_1X24: 364 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 365 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 366 default: 367 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 368 break; 369 } 370 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 371 val |= PRE_DITHER_DOWN_EN(0); 372 else 373 val |= PRE_DITHER_DOWN_EN(1); 374 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO); 375 VOP_CTRL_SET(vop, dither_down, val); 376 377 VOP_CTRL_SET(vop, dclk_ddr, 378 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 379 VOP_CTRL_SET(vop, hdmi_dclk_out_en, 380 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 381 382 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 383 VOP_CTRL_SET(vop, dsp_data_swap, DSP_RB_SWAP); 384 else 385 VOP_CTRL_SET(vop, dsp_data_swap, 0); 386 387 VOP_CTRL_SET(vop, out_mode, conn_state->output_mode); 388 389 if (VOP_CTRL_SUPPORT(vop, overlay_mode)) { 390 yuv_overlay = is_yuv_output(conn_state->bus_format); 391 VOP_CTRL_SET(vop, overlay_mode, yuv_overlay); 392 } 393 /* 394 * todo: r2y for win csc 395 */ 396 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(conn_state->bus_format)); 397 398 if (yuv_overlay) { 399 if (!is_yuv_output(conn_state->bus_format)) 400 post_y2r_en = true; 401 } else { 402 if (is_yuv_output(conn_state->bus_format)) 403 post_r2y_en = true; 404 } 405 406 crtc_state->yuv_overlay = yuv_overlay; 407 post_csc_mode = to_vop_csc_mode(conn_state->color_space); 408 VOP_CTRL_SET(vop, bcsh_r2y_en, post_r2y_en); 409 VOP_CTRL_SET(vop, bcsh_y2r_en, post_y2r_en); 410 VOP_CTRL_SET(vop, bcsh_r2y_csc_mode, post_csc_mode); 411 VOP_CTRL_SET(vop, bcsh_y2r_csc_mode, post_csc_mode); 412 413 /* 414 * Background color is 10bit depth if vop version >= 3.5 415 */ 416 if (!is_yuv_output(conn_state->bus_format)) 417 val = 0; 418 else if (VOP_MAJOR(vop->version) == 3 && 419 VOP_MINOR(vop->version) >= 5) 420 val = 0x20010200; 421 else 422 val = 0x801080; 423 VOP_CTRL_SET(vop, dsp_background, val); 424 425 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 426 val = hact_st << 16; 427 val |= hact_end; 428 VOP_CTRL_SET(vop, hact_st_end, val); 429 val = vact_st << 16; 430 val |= vact_end; 431 VOP_CTRL_SET(vop, vact_st_end, val); 432 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 433 u16 vact_st_f1 = vtotal + vact_st + 1; 434 u16 vact_end_f1 = vact_st_f1 + vdisplay; 435 436 val = vact_st_f1 << 16 | vact_end_f1; 437 VOP_CTRL_SET(vop, vact_st_end_f1, val); 438 439 val = vtotal << 16 | (vtotal + vsync_len); 440 VOP_CTRL_SET(vop, vs_st_end_f1, val); 441 VOP_CTRL_SET(vop, dsp_interlace, 1); 442 VOP_CTRL_SET(vop, p2i_en, 1); 443 vtotal += vtotal + 1; 444 act_end = vact_end_f1; 445 } else { 446 VOP_CTRL_SET(vop, dsp_interlace, 0); 447 VOP_CTRL_SET(vop, p2i_en, 0); 448 act_end = vact_end; 449 } 450 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 451 vop_post_config(state, vop); 452 VOP_CTRL_SET(vop, core_dclk_div, 453 !!(mode->flags & DRM_MODE_FLAG_DBLCLK)); 454 455 VOP_LINE_FLAG_SET(vop, line_flag_num[0], act_end - 3); 456 VOP_LINE_FLAG_SET(vop, line_flag_num[1], 457 act_end - us_to_vertical_line(mode, 1000)); 458 if (state->crtc_state.mcu_timing.mcu_pix_total > 0) 459 vop_mcu_mode(state, vop); 460 vop_cfg_done(vop); 461 462 return 0; 463 } 464 465 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 466 uint32_t dst, bool is_horizontal, 467 int vsu_mode, int *vskiplines) 468 { 469 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 470 471 if (is_horizontal) { 472 if (mode == SCALE_UP) 473 val = GET_SCL_FT_BIC(src, dst); 474 else if (mode == SCALE_DOWN) 475 val = GET_SCL_FT_BILI_DN(src, dst); 476 } else { 477 if (mode == SCALE_UP) { 478 if (vsu_mode == SCALE_UP_BIL) 479 val = GET_SCL_FT_BILI_UP(src, dst); 480 else 481 val = GET_SCL_FT_BIC(src, dst); 482 } else if (mode == SCALE_DOWN) { 483 if (vskiplines) { 484 *vskiplines = scl_get_vskiplines(src, dst); 485 val = scl_get_bili_dn_vskip(src, dst, 486 *vskiplines); 487 } else { 488 val = GET_SCL_FT_BILI_DN(src, dst); 489 } 490 } 491 } 492 493 return val; 494 } 495 496 static void scl_vop_cal_scl_fac(struct vop *vop, 497 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 498 uint32_t dst_h, uint32_t pixel_format) 499 { 500 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 501 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 502 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 503 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 504 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 505 bool is_yuv = false; 506 uint16_t cbcr_src_w = src_w / hsub; 507 uint16_t cbcr_src_h = src_h / vsub; 508 uint16_t vsu_mode; 509 uint16_t lb_mode; 510 uint32_t val; 511 int vskiplines = 0; 512 513 if (!vop->win->scl) 514 return; 515 516 if (!vop->win->scl->ext) { 517 VOP_SCL_SET(vop, scale_yrgb_x, 518 scl_cal_scale2(src_w, dst_w)); 519 VOP_SCL_SET(vop, scale_yrgb_y, 520 scl_cal_scale2(src_h, dst_h)); 521 if (is_yuv) { 522 VOP_SCL_SET(vop, scale_cbcr_x, 523 scl_cal_scale2(src_w, dst_w)); 524 VOP_SCL_SET(vop, scale_cbcr_y, 525 scl_cal_scale2(src_h, dst_h)); 526 } 527 return; 528 } 529 530 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 531 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 532 533 if (is_yuv) { 534 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 535 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 536 if (cbcr_hor_scl_mode == SCALE_DOWN) 537 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 538 else 539 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 540 } else { 541 if (yrgb_hor_scl_mode == SCALE_DOWN) 542 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 543 else 544 lb_mode = scl_vop_cal_lb_mode(src_w, false); 545 } 546 547 VOP_SCL_SET_EXT(vop, lb_mode, lb_mode); 548 if (lb_mode == LB_RGB_3840X2) { 549 if (yrgb_ver_scl_mode != SCALE_NONE) { 550 printf("ERROR : not allow yrgb ver scale\n"); 551 return; 552 } 553 if (cbcr_ver_scl_mode != SCALE_NONE) { 554 printf("ERROR : not allow cbcr ver scale\n"); 555 return; 556 } 557 vsu_mode = SCALE_UP_BIL; 558 } else if (lb_mode == LB_RGB_2560X4) { 559 vsu_mode = SCALE_UP_BIL; 560 } else { 561 vsu_mode = SCALE_UP_BIC; 562 } 563 564 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 565 true, 0, NULL); 566 VOP_SCL_SET(vop, scale_yrgb_x, val); 567 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 568 false, vsu_mode, &vskiplines); 569 VOP_SCL_SET(vop, scale_yrgb_y, val); 570 571 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt4, vskiplines == 4); 572 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt2, vskiplines == 2); 573 574 VOP_SCL_SET_EXT(vop, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 575 VOP_SCL_SET_EXT(vop, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 576 VOP_SCL_SET_EXT(vop, yrgb_hsd_mode, SCALE_DOWN_BIL); 577 VOP_SCL_SET_EXT(vop, yrgb_vsd_mode, SCALE_DOWN_BIL); 578 VOP_SCL_SET_EXT(vop, yrgb_vsu_mode, vsu_mode); 579 if (is_yuv) { 580 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 581 dst_w, true, 0, NULL); 582 VOP_SCL_SET(vop, scale_cbcr_x, val); 583 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 584 dst_h, false, vsu_mode, &vskiplines); 585 VOP_SCL_SET(vop, scale_cbcr_y, val); 586 587 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt4, vskiplines == 4); 588 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt2, vskiplines == 2); 589 VOP_SCL_SET_EXT(vop, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 590 VOP_SCL_SET_EXT(vop, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 591 VOP_SCL_SET_EXT(vop, cbcr_hsd_mode, SCALE_DOWN_BIL); 592 VOP_SCL_SET_EXT(vop, cbcr_vsd_mode, SCALE_DOWN_BIL); 593 VOP_SCL_SET_EXT(vop, cbcr_vsu_mode, vsu_mode); 594 } 595 } 596 597 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table) 598 { 599 int i; 600 601 /* 602 * so far the csc offset is not 0 and in the feature the csc offset 603 * impossible be 0, so when the offset is 0, should return here. 604 */ 605 if (!table || offset == 0) 606 return; 607 608 for (i = 0; i < 8; i++) 609 vop_writel(vop, offset + i * 4, table[i]); 610 } 611 612 static int rockchip_vop_setup_csc_table(struct display_state *state) 613 { 614 struct crtc_state *crtc_state = &state->crtc_state; 615 struct connector_state *conn_state = &state->conn_state; 616 struct vop *vop = crtc_state->private; 617 const uint32_t *csc_table = NULL; 618 619 if (!vop->csc_table || !crtc_state->yuv_overlay) 620 return 0; 621 /* todo: only implement r2y*/ 622 switch (conn_state->color_space) { 623 case V4L2_COLORSPACE_SMPTE170M: 624 csc_table = vop->csc_table->r2y_bt601_12_235; 625 break; 626 case V4L2_COLORSPACE_REC709: 627 case V4L2_COLORSPACE_DEFAULT: 628 case V4L2_COLORSPACE_JPEG: 629 csc_table = vop->csc_table->r2y_bt709; 630 break; 631 case V4L2_COLORSPACE_BT2020: 632 csc_table = vop->csc_table->r2y_bt2020; 633 break; 634 default: 635 csc_table = vop->csc_table->r2y_bt601; 636 break; 637 } 638 639 vop_load_csc_table(vop, vop->win_csc->r2y_offset, csc_table); 640 VOP_WIN_CSC_SET(vop, r2y_en, 1); 641 642 return 0; 643 } 644 645 static int rockchip_vop_set_plane(struct display_state *state) 646 { 647 struct crtc_state *crtc_state = &state->crtc_state; 648 const struct rockchip_crtc *crtc = crtc_state->crtc; 649 const struct vop_data *vop_data = crtc->data; 650 struct connector_state *conn_state = &state->conn_state; 651 struct drm_display_mode *mode = &conn_state->mode; 652 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 653 struct vop *vop = crtc_state->private; 654 int src_w = crtc_state->src_w; 655 int src_h = crtc_state->src_h; 656 int crtc_x = crtc_state->crtc_x; 657 int crtc_y = crtc_state->crtc_y; 658 int crtc_w = crtc_state->crtc_w; 659 int crtc_h = crtc_state->crtc_h; 660 int xvir = crtc_state->xvir; 661 int x_mirror = 0, y_mirror = 0; 662 663 if ((crtc_w > crtc_state->max_output.width) || 664 (crtc_h > crtc_state->max_output.height)){ 665 printf("Maximum destination %dx%d exceeded\n", 666 crtc_state->max_output.width, 667 crtc_state->max_output.height); 668 return -EINVAL; 669 } 670 671 act_info = (src_h - 1) << 16; 672 act_info |= (src_w - 1) & 0xffff; 673 674 dsp_info = (crtc_h - 1) << 16; 675 dsp_info |= (crtc_w - 1) & 0xffff; 676 677 dsp_stx = crtc_x + mode->crtc_htotal - mode->crtc_hsync_start; 678 dsp_sty = crtc_y + mode->crtc_vtotal - mode->crtc_vsync_start; 679 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 680 /* 681 * vop full need to treats rgb888 as bgr888 so we reverse the rb swap to workaround 682 */ 683 if (crtc_state->format == ROCKCHIP_FMT_RGB888 && VOP_MAJOR(vop_data->version) == 3) 684 crtc_state->rb_swap = !crtc_state->rb_swap; 685 686 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 687 y_mirror = 1; 688 else 689 y_mirror = 0; 690 if (mode->flags & DRM_MODE_FLAG_XMIRROR) 691 x_mirror = 1; 692 else 693 x_mirror = 0; 694 if (crtc_state->ymirror ^ y_mirror) 695 y_mirror = 1; 696 else 697 y_mirror = 0; 698 if (y_mirror) { 699 if (VOP_CTRL_SUPPORT(vop, ymirror)) 700 crtc_state->dma_addr += (src_h - 1) * xvir * 4; 701 else 702 y_mirror = 0; 703 } 704 VOP_CTRL_SET(vop, ymirror, y_mirror); 705 VOP_CTRL_SET(vop, xmirror, x_mirror); 706 707 VOP_WIN_SET(vop, format, crtc_state->format); 708 VOP_WIN_SET(vop, yrgb_vir, xvir); 709 VOP_WIN_SET(vop, yrgb_mst, crtc_state->dma_addr); 710 711 scl_vop_cal_scl_fac(vop, src_w, src_h, crtc_w, crtc_h, 712 crtc_state->format); 713 714 VOP_WIN_SET(vop, act_info, act_info); 715 VOP_WIN_SET(vop, dsp_info, dsp_info); 716 VOP_WIN_SET(vop, dsp_st, dsp_st); 717 VOP_WIN_SET(vop, rb_swap, crtc_state->rb_swap); 718 719 VOP_WIN_SET(vop, src_alpha_ctl, 0); 720 721 rockchip_vop_setup_csc_table(state); 722 VOP_WIN_SET(vop, enable, 1); 723 VOP_WIN_SET(vop, gate, 1); 724 vop_cfg_done(vop); 725 726 return 0; 727 } 728 729 static int rockchip_vop_prepare(struct display_state *state) 730 { 731 return 0; 732 } 733 734 static int rockchip_vop_enable(struct display_state *state) 735 { 736 struct crtc_state *crtc_state = &state->crtc_state; 737 struct vop *vop = crtc_state->private; 738 739 VOP_CTRL_SET(vop, standby, 0); 740 vop_cfg_done(vop); 741 if (crtc_state->mcu_timing.mcu_pix_total > 0) 742 VOP_CTRL_SET(vop, mcu_hold_mode, 0); 743 744 return 0; 745 } 746 747 static int rockchip_vop_disable(struct display_state *state) 748 { 749 struct crtc_state *crtc_state = &state->crtc_state; 750 struct vop *vop = crtc_state->private; 751 752 VOP_CTRL_SET(vop, standby, 1); 753 vop_cfg_done(vop); 754 return 0; 755 } 756 757 static int rockchip_vop_fixup_dts(struct display_state *state, void *blob) 758 { 759 #if 0 760 struct crtc_state *crtc_state = &state->crtc_state; 761 struct panel_state *pstate = &state->panel_state; 762 uint32_t phandle; 763 char path[100]; 764 int ret, dsp_lut_node; 765 766 if (!ofnode_valid(pstate->dsp_lut_node)) 767 return 0; 768 ret = fdt_get_path(state->blob, pstate->dsp_lut_node, path, sizeof(path)); 769 if (ret < 0) { 770 printf("failed to get dsp_lut path[%s], ret=%d\n", 771 path, ret); 772 return ret; 773 } 774 775 dsp_lut_node = fdt_path_offset(blob, path); 776 phandle = fdt_get_phandle(blob, dsp_lut_node); 777 if (!phandle) { 778 phandle = fdt_alloc_phandle(blob); 779 if (!phandle) { 780 printf("failed to alloc phandle\n"); 781 return -ENOMEM; 782 } 783 784 fdt_set_phandle(blob, dsp_lut_node, phandle); 785 } 786 787 ret = fdt_get_path(state->blob, crtc_state->node, path, sizeof(path)); 788 if (ret < 0) { 789 printf("failed to get route path[%s], ret=%d\n", 790 path, ret); 791 return ret; 792 } 793 794 do_fixup_by_path_u32(blob, path, "dsp-lut", phandle, 1); 795 #endif 796 return 0; 797 } 798 799 static int rockchip_vop_send_mcu_cmd(struct display_state *state, 800 u32 type, u32 value) 801 { 802 struct crtc_state *crtc_state = &state->crtc_state; 803 struct vop *vop = crtc_state->private; 804 805 if (vop) { 806 switch (type) { 807 case MCU_WRCMD: 808 VOP_CTRL_SET(vop, mcu_rs, 0); 809 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value); 810 VOP_CTRL_SET(vop, mcu_rs, 1); 811 break; 812 case MCU_WRDATA: 813 VOP_CTRL_SET(vop, mcu_rs, 1); 814 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value); 815 break; 816 case MCU_SETBYPASS: 817 VOP_CTRL_SET(vop, mcu_bypass, value ? 1 : 0); 818 break; 819 default: 820 break; 821 } 822 } 823 824 return 0; 825 } 826 827 const struct rockchip_crtc_funcs rockchip_vop_funcs = { 828 .preinit = rockchip_vop_preinit, 829 .init = rockchip_vop_init, 830 .set_plane = rockchip_vop_set_plane, 831 .prepare = rockchip_vop_prepare, 832 .enable = rockchip_vop_enable, 833 .disable = rockchip_vop_disable, 834 .fixup_dts = rockchip_vop_fixup_dts, 835 .send_mcu_cmd = rockchip_vop_send_mcu_cmd, 836 }; 837