1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <asm/io.h> 15 #include <linux/list.h> 16 #include <linux/media-bus-format.h> 17 #include <clk.h> 18 #include <asm/arch/clock.h> 19 #include <linux/err.h> 20 21 #include "rockchip_display.h" 22 #include "rockchip_crtc.h" 23 #include "rockchip_connector.h" 24 #include "rockchip_vop.h" 25 26 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 27 { 28 return us * mode->clock / mode->htotal / 1000; 29 } 30 31 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) 32 { 33 struct crtc_state *crtc_state = &state->crtc_state; 34 struct connector_state *conn_state = &state->conn_state; 35 u32 *lut = conn_state->gamma.lut; 36 int node = crtc_state->node; 37 fdt_size_t lut_size; 38 int i, lut_len; 39 u32 *lut_regs; 40 41 if (!conn_state->gamma.lut) 42 return 0; 43 44 i = fdt_stringlist_search(state->blob, node, "reg-names", "gamma_lut"); 45 if (i < 0) { 46 printf("Warning: vop not support gamma\n"); 47 return 0; 48 } 49 lut_regs = (u32 *)fdtdec_get_addr_size_auto_noparent(state->blob, 50 node, "reg", i, 51 &lut_size, false); 52 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 53 printf("failed to get gamma lut register\n"); 54 return 0; 55 } 56 lut_len = lut_size / 4; 57 if (lut_len != 256 && lut_len != 1024) { 58 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 59 return 0; 60 } 61 62 if (conn_state->gamma.size != lut_len) { 63 int size = conn_state->gamma.size; 64 u32 j, r, g, b, color; 65 66 for (i = 0; i < lut_len; i++) { 67 j = i * size / lut_len; 68 r = lut[j] / size / size * lut_len / size; 69 g = lut[j] / size % size * lut_len / size; 70 b = lut[j] % size * lut_len / size; 71 color = r * lut_len * lut_len + g * lut_len + b; 72 73 writel(color, lut_regs + (i << 2)); 74 } 75 } else { 76 for (i = 0; i < lut_len; i++) 77 writel(lut[i], lut_regs + (i << 2)); 78 } 79 80 VOP_CTRL_SET(vop, dsp_lut_en, 1); 81 VOP_CTRL_SET(vop, update_gamma_lut, 1); 82 83 return 0; 84 } 85 86 static int rockchip_vop_init(struct display_state *state) 87 { 88 struct crtc_state *crtc_state = &state->crtc_state; 89 struct connector_state *conn_state = &state->conn_state; 90 struct drm_display_mode *mode = &conn_state->mode; 91 const struct rockchip_crtc *crtc = crtc_state->crtc; 92 const struct vop_data *vop_data = crtc->data; 93 struct vop *vop; 94 u16 hsync_len = mode->hsync_end - mode->hsync_start; 95 u16 hdisplay = mode->hdisplay; 96 u16 htotal = mode->htotal; 97 u16 hact_st = mode->htotal - mode->hsync_start; 98 u16 hact_end = hact_st + hdisplay; 99 u16 vdisplay = mode->vdisplay; 100 u16 vtotal = mode->vtotal; 101 u16 vsync_len = mode->vsync_end - mode->vsync_start; 102 u16 vact_st = mode->vtotal - mode->vsync_start; 103 u16 vact_end = vact_st + vdisplay; 104 struct clk dclk, aclk; 105 u32 val; 106 int ret; 107 108 vop = malloc(sizeof(*vop)); 109 if (!vop) 110 return -ENOMEM; 111 memset(vop, 0, sizeof(*vop)); 112 113 crtc_state->private = vop; 114 vop->regs = (void *)fdtdec_get_addr_size_auto_noparent(state->blob, 115 crtc_state->node, "reg", 0, NULL, false); 116 vop->regsbak = malloc(vop_data->reg_len); 117 vop->win = vop_data->win; 118 vop->win_offset = vop_data->win_offset; 119 vop->ctrl = vop_data->ctrl; 120 vop->line_flag = vop_data->line_flag; 121 vop->version = vop_data->version; 122 123 /* 124 * TODO: 125 * Set Dclk pll parent 126 */ 127 128 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &dclk); 129 if (!ret) 130 ret = clk_set_rate(&dclk, mode->clock * 1000); 131 if (IS_ERR_VALUE(ret)) { 132 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret); 133 return ret; 134 } 135 136 ret = clk_get_by_name(crtc_state->dev, "aclk_vop", &aclk); 137 if (!ret) 138 ret = clk_set_rate(&aclk, 400 * 1000 * 1000); 139 if (IS_ERR_VALUE(ret)) 140 printf("%s: Failed to set aclk: ret=%d\n", __func__, ret); 141 142 memcpy(vop->regsbak, vop->regs, vop_data->reg_len); 143 144 rockchip_vop_init_gamma(vop, state); 145 146 VOP_CTRL_SET(vop, global_regdone_en, 1); 147 VOP_CTRL_SET(vop, win_gate[0], 1); 148 VOP_CTRL_SET(vop, win_gate[1], 1); 149 VOP_CTRL_SET(vop, dsp_blank, 0); 150 151 val = 0x8; 152 val |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 153 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 154 VOP_CTRL_SET(vop, pin_pol, val); 155 156 switch (conn_state->type) { 157 case DRM_MODE_CONNECTOR_LVDS: 158 VOP_CTRL_SET(vop, rgb_en, 1); 159 VOP_CTRL_SET(vop, rgb_pin_pol, val); 160 break; 161 case DRM_MODE_CONNECTOR_eDP: 162 VOP_CTRL_SET(vop, edp_en, 1); 163 VOP_CTRL_SET(vop, edp_pin_pol, val); 164 break; 165 case DRM_MODE_CONNECTOR_HDMIA: 166 VOP_CTRL_SET(vop, hdmi_en, 1); 167 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 168 break; 169 case DRM_MODE_CONNECTOR_DSI: 170 VOP_CTRL_SET(vop, mipi_en, 1); 171 VOP_CTRL_SET(vop, mipi_pin_pol, val); 172 VOP_CTRL_SET(vop, mipi_dual_channel_en, 173 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL)); 174 VOP_CTRL_SET(vop, data01_swap, 175 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_LINK)); 176 break; 177 default: 178 printf("unsupport connector_type[%d]\n", conn_state->type); 179 } 180 181 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 182 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 183 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 184 185 switch (conn_state->bus_format) { 186 case MEDIA_BUS_FMT_RGB565_1X16: 187 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565); 188 break; 189 case MEDIA_BUS_FMT_RGB666_1X18: 190 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 191 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666); 192 break; 193 case MEDIA_BUS_FMT_RGB888_1X24: 194 default: 195 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 196 break; 197 } 198 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 199 val |= PRE_DITHER_DOWN_EN(0); 200 else 201 val |= PRE_DITHER_DOWN_EN(1); 202 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO); 203 VOP_CTRL_SET(vop, dither_down, val); 204 205 VOP_CTRL_SET(vop, out_mode, conn_state->output_mode); 206 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 207 val = hact_st << 16; 208 val |= hact_end; 209 VOP_CTRL_SET(vop, hact_st_end, val); 210 VOP_CTRL_SET(vop, hpost_st_end, val); 211 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 212 val = vact_st << 16; 213 val |= vact_end; 214 VOP_CTRL_SET(vop, vact_st_end, val); 215 VOP_CTRL_SET(vop, vpost_st_end, val); 216 VOP_CTRL_SET(vop, standby, 1); 217 VOP_LINE_FLAG_SET(vop, line_flag_num[0], vact_end - 3); 218 VOP_LINE_FLAG_SET(vop, line_flag_num[1], 219 vact_end - us_to_vertical_line(mode, 1000)); 220 vop_cfg_done(vop); 221 222 return 0; 223 } 224 225 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 226 uint32_t dst, bool is_horizontal, 227 int vsu_mode, int *vskiplines) 228 { 229 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 230 231 if (is_horizontal) { 232 if (mode == SCALE_UP) 233 val = GET_SCL_FT_BIC(src, dst); 234 else if (mode == SCALE_DOWN) 235 val = GET_SCL_FT_BILI_DN(src, dst); 236 } else { 237 if (mode == SCALE_UP) { 238 if (vsu_mode == SCALE_UP_BIL) 239 val = GET_SCL_FT_BILI_UP(src, dst); 240 else 241 val = GET_SCL_FT_BIC(src, dst); 242 } else if (mode == SCALE_DOWN) { 243 if (vskiplines) { 244 *vskiplines = scl_get_vskiplines(src, dst); 245 val = scl_get_bili_dn_vskip(src, dst, 246 *vskiplines); 247 } else { 248 val = GET_SCL_FT_BILI_DN(src, dst); 249 } 250 } 251 } 252 253 return val; 254 } 255 256 static void scl_vop_cal_scl_fac(struct vop *vop, 257 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 258 uint32_t dst_h, uint32_t pixel_format) 259 { 260 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 261 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 262 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 263 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 264 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 265 bool is_yuv = false; 266 uint16_t cbcr_src_w = src_w / hsub; 267 uint16_t cbcr_src_h = src_h / vsub; 268 uint16_t vsu_mode; 269 uint16_t lb_mode; 270 uint32_t val; 271 int vskiplines = 0; 272 273 if (!vop->win->scl) 274 return; 275 276 if (dst_w > 3840) { 277 printf("Maximum destination width (3840) exceeded\n"); 278 return; 279 } 280 281 if (!vop->win->scl->ext) { 282 VOP_SCL_SET(vop, scale_yrgb_x, 283 scl_cal_scale2(src_w, dst_w)); 284 VOP_SCL_SET(vop, scale_yrgb_y, 285 scl_cal_scale2(src_h, dst_h)); 286 if (is_yuv) { 287 VOP_SCL_SET(vop, scale_cbcr_x, 288 scl_cal_scale2(src_w, dst_w)); 289 VOP_SCL_SET(vop, scale_cbcr_y, 290 scl_cal_scale2(src_h, dst_h)); 291 } 292 return; 293 } 294 295 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 296 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 297 298 if (is_yuv) { 299 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 300 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 301 if (cbcr_hor_scl_mode == SCALE_DOWN) 302 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 303 else 304 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 305 } else { 306 if (yrgb_hor_scl_mode == SCALE_DOWN) 307 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 308 else 309 lb_mode = scl_vop_cal_lb_mode(src_w, false); 310 } 311 312 VOP_SCL_SET_EXT(vop, lb_mode, lb_mode); 313 if (lb_mode == LB_RGB_3840X2) { 314 if (yrgb_ver_scl_mode != SCALE_NONE) { 315 printf("ERROR : not allow yrgb ver scale\n"); 316 return; 317 } 318 if (cbcr_ver_scl_mode != SCALE_NONE) { 319 printf("ERROR : not allow cbcr ver scale\n"); 320 return; 321 } 322 vsu_mode = SCALE_UP_BIL; 323 } else if (lb_mode == LB_RGB_2560X4) { 324 vsu_mode = SCALE_UP_BIL; 325 } else { 326 vsu_mode = SCALE_UP_BIC; 327 } 328 329 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 330 true, 0, NULL); 331 VOP_SCL_SET(vop, scale_yrgb_x, val); 332 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 333 false, vsu_mode, &vskiplines); 334 VOP_SCL_SET(vop, scale_yrgb_y, val); 335 336 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt4, vskiplines == 4); 337 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt2, vskiplines == 2); 338 339 VOP_SCL_SET_EXT(vop, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 340 VOP_SCL_SET_EXT(vop, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 341 VOP_SCL_SET_EXT(vop, yrgb_hsd_mode, SCALE_DOWN_BIL); 342 VOP_SCL_SET_EXT(vop, yrgb_vsd_mode, SCALE_DOWN_BIL); 343 VOP_SCL_SET_EXT(vop, yrgb_vsu_mode, vsu_mode); 344 if (is_yuv) { 345 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 346 dst_w, true, 0, NULL); 347 VOP_SCL_SET(vop, scale_cbcr_x, val); 348 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 349 dst_h, false, vsu_mode, &vskiplines); 350 VOP_SCL_SET(vop, scale_cbcr_y, val); 351 352 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt4, vskiplines == 4); 353 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt2, vskiplines == 2); 354 VOP_SCL_SET_EXT(vop, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 355 VOP_SCL_SET_EXT(vop, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 356 VOP_SCL_SET_EXT(vop, cbcr_hsd_mode, SCALE_DOWN_BIL); 357 VOP_SCL_SET_EXT(vop, cbcr_vsd_mode, SCALE_DOWN_BIL); 358 VOP_SCL_SET_EXT(vop, cbcr_vsu_mode, vsu_mode); 359 } 360 } 361 362 static int rockchip_vop_set_plane(struct display_state *state) 363 { 364 struct crtc_state *crtc_state = &state->crtc_state; 365 struct connector_state *conn_state = &state->conn_state; 366 struct drm_display_mode *mode = &conn_state->mode; 367 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 368 struct vop *vop = crtc_state->private; 369 int src_w = crtc_state->src_w; 370 int src_h = crtc_state->src_h; 371 int crtc_x = crtc_state->crtc_x; 372 int crtc_y = crtc_state->crtc_y; 373 int crtc_w = crtc_state->crtc_w; 374 int crtc_h = crtc_state->crtc_h; 375 int xvir = crtc_state->xvir; 376 377 act_info = (src_h - 1) << 16; 378 act_info |= (src_w - 1) & 0xffff; 379 380 dsp_info = (crtc_h - 1) << 16; 381 dsp_info |= (crtc_w - 1) & 0xffff; 382 383 dsp_stx = crtc_x + mode->htotal - mode->hsync_start; 384 dsp_sty = crtc_y + mode->vtotal - mode->vsync_start; 385 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 386 387 if (crtc_state->ymirror) 388 crtc_state->dma_addr += (src_h - 1) * xvir * 4; 389 VOP_WIN_SET(vop, ymirror, crtc_state->ymirror); 390 VOP_WIN_SET(vop, format, crtc_state->format); 391 VOP_WIN_SET(vop, yrgb_vir, xvir); 392 VOP_WIN_SET(vop, yrgb_mst, crtc_state->dma_addr); 393 394 scl_vop_cal_scl_fac(vop, src_w, src_h, crtc_w, crtc_h, 395 crtc_state->format); 396 397 VOP_WIN_SET(vop, act_info, act_info); 398 VOP_WIN_SET(vop, dsp_info, dsp_info); 399 VOP_WIN_SET(vop, dsp_st, dsp_st); 400 VOP_WIN_SET(vop, rb_swap, crtc_state->rb_swap); 401 402 VOP_WIN_SET(vop, src_alpha_ctl, 0); 403 404 VOP_WIN_SET(vop, enable, 1); 405 vop_cfg_done(vop); 406 407 return 0; 408 } 409 410 static int rockchip_vop_prepare(struct display_state *state) 411 { 412 return 0; 413 } 414 415 static int rockchip_vop_enable(struct display_state *state) 416 { 417 struct crtc_state *crtc_state = &state->crtc_state; 418 struct vop *vop = crtc_state->private; 419 420 VOP_CTRL_SET(vop, standby, 0); 421 vop_cfg_done(vop); 422 423 return 0; 424 } 425 426 static int rockchip_vop_disable(struct display_state *state) 427 { 428 struct crtc_state *crtc_state = &state->crtc_state; 429 struct vop *vop = crtc_state->private; 430 431 VOP_CTRL_SET(vop, standby, 1); 432 vop_cfg_done(vop); 433 return 0; 434 } 435 436 static int rockchip_vop_fixup_dts(struct display_state *state, void *blob) 437 { 438 struct crtc_state *crtc_state = &state->crtc_state; 439 struct panel_state *pstate = &state->panel_state; 440 uint32_t phandle; 441 char path[100]; 442 int ret, dsp_lut_node; 443 444 if (!pstate->dsp_lut_node) 445 return 0; 446 447 ret = fdt_get_path(state->blob, pstate->dsp_lut_node, path, sizeof(path)); 448 if (ret < 0) { 449 printf("failed to get dsp_lut path[%s], ret=%d\n", 450 path, ret); 451 return ret; 452 } 453 454 dsp_lut_node = fdt_path_offset(blob, path); 455 phandle = fdt_get_phandle(blob, dsp_lut_node); 456 if (!phandle) { 457 phandle = fdt_alloc_phandle(blob); 458 if (!phandle) { 459 printf("failed to alloc phandle\n"); 460 return -ENOMEM; 461 } 462 463 fdt_set_phandle(blob, dsp_lut_node, phandle); 464 } 465 466 ret = fdt_get_path(state->blob, crtc_state->node, path, sizeof(path)); 467 if (ret < 0) { 468 printf("failed to get route path[%s], ret=%d\n", 469 path, ret); 470 return ret; 471 } 472 473 do_fixup_by_path_u32(blob, path, "dsp-lut", phandle, 1); 474 475 return 0; 476 } 477 478 const struct rockchip_crtc_funcs rockchip_vop_funcs = { 479 .init = rockchip_vop_init, 480 .set_plane = rockchip_vop_set_plane, 481 .prepare = rockchip_vop_prepare, 482 .enable = rockchip_vop_enable, 483 .disable = rockchip_vop_disable, 484 .fixup_dts = rockchip_vop_fixup_dts, 485 }; 486