1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <asm/io.h> 15 #include <linux/list.h> 16 #include <linux/media-bus-format.h> 17 #include <clk.h> 18 #include <asm/arch/clock.h> 19 #include <linux/err.h> 20 21 #include "rockchip_display.h" 22 #include "rockchip_crtc.h" 23 #include "rockchip_connector.h" 24 #include "rockchip_vop.h" 25 26 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 27 { 28 return us * mode->clock / mode->htotal / 1000; 29 } 30 #if 0 31 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) 32 { 33 struct crtc_state *crtc_state = &state->crtc_state; 34 struct connector_state *conn_state = &state->conn_state; 35 u32 *lut = conn_state->gamma.lut; 36 int node = crtc_state->node; 37 fdt_size_t lut_size; 38 int i, lut_len; 39 u32 *lut_regs; 40 41 if (!conn_state->gamma.lut) 42 return 0; 43 44 i = fdt_find_string(state->blob, node, "reg-names", "gamma_lut"); 45 if (i < 0) { 46 printf("Warning: vop not support gamma\n"); 47 return 0; 48 } 49 lut_regs = (u32 *)fdtdec_get_addr_size_auto_noparent(state->blob, 50 node, "reg", 51 i, &lut_size); 52 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 53 printf("failed to get gamma lut register\n"); 54 return 0; 55 } 56 lut_len = lut_size / 4; 57 if (lut_len != 256 && lut_len != 1024) { 58 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 59 return 0; 60 } 61 62 if (conn_state->gamma.size != lut_len) { 63 int size = conn_state->gamma.size; 64 u32 j, r, g, b, color; 65 66 for (i = 0; i < lut_len; i++) { 67 j = i * size / lut_len; 68 r = lut[j] / size / size * lut_len / size; 69 g = lut[j] / size % size * lut_len / size; 70 b = lut[j] % size * lut_len / size; 71 color = r * lut_len * lut_len + g * lut_len + b; 72 73 writel(color, lut_regs + (i << 2)); 74 } 75 } else { 76 for (i = 0; i < lut_len; i++) 77 writel(lut[i], lut_regs + (i << 2)); 78 } 79 80 VOP_CTRL_SET(vop, dsp_lut_en, 1); 81 VOP_CTRL_SET(vop, update_gamma_lut, 1); 82 83 return 0; 84 } 85 #endif 86 87 static int rockchip_vop_init(struct display_state *state) 88 { 89 struct crtc_state *crtc_state = &state->crtc_state; 90 struct connector_state *conn_state = &state->conn_state; 91 struct drm_display_mode *mode = &conn_state->mode; 92 const struct rockchip_crtc *crtc = crtc_state->crtc; 93 const struct vop_data *vop_data = crtc->data; 94 struct vop *vop; 95 u16 hsync_len = mode->hsync_end - mode->hsync_start; 96 u16 hdisplay = mode->hdisplay; 97 u16 htotal = mode->htotal; 98 u16 hact_st = mode->htotal - mode->hsync_start; 99 u16 hact_end = hact_st + hdisplay; 100 u16 vdisplay = mode->vdisplay; 101 u16 vtotal = mode->vtotal; 102 u16 vsync_len = mode->vsync_end - mode->vsync_start; 103 u16 vact_st = mode->vtotal - mode->vsync_start; 104 u16 vact_end = vact_st + vdisplay; 105 struct clk aclk, hclk, dclk; 106 u32 val; 107 int i, ret; 108 int rate; 109 110 vop = malloc(sizeof(*vop)); 111 if (!vop) 112 return -ENOMEM; 113 memset(vop, 0, sizeof(*vop)); 114 115 crtc_state->private = vop; 116 vop->regs = (void *)fdtdec_get_addr_size_auto_noparent(state->blob, 117 crtc_state->node, "reg", 0, NULL, false); 118 vop->regsbak = malloc(vop_data->reg_len); 119 vop->win = vop_data->win; 120 vop->win_offset = vop_data->win_offset; 121 vop->ctrl = vop_data->ctrl; 122 vop->line_flag = vop_data->line_flag; 123 vop->version = vop_data->version; 124 125 ret = clk_get_by_name(crtc_state->dev, "aclk_vop", &aclk); 126 if (IS_ERR_VALUE(ret)) { 127 printf("%s: Failed to get aclk: ret=%d\n", __func__, ret); 128 return ret; 129 } 130 #if 0 131 ret = clk_set_rate(&aclk, 384 * 1000 * 1000); 132 if (IS_ERR_VALUE(ret)) { 133 printf("%s: Failed to set aclk: ret=%d\n", __func__, ret); 134 return ret; 135 } 136 #endif 137 #if 0 138 139 ret = clk_get_by_name(crtc_state->dev, "hclk_vop", &hclk); 140 if (!ret) 141 ret = clk_set_rate(&hclk, 100 * 1000 * 1000); 142 if (IS_ERR_VALUE(ret)) { 143 printf("%s: Failed to set aclk: ret=%d\n", __func__, ret); 144 return ret; 145 } 146 #endif 147 148 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &dclk); 149 if (!ret) 150 ret = clk_set_rate(&dclk, mode->clock * 1000); 151 if (IS_ERR_VALUE(ret)) { 152 printf("%s: Failed to set aclk: ret=%d\n", __func__, ret); 153 return ret; 154 } 155 156 #if 0 157 #ifdef CONFIG_RKCHIP_RK3399 158 /* Set Dclk pll parent */ 159 if (conn_state->type == DRM_MODE_CONNECTOR_HDMIA) 160 rkclk_lcdc_dclk_pll_sel(crtc_state->crtc_id, 0); 161 else 162 rkclk_lcdc_dclk_pll_sel(crtc_state->crtc_id, 1); 163 #endif 164 165 /* Set aclk hclk and dclk */ 166 rate = rkclk_lcdc_clk_set(crtc_state->crtc_id, mode->clock * 1000); 167 if (rate != mode->clock * 1000) { 168 printf("Warn: vop clk request %dhz, but real clock is %dhz", 169 mode->clock * 1000, rate); 170 } 171 #endif 172 memcpy(vop->regsbak, vop->regs, vop_data->reg_len); 173 174 //rockchip_vop_init_gamma(vop, state); 175 176 VOP_CTRL_SET(vop, global_regdone_en, 1); 177 VOP_CTRL_SET(vop, win_gate[0], 1); 178 VOP_CTRL_SET(vop, win_gate[1], 1); 179 VOP_CTRL_SET(vop, dsp_blank, 0); 180 181 val = 0x8; 182 val |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 183 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 184 VOP_CTRL_SET(vop, pin_pol, val); 185 186 switch (conn_state->type) { 187 case DRM_MODE_CONNECTOR_LVDS: 188 VOP_CTRL_SET(vop, rgb_en, 1); 189 VOP_CTRL_SET(vop, rgb_pin_pol, val); 190 break; 191 case DRM_MODE_CONNECTOR_eDP: 192 VOP_CTRL_SET(vop, edp_en, 1); 193 VOP_CTRL_SET(vop, edp_pin_pol, val); 194 break; 195 case DRM_MODE_CONNECTOR_HDMIA: 196 VOP_CTRL_SET(vop, hdmi_en, 1); 197 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 198 break; 199 case DRM_MODE_CONNECTOR_DSI: 200 VOP_CTRL_SET(vop, mipi_en, 1); 201 VOP_CTRL_SET(vop, mipi_pin_pol, val); 202 VOP_CTRL_SET(vop, mipi_dual_channel_en, 203 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL)); 204 VOP_CTRL_SET(vop, data01_swap, 205 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_LINK)); 206 break; 207 default: 208 printf("unsupport connector_type[%d]\n", conn_state->type); 209 } 210 211 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 212 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 213 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 214 215 switch (conn_state->bus_format) { 216 case MEDIA_BUS_FMT_RGB565_1X16: 217 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565); 218 break; 219 case MEDIA_BUS_FMT_RGB666_1X18: 220 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 221 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666); 222 break; 223 case MEDIA_BUS_FMT_RGB888_1X24: 224 default: 225 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 226 break; 227 } 228 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 229 val |= PRE_DITHER_DOWN_EN(0); 230 else 231 val |= PRE_DITHER_DOWN_EN(1); 232 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO); 233 VOP_CTRL_SET(vop, dither_down, val); 234 235 VOP_CTRL_SET(vop, out_mode, conn_state->output_mode); 236 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 237 val = hact_st << 16; 238 val |= hact_end; 239 VOP_CTRL_SET(vop, hact_st_end, val); 240 VOP_CTRL_SET(vop, hpost_st_end, val); 241 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 242 val = vact_st << 16; 243 val |= vact_end; 244 VOP_CTRL_SET(vop, vact_st_end, val); 245 VOP_CTRL_SET(vop, vpost_st_end, val); 246 VOP_CTRL_SET(vop, standby, 1); 247 VOP_LINE_FLAG_SET(vop, line_flag_num[0], vact_end - 3); 248 VOP_LINE_FLAG_SET(vop, line_flag_num[1], 249 vact_end - us_to_vertical_line(mode, 1000)); 250 vop_cfg_done(vop); 251 252 return 0; 253 } 254 255 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 256 uint32_t dst, bool is_horizontal, 257 int vsu_mode, int *vskiplines) 258 { 259 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 260 261 if (is_horizontal) { 262 if (mode == SCALE_UP) 263 val = GET_SCL_FT_BIC(src, dst); 264 else if (mode == SCALE_DOWN) 265 val = GET_SCL_FT_BILI_DN(src, dst); 266 } else { 267 if (mode == SCALE_UP) { 268 if (vsu_mode == SCALE_UP_BIL) 269 val = GET_SCL_FT_BILI_UP(src, dst); 270 else 271 val = GET_SCL_FT_BIC(src, dst); 272 } else if (mode == SCALE_DOWN) { 273 if (vskiplines) { 274 *vskiplines = scl_get_vskiplines(src, dst); 275 val = scl_get_bili_dn_vskip(src, dst, 276 *vskiplines); 277 } else { 278 val = GET_SCL_FT_BILI_DN(src, dst); 279 } 280 } 281 } 282 283 return val; 284 } 285 286 static void scl_vop_cal_scl_fac(struct vop *vop, 287 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 288 uint32_t dst_h, uint32_t pixel_format) 289 { 290 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 291 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 292 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 293 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 294 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 295 bool is_yuv = false; 296 uint16_t cbcr_src_w = src_w / hsub; 297 uint16_t cbcr_src_h = src_h / vsub; 298 uint16_t vsu_mode; 299 uint16_t lb_mode; 300 uint32_t val; 301 int vskiplines = 0; 302 303 if (!vop->win->scl) 304 return; 305 306 if (dst_w > 3840) { 307 printf("Maximum destination width (3840) exceeded\n"); 308 return; 309 } 310 311 if (!vop->win->scl->ext) { 312 VOP_SCL_SET(vop, scale_yrgb_x, 313 scl_cal_scale2(src_w, dst_w)); 314 VOP_SCL_SET(vop, scale_yrgb_y, 315 scl_cal_scale2(src_h, dst_h)); 316 if (is_yuv) { 317 VOP_SCL_SET(vop, scale_cbcr_x, 318 scl_cal_scale2(src_w, dst_w)); 319 VOP_SCL_SET(vop, scale_cbcr_y, 320 scl_cal_scale2(src_h, dst_h)); 321 } 322 return; 323 } 324 325 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 326 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 327 328 if (is_yuv) { 329 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 330 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 331 if (cbcr_hor_scl_mode == SCALE_DOWN) 332 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 333 else 334 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 335 } else { 336 if (yrgb_hor_scl_mode == SCALE_DOWN) 337 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 338 else 339 lb_mode = scl_vop_cal_lb_mode(src_w, false); 340 } 341 342 VOP_SCL_SET_EXT(vop, lb_mode, lb_mode); 343 if (lb_mode == LB_RGB_3840X2) { 344 if (yrgb_ver_scl_mode != SCALE_NONE) { 345 printf("ERROR : not allow yrgb ver scale\n"); 346 return; 347 } 348 if (cbcr_ver_scl_mode != SCALE_NONE) { 349 printf("ERROR : not allow cbcr ver scale\n"); 350 return; 351 } 352 vsu_mode = SCALE_UP_BIL; 353 } else if (lb_mode == LB_RGB_2560X4) { 354 vsu_mode = SCALE_UP_BIL; 355 } else { 356 vsu_mode = SCALE_UP_BIC; 357 } 358 359 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 360 true, 0, NULL); 361 VOP_SCL_SET(vop, scale_yrgb_x, val); 362 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 363 false, vsu_mode, &vskiplines); 364 VOP_SCL_SET(vop, scale_yrgb_y, val); 365 366 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt4, vskiplines == 4); 367 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt2, vskiplines == 2); 368 369 VOP_SCL_SET_EXT(vop, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 370 VOP_SCL_SET_EXT(vop, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 371 VOP_SCL_SET_EXT(vop, yrgb_hsd_mode, SCALE_DOWN_BIL); 372 VOP_SCL_SET_EXT(vop, yrgb_vsd_mode, SCALE_DOWN_BIL); 373 VOP_SCL_SET_EXT(vop, yrgb_vsu_mode, vsu_mode); 374 if (is_yuv) { 375 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 376 dst_w, true, 0, NULL); 377 VOP_SCL_SET(vop, scale_cbcr_x, val); 378 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 379 dst_h, false, vsu_mode, &vskiplines); 380 VOP_SCL_SET(vop, scale_cbcr_y, val); 381 382 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt4, vskiplines == 4); 383 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt2, vskiplines == 2); 384 VOP_SCL_SET_EXT(vop, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 385 VOP_SCL_SET_EXT(vop, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 386 VOP_SCL_SET_EXT(vop, cbcr_hsd_mode, SCALE_DOWN_BIL); 387 VOP_SCL_SET_EXT(vop, cbcr_vsd_mode, SCALE_DOWN_BIL); 388 VOP_SCL_SET_EXT(vop, cbcr_vsu_mode, vsu_mode); 389 } 390 } 391 392 static int rockchip_vop_set_plane(struct display_state *state) 393 { 394 struct crtc_state *crtc_state = &state->crtc_state; 395 struct connector_state *conn_state = &state->conn_state; 396 struct drm_display_mode *mode = &conn_state->mode; 397 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 398 struct vop *vop = crtc_state->private; 399 int src_w = crtc_state->src_w; 400 int src_h = crtc_state->src_h; 401 int crtc_x = crtc_state->crtc_x; 402 int crtc_y = crtc_state->crtc_y; 403 int crtc_w = crtc_state->crtc_w; 404 int crtc_h = crtc_state->crtc_h; 405 int xvir = crtc_state->xvir; 406 407 act_info = (src_h - 1) << 16; 408 act_info |= (src_w - 1) & 0xffff; 409 410 dsp_info = (crtc_h - 1) << 16; 411 dsp_info |= (crtc_w - 1) & 0xffff; 412 413 dsp_stx = crtc_x + mode->htotal - mode->hsync_start; 414 dsp_sty = crtc_y + mode->vtotal - mode->vsync_start; 415 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 416 417 if (crtc_state->ymirror) 418 crtc_state->dma_addr += (src_h - 1) * xvir * 4; 419 VOP_WIN_SET(vop, ymirror, crtc_state->ymirror); 420 VOP_WIN_SET(vop, format, crtc_state->format); 421 VOP_WIN_SET(vop, yrgb_vir, xvir); 422 VOP_WIN_SET(vop, yrgb_mst, crtc_state->dma_addr); 423 424 scl_vop_cal_scl_fac(vop, src_w, src_h, crtc_w, crtc_h, 425 crtc_state->format); 426 427 VOP_WIN_SET(vop, act_info, act_info); 428 VOP_WIN_SET(vop, dsp_info, dsp_info); 429 VOP_WIN_SET(vop, dsp_st, dsp_st); 430 VOP_WIN_SET(vop, rb_swap, crtc_state->rb_swap); 431 432 VOP_WIN_SET(vop, src_alpha_ctl, 0); 433 434 VOP_WIN_SET(vop, enable, 1); 435 vop_cfg_done(vop); 436 437 return 0; 438 } 439 440 static int rockchip_vop_prepare(struct display_state *state) 441 { 442 return 0; 443 } 444 445 static int rockchip_vop_enable(struct display_state *state) 446 { 447 struct crtc_state *crtc_state = &state->crtc_state; 448 struct vop *vop = crtc_state->private; 449 450 VOP_CTRL_SET(vop, standby, 0); 451 vop_cfg_done(vop); 452 453 return 0; 454 } 455 456 static int rockchip_vop_disable(struct display_state *state) 457 { 458 struct crtc_state *crtc_state = &state->crtc_state; 459 struct vop *vop = crtc_state->private; 460 461 VOP_CTRL_SET(vop, standby, 1); 462 vop_cfg_done(vop); 463 return 0; 464 } 465 466 static int rockchip_vop_fixup_dts(struct display_state *state, void *blob) 467 { 468 struct crtc_state *crtc_state = &state->crtc_state; 469 struct panel_state *pstate = &state->panel_state; 470 uint32_t phandle; 471 char path[100]; 472 int ret, dsp_lut_node; 473 474 if (!pstate->dsp_lut_node) 475 return 0; 476 477 ret = fdt_get_path(state->blob, pstate->dsp_lut_node, path, sizeof(path)); 478 if (ret < 0) { 479 printf("failed to get dsp_lut path[%s], ret=%d\n", 480 path, ret); 481 return ret; 482 } 483 484 dsp_lut_node = fdt_path_offset(blob, path); 485 phandle = fdt_get_phandle(blob, dsp_lut_node); 486 if (!phandle) { 487 phandle = fdt_alloc_phandle(blob); 488 if (!phandle) { 489 printf("failed to alloc phandle\n"); 490 return -ENOMEM; 491 } 492 493 fdt_set_phandle(blob, dsp_lut_node, phandle); 494 } 495 496 ret = fdt_get_path(state->blob, crtc_state->node, path, sizeof(path)); 497 if (ret < 0) { 498 printf("failed to get route path[%s], ret=%d\n", 499 path, ret); 500 return ret; 501 } 502 503 do_fixup_by_path_u32(blob, path, "dsp-lut", phandle, 1); 504 505 return 0; 506 } 507 508 const struct rockchip_crtc_funcs rockchip_vop_funcs = { 509 .init = rockchip_vop_init, 510 .set_plane = rockchip_vop_set_plane, 511 .prepare = rockchip_vop_prepare, 512 .enable = rockchip_vop_enable, 513 .disable = rockchip_vop_disable, 514 .fixup_dts = rockchip_vop_fixup_dts, 515 }; 516