1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <asm/io.h> 15 #include <linux/list.h> 16 #include <linux/media-bus-format.h> 17 #include <clk.h> 18 #include <asm/arch/clock.h> 19 #include <linux/err.h> 20 #include <dm/device.h> 21 #include <dm/read.h> 22 23 #include "rockchip_display.h" 24 #include "rockchip_crtc.h" 25 #include "rockchip_connector.h" 26 #include "rockchip_vop.h" 27 28 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 29 { 30 return us * mode->clock / mode->htotal / 1000; 31 } 32 33 static int to_vop_csc_mode(int csc_mode) 34 { 35 switch (csc_mode) { 36 case V4L2_COLORSPACE_SMPTE170M: 37 return CSC_BT601L; 38 case V4L2_COLORSPACE_REC709: 39 case V4L2_COLORSPACE_DEFAULT: 40 return CSC_BT709L; 41 case V4L2_COLORSPACE_JPEG: 42 return CSC_BT601F; 43 case V4L2_COLORSPACE_BT2020: 44 return CSC_BT2020; 45 default: 46 return CSC_BT709L; 47 } 48 } 49 50 static bool is_yuv_output(uint32_t bus_format) 51 { 52 switch (bus_format) { 53 case MEDIA_BUS_FMT_YUV8_1X24: 54 case MEDIA_BUS_FMT_YUV10_1X30: 55 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 56 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 57 return true; 58 default: 59 return false; 60 } 61 } 62 63 static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode) 64 { 65 /* 66 * FIXME: 67 * 68 * There is no media type for YUV444 output, 69 * so when out_mode is AAAA or P888, assume output is YUV444 on 70 * yuv format. 71 * 72 * From H/W testing, YUV444 mode need a rb swap. 73 */ 74 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 75 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 76 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 77 output_mode == ROCKCHIP_OUT_MODE_P888)) 78 return true; 79 else 80 return false; 81 } 82 83 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) 84 { 85 struct crtc_state *crtc_state = &state->crtc_state; 86 struct connector_state *conn_state = &state->conn_state; 87 u32 *lut = conn_state->gamma.lut; 88 fdt_size_t lut_size; 89 int i, lut_len; 90 u32 *lut_regs; 91 92 if (!conn_state->gamma.lut) 93 return 0; 94 95 i = dev_read_stringlist_search(crtc_state->dev, "reg-names", "gamma_lut"); 96 if (i < 0) { 97 printf("Warning: vop not support gamma\n"); 98 return 0; 99 } 100 lut_regs = (u32 *)dev_read_addr_size(crtc_state->dev, "reg", &lut_size); 101 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 102 printf("failed to get gamma lut register\n"); 103 return 0; 104 } 105 lut_len = lut_size / 4; 106 if (lut_len != 256 && lut_len != 1024) { 107 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 108 return 0; 109 } 110 111 if (conn_state->gamma.size != lut_len) { 112 int size = conn_state->gamma.size; 113 u32 j, r, g, b, color; 114 115 for (i = 0; i < lut_len; i++) { 116 j = i * size / lut_len; 117 r = lut[j] / size / size * lut_len / size; 118 g = lut[j] / size % size * lut_len / size; 119 b = lut[j] % size * lut_len / size; 120 color = r * lut_len * lut_len + g * lut_len + b; 121 122 writel(color, lut_regs + (i << 2)); 123 } 124 } else { 125 for (i = 0; i < lut_len; i++) 126 writel(lut[i], lut_regs + (i << 2)); 127 } 128 129 VOP_CTRL_SET(vop, dsp_lut_en, 1); 130 VOP_CTRL_SET(vop, update_gamma_lut, 1); 131 132 return 0; 133 } 134 135 static void vop_post_config(struct display_state *state, struct vop *vop) 136 { 137 struct connector_state *conn_state = &state->conn_state; 138 struct drm_display_mode *mode = &conn_state->mode; 139 u16 vtotal = mode->crtc_vtotal; 140 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 141 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 142 u16 hdisplay = mode->crtc_hdisplay; 143 u16 vdisplay = mode->crtc_vdisplay; 144 u16 hsize = hdisplay * (conn_state->overscan.left_margin + conn_state->overscan.right_margin) / 200; 145 u16 vsize = vdisplay * (conn_state->overscan.top_margin + conn_state->overscan.bottom_margin) / 200; 146 u16 hact_end, vact_end; 147 u32 val; 148 149 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 150 vsize = round_down(vsize, 2); 151 152 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 153 hact_end = hact_st + hsize; 154 val = hact_st << 16; 155 val |= hact_end; 156 157 VOP_CTRL_SET(vop, hpost_st_end, val); 158 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 159 vact_end = vact_st + vsize; 160 val = vact_st << 16; 161 val |= vact_end; 162 VOP_CTRL_SET(vop, vpost_st_end, val); 163 val = scl_cal_scale2(vdisplay, vsize) << 16; 164 val |= scl_cal_scale2(hdisplay, hsize); 165 VOP_CTRL_SET(vop, post_scl_factor, val); 166 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 167 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 168 VOP_CTRL_SET(vop, post_scl_ctrl, 169 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 170 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 171 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 172 u16 vact_st_f1 = vtotal + vact_st + 1; 173 u16 vact_end_f1 = vact_st_f1 + vsize; 174 175 val = vact_st_f1 << 16 | vact_end_f1; 176 VOP_CTRL_SET(vop, vpost_st_end_f1, val); 177 } 178 } 179 180 static int rockchip_vop_init(struct display_state *state) 181 { 182 struct crtc_state *crtc_state = &state->crtc_state; 183 struct connector_state *conn_state = &state->conn_state; 184 struct drm_display_mode *mode = &conn_state->mode; 185 const struct rockchip_crtc *crtc = crtc_state->crtc; 186 const struct vop_data *vop_data = crtc->data; 187 struct vop *vop; 188 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 189 u16 hdisplay = mode->crtc_hdisplay; 190 u16 htotal = mode->crtc_htotal; 191 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 192 u16 hact_end = hact_st + hdisplay; 193 u16 vdisplay = mode->crtc_vdisplay; 194 u16 vtotal = mode->crtc_vtotal; 195 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 196 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 197 u16 vact_end = vact_st + vdisplay; 198 struct clk dclk, aclk; 199 u32 val, act_end; 200 int ret; 201 bool yuv_overlay = false, post_r2y_en = false, post_y2r_en = false; 202 u16 post_csc_mode; 203 204 vop = malloc(sizeof(*vop)); 205 if (!vop) 206 return -ENOMEM; 207 memset(vop, 0, sizeof(*vop)); 208 209 crtc_state->private = vop; 210 vop->regs = dev_read_addr_ptr(crtc_state->dev); 211 vop->regsbak = malloc(vop_data->reg_len); 212 vop->win = vop_data->win; 213 vop->win_offset = vop_data->win_offset; 214 vop->ctrl = vop_data->ctrl; 215 vop->line_flag = vop_data->line_flag; 216 vop->version = vop_data->version; 217 218 /* 219 * TODO: 220 * Set Dclk pll parent 221 */ 222 223 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &dclk); 224 if (!ret) 225 ret = clk_set_rate(&dclk, mode->clock * 1000); 226 if (IS_ERR_VALUE(ret)) { 227 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret); 228 return ret; 229 } 230 231 ret = clk_get_by_name(crtc_state->dev, "aclk_vop", &aclk); 232 if (!ret) 233 ret = clk_set_rate(&aclk, 400 * 1000 * 1000); 234 if (IS_ERR_VALUE(ret)) 235 printf("%s: Failed to set aclk: ret=%d\n", __func__, ret); 236 237 memcpy(vop->regsbak, vop->regs, vop_data->reg_len); 238 239 rockchip_vop_init_gamma(vop, state); 240 241 VOP_CTRL_SET(vop, global_regdone_en, 1); 242 VOP_CTRL_SET(vop, reg_done_frm, 1); 243 VOP_CTRL_SET(vop, win_gate[0], 1); 244 VOP_CTRL_SET(vop, win_gate[1], 1); 245 VOP_CTRL_SET(vop, dsp_blank, 0); 246 247 val = 0x8; 248 val |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 249 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 250 VOP_CTRL_SET(vop, pin_pol, val); 251 252 switch (conn_state->type) { 253 case DRM_MODE_CONNECTOR_LVDS: 254 VOP_CTRL_SET(vop, rgb_en, 1); 255 VOP_CTRL_SET(vop, rgb_pin_pol, val); 256 break; 257 case DRM_MODE_CONNECTOR_eDP: 258 VOP_CTRL_SET(vop, edp_en, 1); 259 VOP_CTRL_SET(vop, edp_pin_pol, val); 260 break; 261 case DRM_MODE_CONNECTOR_HDMIA: 262 VOP_CTRL_SET(vop, hdmi_en, 1); 263 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 264 break; 265 case DRM_MODE_CONNECTOR_DSI: 266 VOP_CTRL_SET(vop, mipi_en, 1); 267 VOP_CTRL_SET(vop, mipi_pin_pol, val); 268 VOP_CTRL_SET(vop, mipi_dual_channel_en, 269 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL)); 270 VOP_CTRL_SET(vop, data01_swap, 271 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_LINK)); 272 break; 273 default: 274 printf("unsupport connector_type[%d]\n", conn_state->type); 275 } 276 277 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 278 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 279 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 280 281 switch (conn_state->bus_format) { 282 case MEDIA_BUS_FMT_RGB565_1X16: 283 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565); 284 break; 285 case MEDIA_BUS_FMT_RGB666_1X18: 286 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 287 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666); 288 break; 289 case MEDIA_BUS_FMT_YUV8_1X24: 290 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 291 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1); 292 break; 293 case MEDIA_BUS_FMT_YUV10_1X30: 294 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 295 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 296 break; 297 case MEDIA_BUS_FMT_RGB888_1X24: 298 default: 299 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 300 break; 301 } 302 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 303 val |= PRE_DITHER_DOWN_EN(0); 304 else 305 val |= PRE_DITHER_DOWN_EN(1); 306 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO); 307 VOP_CTRL_SET(vop, dither_down, val); 308 309 VOP_CTRL_SET(vop, dclk_ddr, 310 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 311 VOP_CTRL_SET(vop, hdmi_dclk_out_en, 312 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 313 314 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 315 VOP_CTRL_SET(vop, dsp_data_swap, DSP_RB_SWAP); 316 else 317 VOP_CTRL_SET(vop, dsp_data_swap, 0); 318 319 VOP_CTRL_SET(vop, out_mode, conn_state->output_mode); 320 321 if (VOP_CTRL_SUPPORT(vop, overlay_mode)) { 322 yuv_overlay = is_yuv_output(conn_state->bus_format); 323 VOP_CTRL_SET(vop, overlay_mode, yuv_overlay); 324 } 325 /* 326 * todo: r2y for win csc 327 */ 328 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(conn_state->bus_format)); 329 330 if (yuv_overlay) { 331 if (!is_yuv_output(conn_state->bus_format)) 332 post_y2r_en = true; 333 } else { 334 if (is_yuv_output(conn_state->bus_format)) 335 post_r2y_en = true; 336 } 337 338 post_csc_mode = to_vop_csc_mode(conn_state->color_space); 339 VOP_CTRL_SET(vop, bcsh_r2y_en, post_r2y_en); 340 VOP_CTRL_SET(vop, bcsh_y2r_en, post_y2r_en); 341 VOP_CTRL_SET(vop, bcsh_r2y_csc_mode, post_csc_mode); 342 VOP_CTRL_SET(vop, bcsh_y2r_csc_mode, post_csc_mode); 343 344 /* 345 * Background color is 10bit depth if vop version >= 3.5 346 */ 347 if (!is_yuv_output(conn_state->bus_format)) 348 val = 0; 349 else if (VOP_MAJOR(vop->version) == 3 && 350 VOP_MINOR(vop->version) >= 5) 351 val = 0x20010200; 352 else 353 val = 0x801080; 354 VOP_CTRL_SET(vop, dsp_background, val); 355 356 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 357 val = hact_st << 16; 358 val |= hact_end; 359 VOP_CTRL_SET(vop, hact_st_end, val); 360 val = vact_st << 16; 361 val |= vact_end; 362 VOP_CTRL_SET(vop, vact_st_end, val); 363 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 364 u16 vact_st_f1 = vtotal + vact_st + 1; 365 u16 vact_end_f1 = vact_st_f1 + vdisplay; 366 367 val = vact_st_f1 << 16 | vact_end_f1; 368 VOP_CTRL_SET(vop, vact_st_end_f1, val); 369 370 val = vtotal << 16 | (vtotal + vsync_len); 371 VOP_CTRL_SET(vop, vs_st_end_f1, val); 372 VOP_CTRL_SET(vop, dsp_interlace, 1); 373 VOP_CTRL_SET(vop, p2i_en, 1); 374 vtotal += vtotal + 1; 375 act_end = vact_end_f1; 376 } else { 377 VOP_CTRL_SET(vop, dsp_interlace, 0); 378 VOP_CTRL_SET(vop, p2i_en, 0); 379 act_end = vact_end; 380 } 381 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 382 vop_post_config(state, vop); 383 VOP_CTRL_SET(vop, core_dclk_div, 384 !!(mode->flags & DRM_MODE_FLAG_DBLCLK)); 385 386 VOP_CTRL_SET(vop, standby, 1); 387 VOP_LINE_FLAG_SET(vop, line_flag_num[0], act_end - 3); 388 VOP_LINE_FLAG_SET(vop, line_flag_num[1], 389 act_end - us_to_vertical_line(mode, 1000)); 390 vop_cfg_done(vop); 391 392 return 0; 393 } 394 395 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 396 uint32_t dst, bool is_horizontal, 397 int vsu_mode, int *vskiplines) 398 { 399 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 400 401 if (is_horizontal) { 402 if (mode == SCALE_UP) 403 val = GET_SCL_FT_BIC(src, dst); 404 else if (mode == SCALE_DOWN) 405 val = GET_SCL_FT_BILI_DN(src, dst); 406 } else { 407 if (mode == SCALE_UP) { 408 if (vsu_mode == SCALE_UP_BIL) 409 val = GET_SCL_FT_BILI_UP(src, dst); 410 else 411 val = GET_SCL_FT_BIC(src, dst); 412 } else if (mode == SCALE_DOWN) { 413 if (vskiplines) { 414 *vskiplines = scl_get_vskiplines(src, dst); 415 val = scl_get_bili_dn_vskip(src, dst, 416 *vskiplines); 417 } else { 418 val = GET_SCL_FT_BILI_DN(src, dst); 419 } 420 } 421 } 422 423 return val; 424 } 425 426 static void scl_vop_cal_scl_fac(struct vop *vop, 427 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 428 uint32_t dst_h, uint32_t pixel_format) 429 { 430 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 431 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 432 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 433 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 434 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 435 bool is_yuv = false; 436 uint16_t cbcr_src_w = src_w / hsub; 437 uint16_t cbcr_src_h = src_h / vsub; 438 uint16_t vsu_mode; 439 uint16_t lb_mode; 440 uint32_t val; 441 int vskiplines = 0; 442 443 if (!vop->win->scl) 444 return; 445 446 if (dst_w > 3840) { 447 printf("Maximum destination width (3840) exceeded\n"); 448 return; 449 } 450 451 if (!vop->win->scl->ext) { 452 VOP_SCL_SET(vop, scale_yrgb_x, 453 scl_cal_scale2(src_w, dst_w)); 454 VOP_SCL_SET(vop, scale_yrgb_y, 455 scl_cal_scale2(src_h, dst_h)); 456 if (is_yuv) { 457 VOP_SCL_SET(vop, scale_cbcr_x, 458 scl_cal_scale2(src_w, dst_w)); 459 VOP_SCL_SET(vop, scale_cbcr_y, 460 scl_cal_scale2(src_h, dst_h)); 461 } 462 return; 463 } 464 465 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 466 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 467 468 if (is_yuv) { 469 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 470 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 471 if (cbcr_hor_scl_mode == SCALE_DOWN) 472 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 473 else 474 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 475 } else { 476 if (yrgb_hor_scl_mode == SCALE_DOWN) 477 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 478 else 479 lb_mode = scl_vop_cal_lb_mode(src_w, false); 480 } 481 482 VOP_SCL_SET_EXT(vop, lb_mode, lb_mode); 483 if (lb_mode == LB_RGB_3840X2) { 484 if (yrgb_ver_scl_mode != SCALE_NONE) { 485 printf("ERROR : not allow yrgb ver scale\n"); 486 return; 487 } 488 if (cbcr_ver_scl_mode != SCALE_NONE) { 489 printf("ERROR : not allow cbcr ver scale\n"); 490 return; 491 } 492 vsu_mode = SCALE_UP_BIL; 493 } else if (lb_mode == LB_RGB_2560X4) { 494 vsu_mode = SCALE_UP_BIL; 495 } else { 496 vsu_mode = SCALE_UP_BIC; 497 } 498 499 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 500 true, 0, NULL); 501 VOP_SCL_SET(vop, scale_yrgb_x, val); 502 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 503 false, vsu_mode, &vskiplines); 504 VOP_SCL_SET(vop, scale_yrgb_y, val); 505 506 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt4, vskiplines == 4); 507 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt2, vskiplines == 2); 508 509 VOP_SCL_SET_EXT(vop, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 510 VOP_SCL_SET_EXT(vop, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 511 VOP_SCL_SET_EXT(vop, yrgb_hsd_mode, SCALE_DOWN_BIL); 512 VOP_SCL_SET_EXT(vop, yrgb_vsd_mode, SCALE_DOWN_BIL); 513 VOP_SCL_SET_EXT(vop, yrgb_vsu_mode, vsu_mode); 514 if (is_yuv) { 515 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 516 dst_w, true, 0, NULL); 517 VOP_SCL_SET(vop, scale_cbcr_x, val); 518 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 519 dst_h, false, vsu_mode, &vskiplines); 520 VOP_SCL_SET(vop, scale_cbcr_y, val); 521 522 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt4, vskiplines == 4); 523 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt2, vskiplines == 2); 524 VOP_SCL_SET_EXT(vop, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 525 VOP_SCL_SET_EXT(vop, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 526 VOP_SCL_SET_EXT(vop, cbcr_hsd_mode, SCALE_DOWN_BIL); 527 VOP_SCL_SET_EXT(vop, cbcr_vsd_mode, SCALE_DOWN_BIL); 528 VOP_SCL_SET_EXT(vop, cbcr_vsu_mode, vsu_mode); 529 } 530 } 531 532 static int rockchip_vop_set_plane(struct display_state *state) 533 { 534 struct crtc_state *crtc_state = &state->crtc_state; 535 struct connector_state *conn_state = &state->conn_state; 536 struct drm_display_mode *mode = &conn_state->mode; 537 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 538 struct vop *vop = crtc_state->private; 539 int src_w = crtc_state->src_w; 540 int src_h = crtc_state->src_h; 541 int crtc_x = crtc_state->crtc_x; 542 int crtc_y = crtc_state->crtc_y; 543 int crtc_w = crtc_state->crtc_w; 544 int crtc_h = crtc_state->crtc_h; 545 int xvir = crtc_state->xvir; 546 547 act_info = (src_h - 1) << 16; 548 act_info |= (src_w - 1) & 0xffff; 549 550 dsp_info = (crtc_h - 1) << 16; 551 dsp_info |= (crtc_w - 1) & 0xffff; 552 553 dsp_stx = crtc_x + mode->htotal - mode->hsync_start; 554 dsp_sty = crtc_y + mode->vtotal - mode->vsync_start; 555 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 556 557 if (crtc_state->ymirror) 558 crtc_state->dma_addr += (src_h - 1) * xvir * 4; 559 VOP_WIN_SET(vop, ymirror, crtc_state->ymirror); 560 VOP_WIN_SET(vop, format, crtc_state->format); 561 VOP_WIN_SET(vop, yrgb_vir, xvir); 562 VOP_WIN_SET(vop, yrgb_mst, crtc_state->dma_addr); 563 564 scl_vop_cal_scl_fac(vop, src_w, src_h, crtc_w, crtc_h, 565 crtc_state->format); 566 567 VOP_WIN_SET(vop, act_info, act_info); 568 VOP_WIN_SET(vop, dsp_info, dsp_info); 569 VOP_WIN_SET(vop, dsp_st, dsp_st); 570 VOP_WIN_SET(vop, rb_swap, crtc_state->rb_swap); 571 572 VOP_WIN_SET(vop, src_alpha_ctl, 0); 573 574 VOP_WIN_SET(vop, enable, 1); 575 vop_cfg_done(vop); 576 577 return 0; 578 } 579 580 static int rockchip_vop_prepare(struct display_state *state) 581 { 582 return 0; 583 } 584 585 static int rockchip_vop_enable(struct display_state *state) 586 { 587 struct crtc_state *crtc_state = &state->crtc_state; 588 struct vop *vop = crtc_state->private; 589 590 VOP_CTRL_SET(vop, standby, 0); 591 vop_cfg_done(vop); 592 593 return 0; 594 } 595 596 static int rockchip_vop_disable(struct display_state *state) 597 { 598 struct crtc_state *crtc_state = &state->crtc_state; 599 struct vop *vop = crtc_state->private; 600 601 VOP_CTRL_SET(vop, standby, 1); 602 vop_cfg_done(vop); 603 return 0; 604 } 605 606 static int rockchip_vop_fixup_dts(struct display_state *state, void *blob) 607 { 608 #if 0 609 struct crtc_state *crtc_state = &state->crtc_state; 610 struct panel_state *pstate = &state->panel_state; 611 uint32_t phandle; 612 char path[100]; 613 int ret, dsp_lut_node; 614 615 if (!ofnode_valid(pstate->dsp_lut_node)) 616 return 0; 617 ret = fdt_get_path(state->blob, pstate->dsp_lut_node, path, sizeof(path)); 618 if (ret < 0) { 619 printf("failed to get dsp_lut path[%s], ret=%d\n", 620 path, ret); 621 return ret; 622 } 623 624 dsp_lut_node = fdt_path_offset(blob, path); 625 phandle = fdt_get_phandle(blob, dsp_lut_node); 626 if (!phandle) { 627 phandle = fdt_alloc_phandle(blob); 628 if (!phandle) { 629 printf("failed to alloc phandle\n"); 630 return -ENOMEM; 631 } 632 633 fdt_set_phandle(blob, dsp_lut_node, phandle); 634 } 635 636 ret = fdt_get_path(state->blob, crtc_state->node, path, sizeof(path)); 637 if (ret < 0) { 638 printf("failed to get route path[%s], ret=%d\n", 639 path, ret); 640 return ret; 641 } 642 643 do_fixup_by_path_u32(blob, path, "dsp-lut", phandle, 1); 644 #endif 645 return 0; 646 } 647 648 const struct rockchip_crtc_funcs rockchip_vop_funcs = { 649 .init = rockchip_vop_init, 650 .set_plane = rockchip_vop_set_plane, 651 .prepare = rockchip_vop_prepare, 652 .enable = rockchip_vop_enable, 653 .disable = rockchip_vop_disable, 654 .fixup_dts = rockchip_vop_fixup_dts, 655 }; 656