1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <asm/io.h> 15 #include <linux/list.h> 16 #include <linux/media-bus-format.h> 17 #include <clk.h> 18 #include <asm/arch/clock.h> 19 #include <linux/err.h> 20 #include <dm/device.h> 21 #include <dm/read.h> 22 #include <syscon.h> 23 24 #include "rockchip_display.h" 25 #include "rockchip_crtc.h" 26 #include "rockchip_connector.h" 27 #include "rockchip_vop.h" 28 29 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 30 { 31 return us * mode->clock / mode->htotal / 1000; 32 } 33 34 static int to_vop_csc_mode(int csc_mode) 35 { 36 switch (csc_mode) { 37 case V4L2_COLORSPACE_SMPTE170M: 38 return CSC_BT601L; 39 case V4L2_COLORSPACE_REC709: 40 case V4L2_COLORSPACE_DEFAULT: 41 return CSC_BT709L; 42 case V4L2_COLORSPACE_JPEG: 43 return CSC_BT601F; 44 case V4L2_COLORSPACE_BT2020: 45 return CSC_BT2020; 46 default: 47 return CSC_BT709L; 48 } 49 } 50 51 static bool is_yuv_output(uint32_t bus_format) 52 { 53 switch (bus_format) { 54 case MEDIA_BUS_FMT_YUV8_1X24: 55 case MEDIA_BUS_FMT_YUV10_1X30: 56 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 57 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 58 return true; 59 default: 60 return false; 61 } 62 } 63 64 static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode) 65 { 66 /* 67 * FIXME: 68 * 69 * There is no media type for YUV444 output, 70 * so when out_mode is AAAA or P888, assume output is YUV444 on 71 * yuv format. 72 * 73 * From H/W testing, YUV444 mode need a rb swap. 74 */ 75 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 76 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 77 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 78 output_mode == ROCKCHIP_OUT_MODE_P888)) 79 return true; 80 else 81 return false; 82 } 83 84 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) 85 { 86 struct crtc_state *crtc_state = &state->crtc_state; 87 struct connector_state *conn_state = &state->conn_state; 88 u32 *lut = conn_state->gamma.lut; 89 fdt_size_t lut_size; 90 int i, lut_len; 91 u32 *lut_regs; 92 93 if (!conn_state->gamma.lut) 94 return 0; 95 96 i = dev_read_stringlist_search(crtc_state->dev, "reg-names", "gamma_lut"); 97 if (i < 0) { 98 printf("Warning: vop not support gamma\n"); 99 return 0; 100 } 101 lut_regs = (u32 *)dev_read_addr_size(crtc_state->dev, "reg", &lut_size); 102 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 103 printf("failed to get gamma lut register\n"); 104 return 0; 105 } 106 lut_len = lut_size / 4; 107 if (lut_len != 256 && lut_len != 1024) { 108 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 109 return 0; 110 } 111 112 if (conn_state->gamma.size != lut_len) { 113 int size = conn_state->gamma.size; 114 u32 j, r, g, b, color; 115 116 for (i = 0; i < lut_len; i++) { 117 j = i * size / lut_len; 118 r = lut[j] / size / size * lut_len / size; 119 g = lut[j] / size % size * lut_len / size; 120 b = lut[j] % size * lut_len / size; 121 color = r * lut_len * lut_len + g * lut_len + b; 122 123 writel(color, lut_regs + (i << 2)); 124 } 125 } else { 126 for (i = 0; i < lut_len; i++) 127 writel(lut[i], lut_regs + (i << 2)); 128 } 129 130 VOP_CTRL_SET(vop, dsp_lut_en, 1); 131 VOP_CTRL_SET(vop, update_gamma_lut, 1); 132 133 return 0; 134 } 135 136 static void vop_post_config(struct display_state *state, struct vop *vop) 137 { 138 struct connector_state *conn_state = &state->conn_state; 139 struct drm_display_mode *mode = &conn_state->mode; 140 u16 vtotal = mode->crtc_vtotal; 141 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 142 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 143 u16 hdisplay = mode->crtc_hdisplay; 144 u16 vdisplay = mode->crtc_vdisplay; 145 u16 hsize = hdisplay * (conn_state->overscan.left_margin + conn_state->overscan.right_margin) / 200; 146 u16 vsize = vdisplay * (conn_state->overscan.top_margin + conn_state->overscan.bottom_margin) / 200; 147 u16 hact_end, vact_end; 148 u32 val; 149 150 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 151 vsize = round_down(vsize, 2); 152 153 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 154 hact_end = hact_st + hsize; 155 val = hact_st << 16; 156 val |= hact_end; 157 158 VOP_CTRL_SET(vop, hpost_st_end, val); 159 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 160 vact_end = vact_st + vsize; 161 val = vact_st << 16; 162 val |= vact_end; 163 VOP_CTRL_SET(vop, vpost_st_end, val); 164 val = scl_cal_scale2(vdisplay, vsize) << 16; 165 val |= scl_cal_scale2(hdisplay, hsize); 166 VOP_CTRL_SET(vop, post_scl_factor, val); 167 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 168 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 169 VOP_CTRL_SET(vop, post_scl_ctrl, 170 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 171 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 172 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 173 u16 vact_st_f1 = vtotal + vact_st + 1; 174 u16 vact_end_f1 = vact_st_f1 + vsize; 175 176 val = vact_st_f1 << 16 | vact_end_f1; 177 VOP_CTRL_SET(vop, vpost_st_end_f1, val); 178 } 179 } 180 181 static void vop_mcu_mode(struct display_state *state, struct vop *vop) 182 { 183 struct crtc_state *crtc_state = &state->crtc_state; 184 185 VOP_CTRL_SET(vop, mcu_clk_sel, 1); 186 VOP_CTRL_SET(vop, mcu_type, 1); 187 188 VOP_CTRL_SET(vop, mcu_hold_mode, 1); 189 VOP_CTRL_SET(vop, mcu_pix_total, crtc_state->mcu_timing.mcu_pix_total); 190 VOP_CTRL_SET(vop, mcu_cs_pst, crtc_state->mcu_timing.mcu_cs_pst); 191 VOP_CTRL_SET(vop, mcu_cs_pend, crtc_state->mcu_timing.mcu_cs_pend); 192 VOP_CTRL_SET(vop, mcu_rw_pst, crtc_state->mcu_timing.mcu_rw_pst); 193 VOP_CTRL_SET(vop, mcu_rw_pend, crtc_state->mcu_timing.mcu_rw_pend); 194 } 195 196 static int rockchip_vop_init(struct display_state *state) 197 { 198 struct crtc_state *crtc_state = &state->crtc_state; 199 struct connector_state *conn_state = &state->conn_state; 200 struct drm_display_mode *mode = &conn_state->mode; 201 const struct rockchip_crtc *crtc = crtc_state->crtc; 202 const struct vop_data *vop_data = crtc->data; 203 struct vop *vop; 204 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 205 u16 hdisplay = mode->crtc_hdisplay; 206 u16 htotal = mode->crtc_htotal; 207 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 208 u16 hact_end = hact_st + hdisplay; 209 u16 vdisplay = mode->crtc_vdisplay; 210 u16 vtotal = mode->crtc_vtotal; 211 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 212 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 213 u16 vact_end = vact_st + vdisplay; 214 struct clk dclk; 215 u32 val, act_end; 216 int ret; 217 bool yuv_overlay = false, post_r2y_en = false, post_y2r_en = false; 218 u16 post_csc_mode; 219 bool dclk_inv; 220 221 vop = malloc(sizeof(*vop)); 222 if (!vop) 223 return -ENOMEM; 224 memset(vop, 0, sizeof(*vop)); 225 226 crtc_state->private = vop; 227 vop->regs = dev_read_addr_ptr(crtc_state->dev); 228 vop->regsbak = malloc(vop_data->reg_len); 229 vop->win = vop_data->win; 230 vop->win_offset = vop_data->win_offset; 231 vop->ctrl = vop_data->ctrl; 232 vop->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 233 if (vop->grf <= 0) 234 printf("%s: Get syscon grf failed (ret=%p)\n", 235 __func__, vop->grf); 236 237 vop->grf_ctrl = vop_data->grf_ctrl; 238 vop->line_flag = vop_data->line_flag; 239 vop->version = vop_data->version; 240 vop->max_output = vop_data->max_output; 241 242 /* 243 * TODO: 244 * Set Dclk pll parent 245 */ 246 247 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &dclk); 248 if (!ret) 249 ret = clk_set_rate(&dclk, mode->clock * 1000); 250 if (IS_ERR_VALUE(ret)) { 251 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret); 252 return ret; 253 } 254 255 memcpy(vop->regsbak, vop->regs, vop_data->reg_len); 256 257 rockchip_vop_init_gamma(vop, state); 258 259 VOP_CTRL_SET(vop, global_regdone_en, 1); 260 VOP_CTRL_SET(vop, axi_outstanding_max_num, 30); 261 VOP_CTRL_SET(vop, axi_max_outstanding_en, 1); 262 VOP_CTRL_SET(vop, reg_done_frm, 1); 263 VOP_CTRL_SET(vop, win_gate[0], 1); 264 VOP_CTRL_SET(vop, win_gate[1], 1); 265 VOP_CTRL_SET(vop, win_channel[0], 0x12); 266 VOP_CTRL_SET(vop, win_channel[1], 0x34); 267 VOP_CTRL_SET(vop, win_channel[2], 0x56); 268 VOP_CTRL_SET(vop, dsp_blank, 0); 269 270 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 271 VOP_CTRL_SET(vop, dclk_pol, dclk_inv); 272 273 val = 0x8; 274 val |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 275 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 276 VOP_CTRL_SET(vop, pin_pol, val); 277 278 switch (conn_state->type) { 279 case DRM_MODE_CONNECTOR_LVDS: 280 VOP_CTRL_SET(vop, rgb_en, 1); 281 VOP_CTRL_SET(vop, rgb_pin_pol, val); 282 VOP_CTRL_SET(vop, rgb_dclk_pol, dclk_inv); 283 VOP_CTRL_SET(vop, lvds_en, 1); 284 VOP_CTRL_SET(vop, lvds_pin_pol, val); 285 VOP_CTRL_SET(vop, lvds_dclk_pol, dclk_inv); 286 if (!IS_ERR_OR_NULL(vop->grf)) 287 VOP_GRF_SET(vop, grf_dclk_inv, !dclk_inv); 288 break; 289 case DRM_MODE_CONNECTOR_eDP: 290 VOP_CTRL_SET(vop, edp_en, 1); 291 VOP_CTRL_SET(vop, edp_pin_pol, val); 292 VOP_CTRL_SET(vop, edp_dclk_pol, dclk_inv); 293 break; 294 case DRM_MODE_CONNECTOR_HDMIA: 295 VOP_CTRL_SET(vop, hdmi_en, 1); 296 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 297 VOP_CTRL_SET(vop, hdmi_dclk_pol, 1); 298 break; 299 case DRM_MODE_CONNECTOR_DSI: 300 VOP_CTRL_SET(vop, mipi_en, 1); 301 VOP_CTRL_SET(vop, mipi_pin_pol, val); 302 VOP_CTRL_SET(vop, mipi_dclk_pol, dclk_inv); 303 VOP_CTRL_SET(vop, mipi_dual_channel_en, 304 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL)); 305 VOP_CTRL_SET(vop, data01_swap, 306 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_LINK)); 307 break; 308 case DRM_MODE_CONNECTOR_DisplayPort: 309 VOP_CTRL_SET(vop, dp_dclk_pol, 0); 310 VOP_CTRL_SET(vop, dp_pin_pol, val); 311 VOP_CTRL_SET(vop, dp_en, 1); 312 break; 313 case DRM_MODE_CONNECTOR_TV: 314 if (vdisplay == CVBS_PAL_VDISPLAY) 315 VOP_CTRL_SET(vop, tve_sw_mode, 1); 316 else 317 VOP_CTRL_SET(vop, tve_sw_mode, 0); 318 VOP_CTRL_SET(vop, tve_dclk_pol, 1); 319 VOP_CTRL_SET(vop, tve_dclk_en, 1); 320 /* use the same pol reg with hdmi */ 321 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 322 VOP_CTRL_SET(vop, sw_genlock, 1); 323 VOP_CTRL_SET(vop, sw_uv_offset_en, 1); 324 VOP_CTRL_SET(vop, dither_up, 1); 325 break; 326 default: 327 printf("unsupport connector_type[%d]\n", conn_state->type); 328 } 329 330 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 331 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 332 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 333 334 switch (conn_state->bus_format) { 335 case MEDIA_BUS_FMT_RGB565_1X16: 336 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565); 337 break; 338 case MEDIA_BUS_FMT_RGB666_1X18: 339 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 340 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666); 341 break; 342 case MEDIA_BUS_FMT_YUV8_1X24: 343 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 344 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1); 345 break; 346 case MEDIA_BUS_FMT_YUV10_1X30: 347 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 348 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 349 break; 350 case MEDIA_BUS_FMT_RGB888_1X24: 351 default: 352 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 353 break; 354 } 355 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 356 val |= PRE_DITHER_DOWN_EN(0); 357 else 358 val |= PRE_DITHER_DOWN_EN(1); 359 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO); 360 VOP_CTRL_SET(vop, dither_down, val); 361 362 VOP_CTRL_SET(vop, dclk_ddr, 363 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 364 VOP_CTRL_SET(vop, hdmi_dclk_out_en, 365 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 366 367 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 368 VOP_CTRL_SET(vop, dsp_data_swap, DSP_RB_SWAP); 369 else 370 VOP_CTRL_SET(vop, dsp_data_swap, 0); 371 372 VOP_CTRL_SET(vop, out_mode, conn_state->output_mode); 373 374 if (VOP_CTRL_SUPPORT(vop, overlay_mode)) { 375 yuv_overlay = is_yuv_output(conn_state->bus_format); 376 VOP_CTRL_SET(vop, overlay_mode, yuv_overlay); 377 } 378 /* 379 * todo: r2y for win csc 380 */ 381 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(conn_state->bus_format)); 382 383 if (yuv_overlay) { 384 if (!is_yuv_output(conn_state->bus_format)) 385 post_y2r_en = true; 386 } else { 387 if (is_yuv_output(conn_state->bus_format)) 388 post_r2y_en = true; 389 } 390 391 post_csc_mode = to_vop_csc_mode(conn_state->color_space); 392 VOP_CTRL_SET(vop, bcsh_r2y_en, post_r2y_en); 393 VOP_CTRL_SET(vop, bcsh_y2r_en, post_y2r_en); 394 VOP_CTRL_SET(vop, bcsh_r2y_csc_mode, post_csc_mode); 395 VOP_CTRL_SET(vop, bcsh_y2r_csc_mode, post_csc_mode); 396 397 /* 398 * Background color is 10bit depth if vop version >= 3.5 399 */ 400 if (!is_yuv_output(conn_state->bus_format)) 401 val = 0; 402 else if (VOP_MAJOR(vop->version) == 3 && 403 VOP_MINOR(vop->version) >= 5) 404 val = 0x20010200; 405 else 406 val = 0x801080; 407 VOP_CTRL_SET(vop, dsp_background, val); 408 409 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 410 val = hact_st << 16; 411 val |= hact_end; 412 VOP_CTRL_SET(vop, hact_st_end, val); 413 val = vact_st << 16; 414 val |= vact_end; 415 VOP_CTRL_SET(vop, vact_st_end, val); 416 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 417 u16 vact_st_f1 = vtotal + vact_st + 1; 418 u16 vact_end_f1 = vact_st_f1 + vdisplay; 419 420 val = vact_st_f1 << 16 | vact_end_f1; 421 VOP_CTRL_SET(vop, vact_st_end_f1, val); 422 423 val = vtotal << 16 | (vtotal + vsync_len); 424 VOP_CTRL_SET(vop, vs_st_end_f1, val); 425 VOP_CTRL_SET(vop, dsp_interlace, 1); 426 VOP_CTRL_SET(vop, p2i_en, 1); 427 vtotal += vtotal + 1; 428 act_end = vact_end_f1; 429 } else { 430 VOP_CTRL_SET(vop, dsp_interlace, 0); 431 VOP_CTRL_SET(vop, p2i_en, 0); 432 act_end = vact_end; 433 } 434 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 435 vop_post_config(state, vop); 436 VOP_CTRL_SET(vop, core_dclk_div, 437 !!(mode->flags & DRM_MODE_FLAG_DBLCLK)); 438 439 VOP_LINE_FLAG_SET(vop, line_flag_num[0], act_end - 3); 440 VOP_LINE_FLAG_SET(vop, line_flag_num[1], 441 act_end - us_to_vertical_line(mode, 1000)); 442 if (state->crtc_state.mcu_timing.mcu_pix_total > 0) 443 vop_mcu_mode(state, vop); 444 vop_cfg_done(vop); 445 446 return 0; 447 } 448 449 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 450 uint32_t dst, bool is_horizontal, 451 int vsu_mode, int *vskiplines) 452 { 453 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 454 455 if (is_horizontal) { 456 if (mode == SCALE_UP) 457 val = GET_SCL_FT_BIC(src, dst); 458 else if (mode == SCALE_DOWN) 459 val = GET_SCL_FT_BILI_DN(src, dst); 460 } else { 461 if (mode == SCALE_UP) { 462 if (vsu_mode == SCALE_UP_BIL) 463 val = GET_SCL_FT_BILI_UP(src, dst); 464 else 465 val = GET_SCL_FT_BIC(src, dst); 466 } else if (mode == SCALE_DOWN) { 467 if (vskiplines) { 468 *vskiplines = scl_get_vskiplines(src, dst); 469 val = scl_get_bili_dn_vskip(src, dst, 470 *vskiplines); 471 } else { 472 val = GET_SCL_FT_BILI_DN(src, dst); 473 } 474 } 475 } 476 477 return val; 478 } 479 480 static void scl_vop_cal_scl_fac(struct vop *vop, 481 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 482 uint32_t dst_h, uint32_t pixel_format) 483 { 484 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 485 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 486 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 487 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 488 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 489 bool is_yuv = false; 490 uint16_t cbcr_src_w = src_w / hsub; 491 uint16_t cbcr_src_h = src_h / vsub; 492 uint16_t vsu_mode; 493 uint16_t lb_mode; 494 uint32_t val; 495 int vskiplines = 0; 496 497 if (!vop->win->scl) 498 return; 499 500 if (dst_w > vop->max_output.width) { 501 printf("Maximum destination width %d exceeded\n", 502 vop->max_output.width); 503 return; 504 } 505 506 if (!vop->win->scl->ext) { 507 VOP_SCL_SET(vop, scale_yrgb_x, 508 scl_cal_scale2(src_w, dst_w)); 509 VOP_SCL_SET(vop, scale_yrgb_y, 510 scl_cal_scale2(src_h, dst_h)); 511 if (is_yuv) { 512 VOP_SCL_SET(vop, scale_cbcr_x, 513 scl_cal_scale2(src_w, dst_w)); 514 VOP_SCL_SET(vop, scale_cbcr_y, 515 scl_cal_scale2(src_h, dst_h)); 516 } 517 return; 518 } 519 520 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 521 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 522 523 if (is_yuv) { 524 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 525 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 526 if (cbcr_hor_scl_mode == SCALE_DOWN) 527 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 528 else 529 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 530 } else { 531 if (yrgb_hor_scl_mode == SCALE_DOWN) 532 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 533 else 534 lb_mode = scl_vop_cal_lb_mode(src_w, false); 535 } 536 537 VOP_SCL_SET_EXT(vop, lb_mode, lb_mode); 538 if (lb_mode == LB_RGB_3840X2) { 539 if (yrgb_ver_scl_mode != SCALE_NONE) { 540 printf("ERROR : not allow yrgb ver scale\n"); 541 return; 542 } 543 if (cbcr_ver_scl_mode != SCALE_NONE) { 544 printf("ERROR : not allow cbcr ver scale\n"); 545 return; 546 } 547 vsu_mode = SCALE_UP_BIL; 548 } else if (lb_mode == LB_RGB_2560X4) { 549 vsu_mode = SCALE_UP_BIL; 550 } else { 551 vsu_mode = SCALE_UP_BIC; 552 } 553 554 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 555 true, 0, NULL); 556 VOP_SCL_SET(vop, scale_yrgb_x, val); 557 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 558 false, vsu_mode, &vskiplines); 559 VOP_SCL_SET(vop, scale_yrgb_y, val); 560 561 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt4, vskiplines == 4); 562 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt2, vskiplines == 2); 563 564 VOP_SCL_SET_EXT(vop, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 565 VOP_SCL_SET_EXT(vop, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 566 VOP_SCL_SET_EXT(vop, yrgb_hsd_mode, SCALE_DOWN_BIL); 567 VOP_SCL_SET_EXT(vop, yrgb_vsd_mode, SCALE_DOWN_BIL); 568 VOP_SCL_SET_EXT(vop, yrgb_vsu_mode, vsu_mode); 569 if (is_yuv) { 570 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 571 dst_w, true, 0, NULL); 572 VOP_SCL_SET(vop, scale_cbcr_x, val); 573 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 574 dst_h, false, vsu_mode, &vskiplines); 575 VOP_SCL_SET(vop, scale_cbcr_y, val); 576 577 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt4, vskiplines == 4); 578 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt2, vskiplines == 2); 579 VOP_SCL_SET_EXT(vop, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 580 VOP_SCL_SET_EXT(vop, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 581 VOP_SCL_SET_EXT(vop, cbcr_hsd_mode, SCALE_DOWN_BIL); 582 VOP_SCL_SET_EXT(vop, cbcr_vsd_mode, SCALE_DOWN_BIL); 583 VOP_SCL_SET_EXT(vop, cbcr_vsu_mode, vsu_mode); 584 } 585 } 586 587 static int rockchip_vop_set_plane(struct display_state *state) 588 { 589 struct crtc_state *crtc_state = &state->crtc_state; 590 struct connector_state *conn_state = &state->conn_state; 591 struct drm_display_mode *mode = &conn_state->mode; 592 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 593 struct vop *vop = crtc_state->private; 594 int src_w = crtc_state->src_w; 595 int src_h = crtc_state->src_h; 596 int crtc_x = crtc_state->crtc_x; 597 int crtc_y = crtc_state->crtc_y; 598 int crtc_w = crtc_state->crtc_w; 599 int crtc_h = crtc_state->crtc_h; 600 int xvir = crtc_state->xvir; 601 602 act_info = (src_h - 1) << 16; 603 act_info |= (src_w - 1) & 0xffff; 604 605 dsp_info = (crtc_h - 1) << 16; 606 dsp_info |= (crtc_w - 1) & 0xffff; 607 608 dsp_stx = crtc_x + mode->htotal - mode->hsync_start; 609 dsp_sty = crtc_y + mode->vtotal - mode->vsync_start; 610 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 611 612 if (crtc_state->ymirror) { 613 if (VOP_WIN_SUPPORT(vop, vop->win, ymirror)) 614 crtc_state->dma_addr += (src_h - 1) * xvir * 4; 615 else 616 crtc_state->ymirror = 0; 617 } 618 VOP_WIN_SET(vop, ymirror, crtc_state->ymirror); 619 VOP_WIN_SET(vop, format, crtc_state->format); 620 VOP_WIN_SET(vop, yrgb_vir, xvir); 621 VOP_WIN_SET(vop, yrgb_mst, crtc_state->dma_addr); 622 623 scl_vop_cal_scl_fac(vop, src_w, src_h, crtc_w, crtc_h, 624 crtc_state->format); 625 626 VOP_WIN_SET(vop, act_info, act_info); 627 VOP_WIN_SET(vop, dsp_info, dsp_info); 628 VOP_WIN_SET(vop, dsp_st, dsp_st); 629 VOP_WIN_SET(vop, rb_swap, crtc_state->rb_swap); 630 631 VOP_WIN_SET(vop, src_alpha_ctl, 0); 632 633 VOP_WIN_SET(vop, enable, 1); 634 vop_cfg_done(vop); 635 636 return 0; 637 } 638 639 static int rockchip_vop_prepare(struct display_state *state) 640 { 641 return 0; 642 } 643 644 static int rockchip_vop_enable(struct display_state *state) 645 { 646 struct crtc_state *crtc_state = &state->crtc_state; 647 struct vop *vop = crtc_state->private; 648 649 VOP_CTRL_SET(vop, standby, 0); 650 vop_cfg_done(vop); 651 if (crtc_state->mcu_timing.mcu_pix_total > 0) 652 VOP_CTRL_SET(vop, mcu_hold_mode, 0); 653 654 return 0; 655 } 656 657 static int rockchip_vop_disable(struct display_state *state) 658 { 659 struct crtc_state *crtc_state = &state->crtc_state; 660 struct vop *vop = crtc_state->private; 661 662 VOP_CTRL_SET(vop, standby, 1); 663 vop_cfg_done(vop); 664 return 0; 665 } 666 667 static int rockchip_vop_fixup_dts(struct display_state *state, void *blob) 668 { 669 #if 0 670 struct crtc_state *crtc_state = &state->crtc_state; 671 struct panel_state *pstate = &state->panel_state; 672 uint32_t phandle; 673 char path[100]; 674 int ret, dsp_lut_node; 675 676 if (!ofnode_valid(pstate->dsp_lut_node)) 677 return 0; 678 ret = fdt_get_path(state->blob, pstate->dsp_lut_node, path, sizeof(path)); 679 if (ret < 0) { 680 printf("failed to get dsp_lut path[%s], ret=%d\n", 681 path, ret); 682 return ret; 683 } 684 685 dsp_lut_node = fdt_path_offset(blob, path); 686 phandle = fdt_get_phandle(blob, dsp_lut_node); 687 if (!phandle) { 688 phandle = fdt_alloc_phandle(blob); 689 if (!phandle) { 690 printf("failed to alloc phandle\n"); 691 return -ENOMEM; 692 } 693 694 fdt_set_phandle(blob, dsp_lut_node, phandle); 695 } 696 697 ret = fdt_get_path(state->blob, crtc_state->node, path, sizeof(path)); 698 if (ret < 0) { 699 printf("failed to get route path[%s], ret=%d\n", 700 path, ret); 701 return ret; 702 } 703 704 do_fixup_by_path_u32(blob, path, "dsp-lut", phandle, 1); 705 #endif 706 return 0; 707 } 708 709 static int rockchip_vop_send_mcu_cmd(struct display_state *state, 710 u32 type, u32 value) 711 { 712 struct crtc_state *crtc_state = &state->crtc_state; 713 struct vop *vop = crtc_state->private; 714 715 if (vop) { 716 switch (type) { 717 case MCU_WRCMD: 718 VOP_CTRL_SET(vop, mcu_rs, 0); 719 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value); 720 VOP_CTRL_SET(vop, mcu_rs, 1); 721 break; 722 case MCU_WRDATA: 723 VOP_CTRL_SET(vop, mcu_rs, 1); 724 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value); 725 break; 726 case MCU_SETBYPASS: 727 VOP_CTRL_SET(vop, mcu_bypass, value ? 1 : 0); 728 break; 729 default: 730 break; 731 } 732 } 733 734 return 0; 735 } 736 737 const struct rockchip_crtc_funcs rockchip_vop_funcs = { 738 .init = rockchip_vop_init, 739 .set_plane = rockchip_vop_set_plane, 740 .prepare = rockchip_vop_prepare, 741 .enable = rockchip_vop_enable, 742 .disable = rockchip_vop_disable, 743 .fixup_dts = rockchip_vop_fixup_dts, 744 .send_mcu_cmd = rockchip_vop_send_mcu_cmd, 745 }; 746