1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <asm/io.h> 15 #include <linux/list.h> 16 #include <linux/media-bus-format.h> 17 #include <clk.h> 18 #include <asm/arch/clock.h> 19 #include <linux/err.h> 20 #include <dm/device.h> 21 #include <dm/read.h> 22 23 #include "rockchip_display.h" 24 #include "rockchip_crtc.h" 25 #include "rockchip_connector.h" 26 #include "rockchip_vop.h" 27 28 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 29 { 30 return us * mode->clock / mode->htotal / 1000; 31 } 32 33 static int to_vop_csc_mode(int csc_mode) 34 { 35 switch (csc_mode) { 36 case V4L2_COLORSPACE_SMPTE170M: 37 return CSC_BT601L; 38 case V4L2_COLORSPACE_REC709: 39 case V4L2_COLORSPACE_DEFAULT: 40 return CSC_BT709L; 41 case V4L2_COLORSPACE_JPEG: 42 return CSC_BT601F; 43 case V4L2_COLORSPACE_BT2020: 44 return CSC_BT2020; 45 default: 46 return CSC_BT709L; 47 } 48 } 49 50 static bool is_yuv_output(uint32_t bus_format) 51 { 52 switch (bus_format) { 53 case MEDIA_BUS_FMT_YUV8_1X24: 54 case MEDIA_BUS_FMT_YUV10_1X30: 55 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 56 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 57 return true; 58 default: 59 return false; 60 } 61 } 62 63 static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode) 64 { 65 /* 66 * FIXME: 67 * 68 * There is no media type for YUV444 output, 69 * so when out_mode is AAAA or P888, assume output is YUV444 on 70 * yuv format. 71 * 72 * From H/W testing, YUV444 mode need a rb swap. 73 */ 74 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 75 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 76 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 77 output_mode == ROCKCHIP_OUT_MODE_P888)) 78 return true; 79 else 80 return false; 81 } 82 83 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) 84 { 85 struct crtc_state *crtc_state = &state->crtc_state; 86 struct connector_state *conn_state = &state->conn_state; 87 u32 *lut = conn_state->gamma.lut; 88 fdt_size_t lut_size; 89 int i, lut_len; 90 u32 *lut_regs; 91 92 if (!conn_state->gamma.lut) 93 return 0; 94 95 i = dev_read_stringlist_search(crtc_state->dev, "reg-names", "gamma_lut"); 96 if (i < 0) { 97 printf("Warning: vop not support gamma\n"); 98 return 0; 99 } 100 lut_regs = (u32 *)dev_read_addr_size(crtc_state->dev, "reg", &lut_size); 101 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 102 printf("failed to get gamma lut register\n"); 103 return 0; 104 } 105 lut_len = lut_size / 4; 106 if (lut_len != 256 && lut_len != 1024) { 107 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 108 return 0; 109 } 110 111 if (conn_state->gamma.size != lut_len) { 112 int size = conn_state->gamma.size; 113 u32 j, r, g, b, color; 114 115 for (i = 0; i < lut_len; i++) { 116 j = i * size / lut_len; 117 r = lut[j] / size / size * lut_len / size; 118 g = lut[j] / size % size * lut_len / size; 119 b = lut[j] % size * lut_len / size; 120 color = r * lut_len * lut_len + g * lut_len + b; 121 122 writel(color, lut_regs + (i << 2)); 123 } 124 } else { 125 for (i = 0; i < lut_len; i++) 126 writel(lut[i], lut_regs + (i << 2)); 127 } 128 129 VOP_CTRL_SET(vop, dsp_lut_en, 1); 130 VOP_CTRL_SET(vop, update_gamma_lut, 1); 131 132 return 0; 133 } 134 135 static int rockchip_vop_init(struct display_state *state) 136 { 137 struct crtc_state *crtc_state = &state->crtc_state; 138 struct connector_state *conn_state = &state->conn_state; 139 struct drm_display_mode *mode = &conn_state->mode; 140 const struct rockchip_crtc *crtc = crtc_state->crtc; 141 const struct vop_data *vop_data = crtc->data; 142 struct vop *vop; 143 u16 hsync_len = mode->hsync_end - mode->hsync_start; 144 u16 hdisplay = mode->hdisplay; 145 u16 htotal = mode->htotal; 146 u16 hact_st = mode->htotal - mode->hsync_start; 147 u16 hact_end = hact_st + hdisplay; 148 u16 vdisplay = mode->vdisplay; 149 u16 vtotal = mode->vtotal; 150 u16 vsync_len = mode->vsync_end - mode->vsync_start; 151 u16 vact_st = mode->vtotal - mode->vsync_start; 152 u16 vact_end = vact_st + vdisplay; 153 struct clk dclk, aclk; 154 u32 val; 155 int ret; 156 bool yuv_overlay = false, post_r2y_en = false, post_y2r_en = false; 157 u16 post_csc_mode; 158 159 vop = malloc(sizeof(*vop)); 160 if (!vop) 161 return -ENOMEM; 162 memset(vop, 0, sizeof(*vop)); 163 164 crtc_state->private = vop; 165 vop->regs = dev_read_addr_ptr(crtc_state->dev); 166 vop->regsbak = malloc(vop_data->reg_len); 167 vop->win = vop_data->win; 168 vop->win_offset = vop_data->win_offset; 169 vop->ctrl = vop_data->ctrl; 170 vop->line_flag = vop_data->line_flag; 171 vop->version = vop_data->version; 172 173 /* 174 * TODO: 175 * Set Dclk pll parent 176 */ 177 178 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &dclk); 179 if (!ret) 180 ret = clk_set_rate(&dclk, mode->clock * 1000); 181 if (IS_ERR_VALUE(ret)) { 182 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret); 183 return ret; 184 } 185 186 ret = clk_get_by_name(crtc_state->dev, "aclk_vop", &aclk); 187 if (!ret) 188 ret = clk_set_rate(&aclk, 400 * 1000 * 1000); 189 if (IS_ERR_VALUE(ret)) 190 printf("%s: Failed to set aclk: ret=%d\n", __func__, ret); 191 192 memcpy(vop->regsbak, vop->regs, vop_data->reg_len); 193 194 rockchip_vop_init_gamma(vop, state); 195 196 VOP_CTRL_SET(vop, global_regdone_en, 1); 197 VOP_CTRL_SET(vop, win_gate[0], 1); 198 VOP_CTRL_SET(vop, win_gate[1], 1); 199 VOP_CTRL_SET(vop, dsp_blank, 0); 200 201 val = 0x8; 202 val |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 203 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 204 VOP_CTRL_SET(vop, pin_pol, val); 205 206 switch (conn_state->type) { 207 case DRM_MODE_CONNECTOR_LVDS: 208 VOP_CTRL_SET(vop, rgb_en, 1); 209 VOP_CTRL_SET(vop, rgb_pin_pol, val); 210 break; 211 case DRM_MODE_CONNECTOR_eDP: 212 VOP_CTRL_SET(vop, edp_en, 1); 213 VOP_CTRL_SET(vop, edp_pin_pol, val); 214 break; 215 case DRM_MODE_CONNECTOR_HDMIA: 216 VOP_CTRL_SET(vop, hdmi_en, 1); 217 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 218 break; 219 case DRM_MODE_CONNECTOR_DSI: 220 VOP_CTRL_SET(vop, mipi_en, 1); 221 VOP_CTRL_SET(vop, mipi_pin_pol, val); 222 VOP_CTRL_SET(vop, mipi_dual_channel_en, 223 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL)); 224 VOP_CTRL_SET(vop, data01_swap, 225 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_LINK)); 226 break; 227 default: 228 printf("unsupport connector_type[%d]\n", conn_state->type); 229 } 230 231 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 232 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 233 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 234 235 switch (conn_state->bus_format) { 236 case MEDIA_BUS_FMT_RGB565_1X16: 237 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565); 238 break; 239 case MEDIA_BUS_FMT_RGB666_1X18: 240 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 241 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666); 242 break; 243 case MEDIA_BUS_FMT_YUV8_1X24: 244 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 245 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1); 246 break; 247 case MEDIA_BUS_FMT_YUV10_1X30: 248 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 249 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 250 break; 251 case MEDIA_BUS_FMT_RGB888_1X24: 252 default: 253 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 254 break; 255 } 256 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 257 val |= PRE_DITHER_DOWN_EN(0); 258 else 259 val |= PRE_DITHER_DOWN_EN(1); 260 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO); 261 VOP_CTRL_SET(vop, dither_down, val); 262 263 VOP_CTRL_SET(vop, dclk_ddr, 264 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 265 VOP_CTRL_SET(vop, hdmi_dclk_out_en, 266 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 267 268 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 269 VOP_CTRL_SET(vop, dsp_data_swap, DSP_RB_SWAP); 270 else 271 VOP_CTRL_SET(vop, dsp_data_swap, 0); 272 273 VOP_CTRL_SET(vop, out_mode, conn_state->output_mode); 274 275 if (VOP_CTRL_SUPPORT(vop, overlay_mode)) { 276 yuv_overlay = is_yuv_output(conn_state->bus_format); 277 VOP_CTRL_SET(vop, overlay_mode, yuv_overlay); 278 } 279 /* 280 * todo: r2y for win csc 281 */ 282 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(conn_state->bus_format)); 283 284 if (yuv_overlay) { 285 if (!is_yuv_output(conn_state->bus_format)) 286 post_y2r_en = true; 287 } else { 288 if (is_yuv_output(conn_state->bus_format)) 289 post_r2y_en = true; 290 } 291 292 post_csc_mode = to_vop_csc_mode(conn_state->color_space); 293 VOP_CTRL_SET(vop, bcsh_r2y_en, post_r2y_en); 294 VOP_CTRL_SET(vop, bcsh_y2r_en, post_y2r_en); 295 VOP_CTRL_SET(vop, bcsh_r2y_csc_mode, post_csc_mode); 296 VOP_CTRL_SET(vop, bcsh_y2r_csc_mode, post_csc_mode); 297 298 /* 299 * Background color is 10bit depth if vop version >= 3.5 300 */ 301 if (!is_yuv_output(conn_state->bus_format)) 302 val = 0; 303 else if (VOP_MAJOR(vop->version) == 3 && 304 VOP_MINOR(vop->version) >= 5) 305 val = 0x20010200; 306 else 307 val = 0x801080; 308 VOP_CTRL_SET(vop, dsp_background, val); 309 310 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 311 val = hact_st << 16; 312 val |= hact_end; 313 VOP_CTRL_SET(vop, hact_st_end, val); 314 VOP_CTRL_SET(vop, hpost_st_end, val); 315 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 316 val = vact_st << 16; 317 val |= vact_end; 318 VOP_CTRL_SET(vop, vact_st_end, val); 319 VOP_CTRL_SET(vop, vpost_st_end, val); 320 VOP_CTRL_SET(vop, standby, 1); 321 VOP_LINE_FLAG_SET(vop, line_flag_num[0], vact_end - 3); 322 VOP_LINE_FLAG_SET(vop, line_flag_num[1], 323 vact_end - us_to_vertical_line(mode, 1000)); 324 vop_cfg_done(vop); 325 326 return 0; 327 } 328 329 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 330 uint32_t dst, bool is_horizontal, 331 int vsu_mode, int *vskiplines) 332 { 333 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 334 335 if (is_horizontal) { 336 if (mode == SCALE_UP) 337 val = GET_SCL_FT_BIC(src, dst); 338 else if (mode == SCALE_DOWN) 339 val = GET_SCL_FT_BILI_DN(src, dst); 340 } else { 341 if (mode == SCALE_UP) { 342 if (vsu_mode == SCALE_UP_BIL) 343 val = GET_SCL_FT_BILI_UP(src, dst); 344 else 345 val = GET_SCL_FT_BIC(src, dst); 346 } else if (mode == SCALE_DOWN) { 347 if (vskiplines) { 348 *vskiplines = scl_get_vskiplines(src, dst); 349 val = scl_get_bili_dn_vskip(src, dst, 350 *vskiplines); 351 } else { 352 val = GET_SCL_FT_BILI_DN(src, dst); 353 } 354 } 355 } 356 357 return val; 358 } 359 360 static void scl_vop_cal_scl_fac(struct vop *vop, 361 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 362 uint32_t dst_h, uint32_t pixel_format) 363 { 364 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 365 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 366 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 367 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 368 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 369 bool is_yuv = false; 370 uint16_t cbcr_src_w = src_w / hsub; 371 uint16_t cbcr_src_h = src_h / vsub; 372 uint16_t vsu_mode; 373 uint16_t lb_mode; 374 uint32_t val; 375 int vskiplines = 0; 376 377 if (!vop->win->scl) 378 return; 379 380 if (dst_w > 3840) { 381 printf("Maximum destination width (3840) exceeded\n"); 382 return; 383 } 384 385 if (!vop->win->scl->ext) { 386 VOP_SCL_SET(vop, scale_yrgb_x, 387 scl_cal_scale2(src_w, dst_w)); 388 VOP_SCL_SET(vop, scale_yrgb_y, 389 scl_cal_scale2(src_h, dst_h)); 390 if (is_yuv) { 391 VOP_SCL_SET(vop, scale_cbcr_x, 392 scl_cal_scale2(src_w, dst_w)); 393 VOP_SCL_SET(vop, scale_cbcr_y, 394 scl_cal_scale2(src_h, dst_h)); 395 } 396 return; 397 } 398 399 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 400 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 401 402 if (is_yuv) { 403 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 404 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 405 if (cbcr_hor_scl_mode == SCALE_DOWN) 406 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 407 else 408 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 409 } else { 410 if (yrgb_hor_scl_mode == SCALE_DOWN) 411 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 412 else 413 lb_mode = scl_vop_cal_lb_mode(src_w, false); 414 } 415 416 VOP_SCL_SET_EXT(vop, lb_mode, lb_mode); 417 if (lb_mode == LB_RGB_3840X2) { 418 if (yrgb_ver_scl_mode != SCALE_NONE) { 419 printf("ERROR : not allow yrgb ver scale\n"); 420 return; 421 } 422 if (cbcr_ver_scl_mode != SCALE_NONE) { 423 printf("ERROR : not allow cbcr ver scale\n"); 424 return; 425 } 426 vsu_mode = SCALE_UP_BIL; 427 } else if (lb_mode == LB_RGB_2560X4) { 428 vsu_mode = SCALE_UP_BIL; 429 } else { 430 vsu_mode = SCALE_UP_BIC; 431 } 432 433 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 434 true, 0, NULL); 435 VOP_SCL_SET(vop, scale_yrgb_x, val); 436 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 437 false, vsu_mode, &vskiplines); 438 VOP_SCL_SET(vop, scale_yrgb_y, val); 439 440 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt4, vskiplines == 4); 441 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt2, vskiplines == 2); 442 443 VOP_SCL_SET_EXT(vop, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 444 VOP_SCL_SET_EXT(vop, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 445 VOP_SCL_SET_EXT(vop, yrgb_hsd_mode, SCALE_DOWN_BIL); 446 VOP_SCL_SET_EXT(vop, yrgb_vsd_mode, SCALE_DOWN_BIL); 447 VOP_SCL_SET_EXT(vop, yrgb_vsu_mode, vsu_mode); 448 if (is_yuv) { 449 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 450 dst_w, true, 0, NULL); 451 VOP_SCL_SET(vop, scale_cbcr_x, val); 452 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 453 dst_h, false, vsu_mode, &vskiplines); 454 VOP_SCL_SET(vop, scale_cbcr_y, val); 455 456 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt4, vskiplines == 4); 457 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt2, vskiplines == 2); 458 VOP_SCL_SET_EXT(vop, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 459 VOP_SCL_SET_EXT(vop, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 460 VOP_SCL_SET_EXT(vop, cbcr_hsd_mode, SCALE_DOWN_BIL); 461 VOP_SCL_SET_EXT(vop, cbcr_vsd_mode, SCALE_DOWN_BIL); 462 VOP_SCL_SET_EXT(vop, cbcr_vsu_mode, vsu_mode); 463 } 464 } 465 466 static int rockchip_vop_set_plane(struct display_state *state) 467 { 468 struct crtc_state *crtc_state = &state->crtc_state; 469 struct connector_state *conn_state = &state->conn_state; 470 struct drm_display_mode *mode = &conn_state->mode; 471 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 472 struct vop *vop = crtc_state->private; 473 int src_w = crtc_state->src_w; 474 int src_h = crtc_state->src_h; 475 int crtc_x = crtc_state->crtc_x; 476 int crtc_y = crtc_state->crtc_y; 477 int crtc_w = crtc_state->crtc_w; 478 int crtc_h = crtc_state->crtc_h; 479 int xvir = crtc_state->xvir; 480 481 act_info = (src_h - 1) << 16; 482 act_info |= (src_w - 1) & 0xffff; 483 484 dsp_info = (crtc_h - 1) << 16; 485 dsp_info |= (crtc_w - 1) & 0xffff; 486 487 dsp_stx = crtc_x + mode->htotal - mode->hsync_start; 488 dsp_sty = crtc_y + mode->vtotal - mode->vsync_start; 489 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 490 491 if (crtc_state->ymirror) 492 crtc_state->dma_addr += (src_h - 1) * xvir * 4; 493 VOP_WIN_SET(vop, ymirror, crtc_state->ymirror); 494 VOP_WIN_SET(vop, format, crtc_state->format); 495 VOP_WIN_SET(vop, yrgb_vir, xvir); 496 VOP_WIN_SET(vop, yrgb_mst, crtc_state->dma_addr); 497 498 scl_vop_cal_scl_fac(vop, src_w, src_h, crtc_w, crtc_h, 499 crtc_state->format); 500 501 VOP_WIN_SET(vop, act_info, act_info); 502 VOP_WIN_SET(vop, dsp_info, dsp_info); 503 VOP_WIN_SET(vop, dsp_st, dsp_st); 504 VOP_WIN_SET(vop, rb_swap, crtc_state->rb_swap); 505 506 VOP_WIN_SET(vop, src_alpha_ctl, 0); 507 508 VOP_WIN_SET(vop, enable, 1); 509 vop_cfg_done(vop); 510 511 return 0; 512 } 513 514 static int rockchip_vop_prepare(struct display_state *state) 515 { 516 return 0; 517 } 518 519 static int rockchip_vop_enable(struct display_state *state) 520 { 521 struct crtc_state *crtc_state = &state->crtc_state; 522 struct vop *vop = crtc_state->private; 523 524 VOP_CTRL_SET(vop, standby, 0); 525 vop_cfg_done(vop); 526 527 return 0; 528 } 529 530 static int rockchip_vop_disable(struct display_state *state) 531 { 532 struct crtc_state *crtc_state = &state->crtc_state; 533 struct vop *vop = crtc_state->private; 534 535 VOP_CTRL_SET(vop, standby, 1); 536 vop_cfg_done(vop); 537 return 0; 538 } 539 540 static int rockchip_vop_fixup_dts(struct display_state *state, void *blob) 541 { 542 #if 0 543 struct crtc_state *crtc_state = &state->crtc_state; 544 struct panel_state *pstate = &state->panel_state; 545 uint32_t phandle; 546 char path[100]; 547 int ret, dsp_lut_node; 548 549 if (!ofnode_valid(pstate->dsp_lut_node)) 550 return 0; 551 ret = fdt_get_path(state->blob, pstate->dsp_lut_node, path, sizeof(path)); 552 if (ret < 0) { 553 printf("failed to get dsp_lut path[%s], ret=%d\n", 554 path, ret); 555 return ret; 556 } 557 558 dsp_lut_node = fdt_path_offset(blob, path); 559 phandle = fdt_get_phandle(blob, dsp_lut_node); 560 if (!phandle) { 561 phandle = fdt_alloc_phandle(blob); 562 if (!phandle) { 563 printf("failed to alloc phandle\n"); 564 return -ENOMEM; 565 } 566 567 fdt_set_phandle(blob, dsp_lut_node, phandle); 568 } 569 570 ret = fdt_get_path(state->blob, crtc_state->node, path, sizeof(path)); 571 if (ret < 0) { 572 printf("failed to get route path[%s], ret=%d\n", 573 path, ret); 574 return ret; 575 } 576 577 do_fixup_by_path_u32(blob, path, "dsp-lut", phandle, 1); 578 #endif 579 return 0; 580 } 581 582 const struct rockchip_crtc_funcs rockchip_vop_funcs = { 583 .init = rockchip_vop_init, 584 .set_plane = rockchip_vop_set_plane, 585 .prepare = rockchip_vop_prepare, 586 .enable = rockchip_vop_enable, 587 .disable = rockchip_vop_disable, 588 .fixup_dts = rockchip_vop_fixup_dts, 589 }; 590