1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <asm/io.h> 15 #include <linux/list.h> 16 #include <linux/media-bus-format.h> 17 #include <clk.h> 18 #include <asm/arch/clock.h> 19 #include <linux/err.h> 20 #include <dm/device.h> 21 #include <dm/read.h> 22 #include <syscon.h> 23 24 #include "rockchip_display.h" 25 #include "rockchip_crtc.h" 26 #include "rockchip_connector.h" 27 #include "rockchip_vop.h" 28 29 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 30 { 31 return us * mode->clock / mode->htotal / 1000; 32 } 33 34 static int to_vop_csc_mode(int csc_mode) 35 { 36 switch (csc_mode) { 37 case V4L2_COLORSPACE_SMPTE170M: 38 return CSC_BT601L; 39 case V4L2_COLORSPACE_REC709: 40 case V4L2_COLORSPACE_DEFAULT: 41 return CSC_BT709L; 42 case V4L2_COLORSPACE_JPEG: 43 return CSC_BT601F; 44 case V4L2_COLORSPACE_BT2020: 45 return CSC_BT2020; 46 default: 47 return CSC_BT709L; 48 } 49 } 50 51 static bool is_yuv_output(uint32_t bus_format) 52 { 53 switch (bus_format) { 54 case MEDIA_BUS_FMT_YUV8_1X24: 55 case MEDIA_BUS_FMT_YUV10_1X30: 56 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 57 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 58 return true; 59 default: 60 return false; 61 } 62 } 63 64 static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode) 65 { 66 /* 67 * FIXME: 68 * 69 * There is no media type for YUV444 output, 70 * so when out_mode is AAAA or P888, assume output is YUV444 on 71 * yuv format. 72 * 73 * From H/W testing, YUV444 mode need a rb swap. 74 */ 75 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 76 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 77 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 78 output_mode == ROCKCHIP_OUT_MODE_P888)) 79 return true; 80 else 81 return false; 82 } 83 84 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) 85 { 86 struct crtc_state *crtc_state = &state->crtc_state; 87 struct connector_state *conn_state = &state->conn_state; 88 u32 *lut = conn_state->gamma.lut; 89 fdt_size_t lut_size; 90 int i, lut_len; 91 u32 *lut_regs; 92 93 if (!conn_state->gamma.lut) 94 return 0; 95 96 i = dev_read_stringlist_search(crtc_state->dev, "reg-names", "gamma_lut"); 97 if (i < 0) { 98 printf("Warning: vop not support gamma\n"); 99 return 0; 100 } 101 lut_regs = (u32 *)dev_read_addr_size(crtc_state->dev, "reg", &lut_size); 102 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 103 printf("failed to get gamma lut register\n"); 104 return 0; 105 } 106 lut_len = lut_size / 4; 107 if (lut_len != 256 && lut_len != 1024) { 108 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 109 return 0; 110 } 111 112 if (conn_state->gamma.size != lut_len) { 113 int size = conn_state->gamma.size; 114 u32 j, r, g, b, color; 115 116 for (i = 0; i < lut_len; i++) { 117 j = i * size / lut_len; 118 r = lut[j] / size / size * lut_len / size; 119 g = lut[j] / size % size * lut_len / size; 120 b = lut[j] % size * lut_len / size; 121 color = r * lut_len * lut_len + g * lut_len + b; 122 123 writel(color, lut_regs + (i << 2)); 124 } 125 } else { 126 for (i = 0; i < lut_len; i++) 127 writel(lut[i], lut_regs + (i << 2)); 128 } 129 130 VOP_CTRL_SET(vop, dsp_lut_en, 1); 131 VOP_CTRL_SET(vop, update_gamma_lut, 1); 132 133 return 0; 134 } 135 136 static void vop_post_config(struct display_state *state, struct vop *vop) 137 { 138 struct connector_state *conn_state = &state->conn_state; 139 struct drm_display_mode *mode = &conn_state->mode; 140 u16 vtotal = mode->crtc_vtotal; 141 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 142 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 143 u16 hdisplay = mode->crtc_hdisplay; 144 u16 vdisplay = mode->crtc_vdisplay; 145 u16 hsize = hdisplay * (conn_state->overscan.left_margin + conn_state->overscan.right_margin) / 200; 146 u16 vsize = vdisplay * (conn_state->overscan.top_margin + conn_state->overscan.bottom_margin) / 200; 147 u16 hact_end, vact_end; 148 u32 val; 149 150 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 151 vsize = round_down(vsize, 2); 152 153 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 154 hact_end = hact_st + hsize; 155 val = hact_st << 16; 156 val |= hact_end; 157 158 VOP_CTRL_SET(vop, hpost_st_end, val); 159 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 160 vact_end = vact_st + vsize; 161 val = vact_st << 16; 162 val |= vact_end; 163 VOP_CTRL_SET(vop, vpost_st_end, val); 164 val = scl_cal_scale2(vdisplay, vsize) << 16; 165 val |= scl_cal_scale2(hdisplay, hsize); 166 VOP_CTRL_SET(vop, post_scl_factor, val); 167 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 168 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 169 VOP_CTRL_SET(vop, post_scl_ctrl, 170 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 171 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 172 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 173 u16 vact_st_f1 = vtotal + vact_st + 1; 174 u16 vact_end_f1 = vact_st_f1 + vsize; 175 176 val = vact_st_f1 << 16 | vact_end_f1; 177 VOP_CTRL_SET(vop, vpost_st_end_f1, val); 178 } 179 } 180 181 static void vop_mcu_mode(struct display_state *state, struct vop *vop) 182 { 183 struct crtc_state *crtc_state = &state->crtc_state; 184 185 VOP_CTRL_SET(vop, mcu_clk_sel, 1); 186 VOP_CTRL_SET(vop, mcu_type, 1); 187 188 VOP_CTRL_SET(vop, mcu_hold_mode, 1); 189 VOP_CTRL_SET(vop, mcu_pix_total, crtc_state->mcu_timing.mcu_pix_total); 190 VOP_CTRL_SET(vop, mcu_cs_pst, crtc_state->mcu_timing.mcu_cs_pst); 191 VOP_CTRL_SET(vop, mcu_cs_pend, crtc_state->mcu_timing.mcu_cs_pend); 192 VOP_CTRL_SET(vop, mcu_rw_pst, crtc_state->mcu_timing.mcu_rw_pst); 193 VOP_CTRL_SET(vop, mcu_rw_pend, crtc_state->mcu_timing.mcu_rw_pend); 194 } 195 196 static int rockchip_vop_init(struct display_state *state) 197 { 198 struct crtc_state *crtc_state = &state->crtc_state; 199 struct connector_state *conn_state = &state->conn_state; 200 struct drm_display_mode *mode = &conn_state->mode; 201 const struct rockchip_crtc *crtc = crtc_state->crtc; 202 const struct vop_data *vop_data = crtc->data; 203 struct vop *vop; 204 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 205 u16 hdisplay = mode->crtc_hdisplay; 206 u16 htotal = mode->crtc_htotal; 207 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 208 u16 hact_end = hact_st + hdisplay; 209 u16 vdisplay = mode->crtc_vdisplay; 210 u16 vtotal = mode->crtc_vtotal; 211 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 212 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 213 u16 vact_end = vact_st + vdisplay; 214 struct clk dclk; 215 u32 val, act_end; 216 int ret; 217 bool yuv_overlay = false, post_r2y_en = false, post_y2r_en = false; 218 u16 post_csc_mode; 219 bool dclk_inv; 220 221 vop = malloc(sizeof(*vop)); 222 if (!vop) 223 return -ENOMEM; 224 memset(vop, 0, sizeof(*vop)); 225 226 crtc_state->private = vop; 227 vop->regs = dev_read_addr_ptr(crtc_state->dev); 228 vop->regsbak = malloc(vop_data->reg_len); 229 vop->win = vop_data->win; 230 vop->win_offset = vop_data->win_offset; 231 vop->ctrl = vop_data->ctrl; 232 vop->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 233 if (vop->grf <= 0) 234 printf("%s: Get syscon grf failed (ret=%p)\n", 235 __func__, vop->grf); 236 237 vop->grf_ctrl = vop_data->grf_ctrl; 238 vop->line_flag = vop_data->line_flag; 239 vop->csc_table = vop_data->csc_table; 240 vop->win_csc = vop_data->win_csc; 241 vop->version = vop_data->version; 242 vop->max_output = vop_data->max_output; 243 244 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 245 ret = clk_set_defaults(crtc_state->dev); 246 if (ret) 247 debug("%s clk_set_defaults failed %d\n", __func__, ret); 248 249 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &dclk); 250 if (!ret) 251 ret = clk_set_rate(&dclk, mode->clock * 1000); 252 if (IS_ERR_VALUE(ret)) { 253 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret); 254 return ret; 255 } 256 257 memcpy(vop->regsbak, vop->regs, vop_data->reg_len); 258 259 rockchip_vop_init_gamma(vop, state); 260 261 VOP_CTRL_SET(vop, global_regdone_en, 1); 262 VOP_CTRL_SET(vop, axi_outstanding_max_num, 30); 263 VOP_CTRL_SET(vop, axi_max_outstanding_en, 1); 264 VOP_CTRL_SET(vop, reg_done_frm, 1); 265 VOP_CTRL_SET(vop, win_gate[0], 1); 266 VOP_CTRL_SET(vop, win_gate[1], 1); 267 VOP_CTRL_SET(vop, win_channel[0], 0x12); 268 VOP_CTRL_SET(vop, win_channel[1], 0x34); 269 VOP_CTRL_SET(vop, win_channel[2], 0x56); 270 VOP_CTRL_SET(vop, dsp_blank, 0); 271 272 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 273 VOP_CTRL_SET(vop, dclk_pol, dclk_inv); 274 275 val = 0x8; 276 val |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 277 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 278 VOP_CTRL_SET(vop, pin_pol, val); 279 280 switch (conn_state->type) { 281 case DRM_MODE_CONNECTOR_LVDS: 282 VOP_CTRL_SET(vop, rgb_en, 1); 283 VOP_CTRL_SET(vop, rgb_pin_pol, val); 284 VOP_CTRL_SET(vop, rgb_dclk_pol, dclk_inv); 285 VOP_CTRL_SET(vop, lvds_en, 1); 286 VOP_CTRL_SET(vop, lvds_pin_pol, val); 287 VOP_CTRL_SET(vop, lvds_dclk_pol, dclk_inv); 288 if (!IS_ERR_OR_NULL(vop->grf)) 289 VOP_GRF_SET(vop, grf_dclk_inv, !dclk_inv); 290 break; 291 case DRM_MODE_CONNECTOR_eDP: 292 VOP_CTRL_SET(vop, edp_en, 1); 293 VOP_CTRL_SET(vop, edp_pin_pol, val); 294 VOP_CTRL_SET(vop, edp_dclk_pol, dclk_inv); 295 break; 296 case DRM_MODE_CONNECTOR_HDMIA: 297 VOP_CTRL_SET(vop, hdmi_en, 1); 298 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 299 VOP_CTRL_SET(vop, hdmi_dclk_pol, 1); 300 break; 301 case DRM_MODE_CONNECTOR_DSI: 302 VOP_CTRL_SET(vop, mipi_en, 1); 303 VOP_CTRL_SET(vop, mipi_pin_pol, val); 304 VOP_CTRL_SET(vop, mipi_dclk_pol, dclk_inv); 305 VOP_CTRL_SET(vop, mipi_dual_channel_en, 306 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL)); 307 VOP_CTRL_SET(vop, data01_swap, 308 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_LINK) || 309 crtc_state->dual_channel_swap); 310 break; 311 case DRM_MODE_CONNECTOR_DisplayPort: 312 VOP_CTRL_SET(vop, dp_dclk_pol, 0); 313 VOP_CTRL_SET(vop, dp_pin_pol, val); 314 VOP_CTRL_SET(vop, dp_en, 1); 315 break; 316 case DRM_MODE_CONNECTOR_TV: 317 if (vdisplay == CVBS_PAL_VDISPLAY) 318 VOP_CTRL_SET(vop, tve_sw_mode, 1); 319 else 320 VOP_CTRL_SET(vop, tve_sw_mode, 0); 321 VOP_CTRL_SET(vop, tve_dclk_pol, 1); 322 VOP_CTRL_SET(vop, tve_dclk_en, 1); 323 /* use the same pol reg with hdmi */ 324 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 325 VOP_CTRL_SET(vop, sw_genlock, 1); 326 VOP_CTRL_SET(vop, sw_uv_offset_en, 1); 327 VOP_CTRL_SET(vop, dither_up, 1); 328 break; 329 default: 330 printf("unsupport connector_type[%d]\n", conn_state->type); 331 } 332 333 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 334 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 335 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 336 337 switch (conn_state->bus_format) { 338 case MEDIA_BUS_FMT_RGB565_1X16: 339 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565); 340 break; 341 case MEDIA_BUS_FMT_RGB666_1X18: 342 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 343 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 344 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: 345 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666); 346 break; 347 case MEDIA_BUS_FMT_YUV8_1X24: 348 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 349 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1); 350 break; 351 case MEDIA_BUS_FMT_YUV10_1X30: 352 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 353 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 354 break; 355 case MEDIA_BUS_FMT_RGB888_1X24: 356 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 357 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 358 default: 359 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 360 break; 361 } 362 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 363 val |= PRE_DITHER_DOWN_EN(0); 364 else 365 val |= PRE_DITHER_DOWN_EN(1); 366 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO); 367 VOP_CTRL_SET(vop, dither_down, val); 368 369 VOP_CTRL_SET(vop, dclk_ddr, 370 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 371 VOP_CTRL_SET(vop, hdmi_dclk_out_en, 372 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 373 374 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 375 VOP_CTRL_SET(vop, dsp_data_swap, DSP_RB_SWAP); 376 else 377 VOP_CTRL_SET(vop, dsp_data_swap, 0); 378 379 VOP_CTRL_SET(vop, out_mode, conn_state->output_mode); 380 381 if (VOP_CTRL_SUPPORT(vop, overlay_mode)) { 382 yuv_overlay = is_yuv_output(conn_state->bus_format); 383 VOP_CTRL_SET(vop, overlay_mode, yuv_overlay); 384 } 385 /* 386 * todo: r2y for win csc 387 */ 388 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(conn_state->bus_format)); 389 390 if (yuv_overlay) { 391 if (!is_yuv_output(conn_state->bus_format)) 392 post_y2r_en = true; 393 } else { 394 if (is_yuv_output(conn_state->bus_format)) 395 post_r2y_en = true; 396 } 397 398 crtc_state->yuv_overlay = yuv_overlay; 399 post_csc_mode = to_vop_csc_mode(conn_state->color_space); 400 VOP_CTRL_SET(vop, bcsh_r2y_en, post_r2y_en); 401 VOP_CTRL_SET(vop, bcsh_y2r_en, post_y2r_en); 402 VOP_CTRL_SET(vop, bcsh_r2y_csc_mode, post_csc_mode); 403 VOP_CTRL_SET(vop, bcsh_y2r_csc_mode, post_csc_mode); 404 405 /* 406 * Background color is 10bit depth if vop version >= 3.5 407 */ 408 if (!is_yuv_output(conn_state->bus_format)) 409 val = 0; 410 else if (VOP_MAJOR(vop->version) == 3 && 411 VOP_MINOR(vop->version) >= 5) 412 val = 0x20010200; 413 else 414 val = 0x801080; 415 VOP_CTRL_SET(vop, dsp_background, val); 416 417 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 418 val = hact_st << 16; 419 val |= hact_end; 420 VOP_CTRL_SET(vop, hact_st_end, val); 421 val = vact_st << 16; 422 val |= vact_end; 423 VOP_CTRL_SET(vop, vact_st_end, val); 424 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 425 u16 vact_st_f1 = vtotal + vact_st + 1; 426 u16 vact_end_f1 = vact_st_f1 + vdisplay; 427 428 val = vact_st_f1 << 16 | vact_end_f1; 429 VOP_CTRL_SET(vop, vact_st_end_f1, val); 430 431 val = vtotal << 16 | (vtotal + vsync_len); 432 VOP_CTRL_SET(vop, vs_st_end_f1, val); 433 VOP_CTRL_SET(vop, dsp_interlace, 1); 434 VOP_CTRL_SET(vop, p2i_en, 1); 435 vtotal += vtotal + 1; 436 act_end = vact_end_f1; 437 } else { 438 VOP_CTRL_SET(vop, dsp_interlace, 0); 439 VOP_CTRL_SET(vop, p2i_en, 0); 440 act_end = vact_end; 441 } 442 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 443 vop_post_config(state, vop); 444 VOP_CTRL_SET(vop, core_dclk_div, 445 !!(mode->flags & DRM_MODE_FLAG_DBLCLK)); 446 447 VOP_LINE_FLAG_SET(vop, line_flag_num[0], act_end - 3); 448 VOP_LINE_FLAG_SET(vop, line_flag_num[1], 449 act_end - us_to_vertical_line(mode, 1000)); 450 if (state->crtc_state.mcu_timing.mcu_pix_total > 0) 451 vop_mcu_mode(state, vop); 452 vop_cfg_done(vop); 453 454 return 0; 455 } 456 457 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 458 uint32_t dst, bool is_horizontal, 459 int vsu_mode, int *vskiplines) 460 { 461 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 462 463 if (is_horizontal) { 464 if (mode == SCALE_UP) 465 val = GET_SCL_FT_BIC(src, dst); 466 else if (mode == SCALE_DOWN) 467 val = GET_SCL_FT_BILI_DN(src, dst); 468 } else { 469 if (mode == SCALE_UP) { 470 if (vsu_mode == SCALE_UP_BIL) 471 val = GET_SCL_FT_BILI_UP(src, dst); 472 else 473 val = GET_SCL_FT_BIC(src, dst); 474 } else if (mode == SCALE_DOWN) { 475 if (vskiplines) { 476 *vskiplines = scl_get_vskiplines(src, dst); 477 val = scl_get_bili_dn_vskip(src, dst, 478 *vskiplines); 479 } else { 480 val = GET_SCL_FT_BILI_DN(src, dst); 481 } 482 } 483 } 484 485 return val; 486 } 487 488 static void scl_vop_cal_scl_fac(struct vop *vop, 489 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 490 uint32_t dst_h, uint32_t pixel_format) 491 { 492 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 493 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 494 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 495 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 496 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 497 bool is_yuv = false; 498 uint16_t cbcr_src_w = src_w / hsub; 499 uint16_t cbcr_src_h = src_h / vsub; 500 uint16_t vsu_mode; 501 uint16_t lb_mode; 502 uint32_t val; 503 int vskiplines = 0; 504 505 if (!vop->win->scl) 506 return; 507 508 if (dst_w > vop->max_output.width) { 509 printf("Maximum destination width %d exceeded\n", 510 vop->max_output.width); 511 return; 512 } 513 514 if (!vop->win->scl->ext) { 515 VOP_SCL_SET(vop, scale_yrgb_x, 516 scl_cal_scale2(src_w, dst_w)); 517 VOP_SCL_SET(vop, scale_yrgb_y, 518 scl_cal_scale2(src_h, dst_h)); 519 if (is_yuv) { 520 VOP_SCL_SET(vop, scale_cbcr_x, 521 scl_cal_scale2(src_w, dst_w)); 522 VOP_SCL_SET(vop, scale_cbcr_y, 523 scl_cal_scale2(src_h, dst_h)); 524 } 525 return; 526 } 527 528 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 529 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 530 531 if (is_yuv) { 532 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 533 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 534 if (cbcr_hor_scl_mode == SCALE_DOWN) 535 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 536 else 537 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 538 } else { 539 if (yrgb_hor_scl_mode == SCALE_DOWN) 540 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 541 else 542 lb_mode = scl_vop_cal_lb_mode(src_w, false); 543 } 544 545 VOP_SCL_SET_EXT(vop, lb_mode, lb_mode); 546 if (lb_mode == LB_RGB_3840X2) { 547 if (yrgb_ver_scl_mode != SCALE_NONE) { 548 printf("ERROR : not allow yrgb ver scale\n"); 549 return; 550 } 551 if (cbcr_ver_scl_mode != SCALE_NONE) { 552 printf("ERROR : not allow cbcr ver scale\n"); 553 return; 554 } 555 vsu_mode = SCALE_UP_BIL; 556 } else if (lb_mode == LB_RGB_2560X4) { 557 vsu_mode = SCALE_UP_BIL; 558 } else { 559 vsu_mode = SCALE_UP_BIC; 560 } 561 562 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 563 true, 0, NULL); 564 VOP_SCL_SET(vop, scale_yrgb_x, val); 565 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 566 false, vsu_mode, &vskiplines); 567 VOP_SCL_SET(vop, scale_yrgb_y, val); 568 569 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt4, vskiplines == 4); 570 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt2, vskiplines == 2); 571 572 VOP_SCL_SET_EXT(vop, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 573 VOP_SCL_SET_EXT(vop, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 574 VOP_SCL_SET_EXT(vop, yrgb_hsd_mode, SCALE_DOWN_BIL); 575 VOP_SCL_SET_EXT(vop, yrgb_vsd_mode, SCALE_DOWN_BIL); 576 VOP_SCL_SET_EXT(vop, yrgb_vsu_mode, vsu_mode); 577 if (is_yuv) { 578 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 579 dst_w, true, 0, NULL); 580 VOP_SCL_SET(vop, scale_cbcr_x, val); 581 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 582 dst_h, false, vsu_mode, &vskiplines); 583 VOP_SCL_SET(vop, scale_cbcr_y, val); 584 585 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt4, vskiplines == 4); 586 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt2, vskiplines == 2); 587 VOP_SCL_SET_EXT(vop, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 588 VOP_SCL_SET_EXT(vop, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 589 VOP_SCL_SET_EXT(vop, cbcr_hsd_mode, SCALE_DOWN_BIL); 590 VOP_SCL_SET_EXT(vop, cbcr_vsd_mode, SCALE_DOWN_BIL); 591 VOP_SCL_SET_EXT(vop, cbcr_vsu_mode, vsu_mode); 592 } 593 } 594 595 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table) 596 { 597 int i; 598 599 /* 600 * so far the csc offset is not 0 and in the feature the csc offset 601 * impossible be 0, so when the offset is 0, should return here. 602 */ 603 if (!table || offset == 0) 604 return; 605 606 for (i = 0; i < 8; i++) 607 vop_writel(vop, offset + i * 4, table[i]); 608 } 609 610 static int rockchip_vop_setup_csc_table(struct display_state *state) 611 { 612 struct crtc_state *crtc_state = &state->crtc_state; 613 struct connector_state *conn_state = &state->conn_state; 614 struct vop *vop = crtc_state->private; 615 const uint32_t *csc_table = NULL; 616 617 if (!vop->csc_table || !crtc_state->yuv_overlay) 618 return 0; 619 /* todo: only implement r2y*/ 620 switch (conn_state->color_space) { 621 case V4L2_COLORSPACE_SMPTE170M: 622 csc_table = vop->csc_table->r2y_bt601_12_235; 623 break; 624 case V4L2_COLORSPACE_REC709: 625 case V4L2_COLORSPACE_DEFAULT: 626 case V4L2_COLORSPACE_JPEG: 627 csc_table = vop->csc_table->r2y_bt709; 628 break; 629 case V4L2_COLORSPACE_BT2020: 630 csc_table = vop->csc_table->r2y_bt2020; 631 break; 632 default: 633 csc_table = vop->csc_table->r2y_bt601; 634 break; 635 } 636 637 vop_load_csc_table(vop, vop->win_csc->r2y_offset, csc_table); 638 VOP_WIN_CSC_SET(vop, r2y_en, 1); 639 640 return 0; 641 } 642 643 static int rockchip_vop_set_plane(struct display_state *state) 644 { 645 struct crtc_state *crtc_state = &state->crtc_state; 646 const struct rockchip_crtc *crtc = crtc_state->crtc; 647 const struct vop_data *vop_data = crtc->data; 648 struct connector_state *conn_state = &state->conn_state; 649 struct drm_display_mode *mode = &conn_state->mode; 650 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 651 struct vop *vop = crtc_state->private; 652 int src_w = crtc_state->src_w; 653 int src_h = crtc_state->src_h; 654 int crtc_x = crtc_state->crtc_x; 655 int crtc_y = crtc_state->crtc_y; 656 int crtc_w = crtc_state->crtc_w; 657 int crtc_h = crtc_state->crtc_h; 658 int xvir = crtc_state->xvir; 659 int x_mirror = 0, y_mirror = 0; 660 661 act_info = (src_h - 1) << 16; 662 act_info |= (src_w - 1) & 0xffff; 663 664 dsp_info = (crtc_h - 1) << 16; 665 dsp_info |= (crtc_w - 1) & 0xffff; 666 667 dsp_stx = crtc_x + mode->crtc_htotal - mode->crtc_hsync_start; 668 dsp_sty = crtc_y + mode->crtc_vtotal - mode->crtc_vsync_start; 669 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 670 /* 671 * PX30 treat rgb888 as bgr888 672 * so we reverse the rb swap to workaround 673 */ 674 if (VOP_MAJOR(vop_data->version) == 2 && 675 VOP_MINOR(vop_data->version) == 6 && 676 crtc_state->format == ROCKCHIP_FMT_RGB888) 677 crtc_state->rb_swap = !crtc_state->rb_swap; 678 679 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 680 y_mirror = 1; 681 else 682 y_mirror = 0; 683 if (mode->flags & DRM_MODE_FLAG_XMIRROR) 684 x_mirror = 1; 685 else 686 x_mirror = 0; 687 if (crtc_state->ymirror ^ y_mirror) 688 y_mirror = 1; 689 else 690 y_mirror = 0; 691 if (y_mirror) { 692 if (VOP_CTRL_SUPPORT(vop, ymirror)) 693 crtc_state->dma_addr += (src_h - 1) * xvir * 4; 694 else 695 y_mirror = 0; 696 } 697 VOP_CTRL_SET(vop, ymirror, y_mirror); 698 VOP_CTRL_SET(vop, xmirror, x_mirror); 699 700 VOP_WIN_SET(vop, format, crtc_state->format); 701 VOP_WIN_SET(vop, yrgb_vir, xvir); 702 VOP_WIN_SET(vop, yrgb_mst, crtc_state->dma_addr); 703 704 scl_vop_cal_scl_fac(vop, src_w, src_h, crtc_w, crtc_h, 705 crtc_state->format); 706 707 VOP_WIN_SET(vop, act_info, act_info); 708 VOP_WIN_SET(vop, dsp_info, dsp_info); 709 VOP_WIN_SET(vop, dsp_st, dsp_st); 710 VOP_WIN_SET(vop, rb_swap, crtc_state->rb_swap); 711 712 VOP_WIN_SET(vop, src_alpha_ctl, 0); 713 714 rockchip_vop_setup_csc_table(state); 715 VOP_WIN_SET(vop, enable, 1); 716 vop_cfg_done(vop); 717 718 return 0; 719 } 720 721 static int rockchip_vop_prepare(struct display_state *state) 722 { 723 return 0; 724 } 725 726 static int rockchip_vop_enable(struct display_state *state) 727 { 728 struct crtc_state *crtc_state = &state->crtc_state; 729 struct vop *vop = crtc_state->private; 730 731 VOP_CTRL_SET(vop, standby, 0); 732 vop_cfg_done(vop); 733 if (crtc_state->mcu_timing.mcu_pix_total > 0) 734 VOP_CTRL_SET(vop, mcu_hold_mode, 0); 735 736 return 0; 737 } 738 739 static int rockchip_vop_disable(struct display_state *state) 740 { 741 struct crtc_state *crtc_state = &state->crtc_state; 742 struct vop *vop = crtc_state->private; 743 744 VOP_CTRL_SET(vop, standby, 1); 745 vop_cfg_done(vop); 746 return 0; 747 } 748 749 static int rockchip_vop_fixup_dts(struct display_state *state, void *blob) 750 { 751 #if 0 752 struct crtc_state *crtc_state = &state->crtc_state; 753 struct panel_state *pstate = &state->panel_state; 754 uint32_t phandle; 755 char path[100]; 756 int ret, dsp_lut_node; 757 758 if (!ofnode_valid(pstate->dsp_lut_node)) 759 return 0; 760 ret = fdt_get_path(state->blob, pstate->dsp_lut_node, path, sizeof(path)); 761 if (ret < 0) { 762 printf("failed to get dsp_lut path[%s], ret=%d\n", 763 path, ret); 764 return ret; 765 } 766 767 dsp_lut_node = fdt_path_offset(blob, path); 768 phandle = fdt_get_phandle(blob, dsp_lut_node); 769 if (!phandle) { 770 phandle = fdt_alloc_phandle(blob); 771 if (!phandle) { 772 printf("failed to alloc phandle\n"); 773 return -ENOMEM; 774 } 775 776 fdt_set_phandle(blob, dsp_lut_node, phandle); 777 } 778 779 ret = fdt_get_path(state->blob, crtc_state->node, path, sizeof(path)); 780 if (ret < 0) { 781 printf("failed to get route path[%s], ret=%d\n", 782 path, ret); 783 return ret; 784 } 785 786 do_fixup_by_path_u32(blob, path, "dsp-lut", phandle, 1); 787 #endif 788 return 0; 789 } 790 791 static int rockchip_vop_send_mcu_cmd(struct display_state *state, 792 u32 type, u32 value) 793 { 794 struct crtc_state *crtc_state = &state->crtc_state; 795 struct vop *vop = crtc_state->private; 796 797 if (vop) { 798 switch (type) { 799 case MCU_WRCMD: 800 VOP_CTRL_SET(vop, mcu_rs, 0); 801 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value); 802 VOP_CTRL_SET(vop, mcu_rs, 1); 803 break; 804 case MCU_WRDATA: 805 VOP_CTRL_SET(vop, mcu_rs, 1); 806 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value); 807 break; 808 case MCU_SETBYPASS: 809 VOP_CTRL_SET(vop, mcu_bypass, value ? 1 : 0); 810 break; 811 default: 812 break; 813 } 814 } 815 816 return 0; 817 } 818 819 const struct rockchip_crtc_funcs rockchip_vop_funcs = { 820 .init = rockchip_vop_init, 821 .set_plane = rockchip_vop_set_plane, 822 .prepare = rockchip_vop_prepare, 823 .enable = rockchip_vop_enable, 824 .disable = rockchip_vop_disable, 825 .fixup_dts = rockchip_vop_fixup_dts, 826 .send_mcu_cmd = rockchip_vop_send_mcu_cmd, 827 }; 828