1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <asm/io.h> 15 #include <linux/list.h> 16 #include <linux/media-bus-format.h> 17 #include <clk.h> 18 #include <asm/arch/clock.h> 19 #include <linux/err.h> 20 #include <dm/device.h> 21 #include <dm/read.h> 22 #include <syscon.h> 23 24 #include "rockchip_display.h" 25 #include "rockchip_crtc.h" 26 #include "rockchip_connector.h" 27 #include "rockchip_vop.h" 28 29 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 30 { 31 return us * mode->clock / mode->htotal / 1000; 32 } 33 34 static inline void set_vop_mcu_rs(struct vop *vop, int v) 35 { 36 if (dm_gpio_is_valid(&vop->mcu_rs_gpio)) 37 dm_gpio_set_value(&vop->mcu_rs_gpio, v); 38 else 39 VOP_CTRL_SET(vop, mcu_rs, v); 40 } 41 42 static int to_vop_csc_mode(int csc_mode) 43 { 44 switch (csc_mode) { 45 case V4L2_COLORSPACE_SMPTE170M: 46 return CSC_BT601L; 47 case V4L2_COLORSPACE_REC709: 48 case V4L2_COLORSPACE_DEFAULT: 49 return CSC_BT709L; 50 case V4L2_COLORSPACE_JPEG: 51 return CSC_BT601F; 52 case V4L2_COLORSPACE_BT2020: 53 return CSC_BT2020; 54 default: 55 return CSC_BT709L; 56 } 57 } 58 59 static bool is_yuv_output(uint32_t bus_format) 60 { 61 switch (bus_format) { 62 case MEDIA_BUS_FMT_YUV8_1X24: 63 case MEDIA_BUS_FMT_YUV10_1X30: 64 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 65 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 66 case MEDIA_BUS_FMT_YUYV8_2X8: 67 case MEDIA_BUS_FMT_YVYU8_2X8: 68 case MEDIA_BUS_FMT_UYVY8_2X8: 69 case MEDIA_BUS_FMT_VYUY8_2X8: 70 case MEDIA_BUS_FMT_YUYV8_1X16: 71 case MEDIA_BUS_FMT_YVYU8_1X16: 72 case MEDIA_BUS_FMT_UYVY8_1X16: 73 case MEDIA_BUS_FMT_VYUY8_1X16: 74 return true; 75 default: 76 return false; 77 } 78 } 79 80 static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode) 81 { 82 /* 83 * FIXME: 84 * 85 * There is no media type for YUV444 output, 86 * so when out_mode is AAAA or P888, assume output is YUV444 on 87 * yuv format. 88 * 89 * From H/W testing, YUV444 mode need a rb swap. 90 */ 91 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 92 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 93 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 94 output_mode == ROCKCHIP_OUT_MODE_P888)) 95 return true; 96 else 97 return false; 98 } 99 100 static bool is_rb_swap(uint32_t bus_format, uint32_t output_mode) 101 { 102 /* 103 * The default component order of serial rgb3x8 formats 104 * is BGR. So it is needed to enable RB swap. 105 */ 106 if (bus_format == MEDIA_BUS_FMT_RGB888_3X8 || 107 bus_format == MEDIA_BUS_FMT_RGB888_DUMMY_4X8) 108 return true; 109 else 110 return false; 111 } 112 113 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) 114 { 115 struct crtc_state *crtc_state = &state->crtc_state; 116 struct connector_state *conn_state = &state->conn_state; 117 u32 *lut = conn_state->gamma.lut; 118 fdt_size_t lut_size; 119 int i, lut_len; 120 u32 *lut_regs; 121 122 if (!conn_state->gamma.lut) 123 return 0; 124 125 i = dev_read_stringlist_search(crtc_state->dev, "reg-names", "gamma_lut"); 126 if (i < 0) { 127 printf("Warning: vop not support gamma\n"); 128 return 0; 129 } 130 lut_regs = (u32 *)dev_read_addr_size(crtc_state->dev, "reg", &lut_size); 131 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 132 printf("failed to get gamma lut register\n"); 133 return 0; 134 } 135 lut_len = lut_size / 4; 136 if (lut_len != 256 && lut_len != 1024) { 137 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 138 return 0; 139 } 140 141 if (conn_state->gamma.size != lut_len) { 142 int size = conn_state->gamma.size; 143 u32 j, r, g, b, color; 144 145 for (i = 0; i < lut_len; i++) { 146 j = i * size / lut_len; 147 r = lut[j] / size / size * lut_len / size; 148 g = lut[j] / size % size * lut_len / size; 149 b = lut[j] % size * lut_len / size; 150 color = r * lut_len * lut_len + g * lut_len + b; 151 152 writel(color, lut_regs + (i << 2)); 153 } 154 } else { 155 for (i = 0; i < lut_len; i++) 156 writel(lut[i], lut_regs + (i << 2)); 157 } 158 159 VOP_CTRL_SET(vop, dsp_lut_en, 1); 160 VOP_CTRL_SET(vop, update_gamma_lut, 1); 161 162 return 0; 163 } 164 165 static void vop_post_config(struct display_state *state, struct vop *vop) 166 { 167 struct connector_state *conn_state = &state->conn_state; 168 struct drm_display_mode *mode = &conn_state->mode; 169 u16 vtotal = mode->crtc_vtotal; 170 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 171 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 172 u16 hdisplay = mode->crtc_hdisplay; 173 u16 vdisplay = mode->crtc_vdisplay; 174 u16 hsize = hdisplay * (conn_state->overscan.left_margin + conn_state->overscan.right_margin) / 200; 175 u16 vsize = vdisplay * (conn_state->overscan.top_margin + conn_state->overscan.bottom_margin) / 200; 176 u16 hact_end, vact_end; 177 u32 val; 178 179 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 180 vsize = round_down(vsize, 2); 181 182 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 183 hact_end = hact_st + hsize; 184 val = hact_st << 16; 185 val |= hact_end; 186 187 VOP_CTRL_SET(vop, hpost_st_end, val); 188 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 189 vact_end = vact_st + vsize; 190 val = vact_st << 16; 191 val |= vact_end; 192 VOP_CTRL_SET(vop, vpost_st_end, val); 193 val = scl_cal_scale2(vdisplay, vsize) << 16; 194 val |= scl_cal_scale2(hdisplay, hsize); 195 VOP_CTRL_SET(vop, post_scl_factor, val); 196 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 197 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 198 VOP_CTRL_SET(vop, post_scl_ctrl, 199 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 200 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 201 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 202 u16 vact_st_f1 = vtotal + vact_st + 1; 203 u16 vact_end_f1 = vact_st_f1 + vsize; 204 205 val = vact_st_f1 << 16 | vact_end_f1; 206 VOP_CTRL_SET(vop, vpost_st_end_f1, val); 207 } 208 } 209 210 static void vop_mcu_mode(struct display_state *state, struct vop *vop) 211 { 212 struct crtc_state *crtc_state = &state->crtc_state; 213 214 VOP_CTRL_SET(vop, mcu_clk_sel, 1); 215 VOP_CTRL_SET(vop, mcu_type, 1); 216 217 VOP_CTRL_SET(vop, mcu_hold_mode, 1); 218 VOP_CTRL_SET(vop, mcu_pix_total, crtc_state->mcu_timing.mcu_pix_total); 219 VOP_CTRL_SET(vop, mcu_cs_pst, crtc_state->mcu_timing.mcu_cs_pst); 220 VOP_CTRL_SET(vop, mcu_cs_pend, crtc_state->mcu_timing.mcu_cs_pend); 221 VOP_CTRL_SET(vop, mcu_rw_pst, crtc_state->mcu_timing.mcu_rw_pst); 222 VOP_CTRL_SET(vop, mcu_rw_pend, crtc_state->mcu_timing.mcu_rw_pend); 223 } 224 225 static int rockchip_vop_preinit(struct display_state *state) 226 { 227 const struct vop_data *vop_data = state->crtc_state.crtc->data; 228 229 state->crtc_state.max_output = vop_data->max_output; 230 231 return 0; 232 } 233 234 static int rockchip_vop_init(struct display_state *state) 235 { 236 struct crtc_state *crtc_state = &state->crtc_state; 237 struct connector_state *conn_state = &state->conn_state; 238 struct drm_display_mode *mode = &conn_state->mode; 239 const struct rockchip_crtc *crtc = crtc_state->crtc; 240 const struct vop_data *vop_data = crtc->data; 241 struct vop *vop; 242 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 243 u16 hdisplay = mode->crtc_hdisplay; 244 u16 htotal = mode->crtc_htotal; 245 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 246 u16 hact_end = hact_st + hdisplay; 247 u16 vdisplay = mode->crtc_vdisplay; 248 u16 vtotal = mode->crtc_vtotal; 249 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 250 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 251 u16 vact_end = vact_st + vdisplay; 252 struct clk dclk; 253 u32 val, act_end; 254 int ret; 255 bool yuv_overlay = false, post_r2y_en = false, post_y2r_en = false; 256 u16 post_csc_mode; 257 bool dclk_inv; 258 char output_type_name[30] = {0}; 259 260 vop = malloc(sizeof(*vop)); 261 if (!vop) 262 return -ENOMEM; 263 memset(vop, 0, sizeof(*vop)); 264 265 crtc_state->private = vop; 266 vop->regs = dev_read_addr_ptr(crtc_state->dev); 267 vop->regsbak = malloc(vop_data->reg_len); 268 vop->win = vop_data->win; 269 vop->win_offset = vop_data->win_offset; 270 vop->ctrl = vop_data->ctrl; 271 vop->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 272 if (vop->grf <= 0) 273 printf("%s: Get syscon grf failed (ret=%p)\n", 274 __func__, vop->grf); 275 276 vop->grf_ctrl = vop_data->grf_ctrl; 277 vop->line_flag = vop_data->line_flag; 278 vop->csc_table = vop_data->csc_table; 279 vop->win_csc = vop_data->win_csc; 280 vop->version = vop_data->version; 281 282 printf("VOP:0x%8p update mode to: %dx%d%s%d, type:%s\n", 283 vop->regs, mode->crtc_hdisplay, mode->vdisplay, 284 mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p", 285 mode->vrefresh, 286 rockchip_get_output_if_name(conn_state->output_if, output_type_name)); 287 288 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 289 ret = clk_set_defaults(crtc_state->dev); 290 if (ret) 291 debug("%s clk_set_defaults failed %d\n", __func__, ret); 292 293 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &dclk); 294 if (!ret) 295 ret = clk_set_rate(&dclk, mode->crtc_clock * 1000); 296 if (IS_ERR_VALUE(ret)) { 297 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret); 298 return ret; 299 } 300 printf("VOP:0x%8p set crtc_clock to %dKHz\n", vop->regs, mode->crtc_clock); 301 302 memcpy(vop->regsbak, vop->regs, vop_data->reg_len); 303 304 rockchip_vop_init_gamma(vop, state); 305 306 ret = gpio_request_by_name(crtc_state->dev, "mcu-rs-gpios", 307 0, &vop->mcu_rs_gpio, GPIOD_IS_OUT); 308 if (ret && ret != -ENOENT) 309 printf("%s: Cannot get mcu rs GPIO: %d\n", __func__, ret); 310 311 VOP_CTRL_SET(vop, global_regdone_en, 1); 312 VOP_CTRL_SET(vop, axi_outstanding_max_num, 30); 313 VOP_CTRL_SET(vop, axi_max_outstanding_en, 1); 314 VOP_CTRL_SET(vop, reg_done_frm, 1); 315 VOP_CTRL_SET(vop, win_gate[0], 1); 316 VOP_CTRL_SET(vop, win_gate[1], 1); 317 VOP_CTRL_SET(vop, win_channel[0], 0x12); 318 VOP_CTRL_SET(vop, win_channel[1], 0x34); 319 VOP_CTRL_SET(vop, win_channel[2], 0x56); 320 VOP_CTRL_SET(vop, dsp_blank, 0); 321 322 dclk_inv = (conn_state->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0; 323 /* For improving signal quality, dclk need to be inverted by default on rv1106. */ 324 if ((VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) == 12)) 325 dclk_inv = !dclk_inv; 326 VOP_CTRL_SET(vop, dclk_pol, dclk_inv); 327 328 val = 0x8; 329 val |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 330 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 331 VOP_CTRL_SET(vop, pin_pol, val); 332 333 switch (conn_state->type) { 334 case DRM_MODE_CONNECTOR_LVDS: 335 VOP_CTRL_SET(vop, rgb_en, 1); 336 VOP_CTRL_SET(vop, rgb_pin_pol, val); 337 VOP_CTRL_SET(vop, rgb_dclk_pol, dclk_inv); 338 VOP_CTRL_SET(vop, lvds_en, 1); 339 VOP_CTRL_SET(vop, lvds_pin_pol, val); 340 VOP_CTRL_SET(vop, lvds_dclk_pol, dclk_inv); 341 if (!IS_ERR_OR_NULL(vop->grf)) 342 VOP_GRF_SET(vop, grf_dclk_inv, dclk_inv); 343 break; 344 case DRM_MODE_CONNECTOR_eDP: 345 VOP_CTRL_SET(vop, edp_en, 1); 346 VOP_CTRL_SET(vop, edp_pin_pol, val); 347 VOP_CTRL_SET(vop, edp_dclk_pol, dclk_inv); 348 break; 349 case DRM_MODE_CONNECTOR_HDMIA: 350 VOP_CTRL_SET(vop, hdmi_en, 1); 351 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 352 VOP_CTRL_SET(vop, hdmi_dclk_pol, 1); 353 break; 354 case DRM_MODE_CONNECTOR_DSI: 355 VOP_CTRL_SET(vop, mipi_en, 1); 356 VOP_CTRL_SET(vop, mipi_pin_pol, val); 357 VOP_CTRL_SET(vop, mipi_dclk_pol, dclk_inv); 358 VOP_CTRL_SET(vop, mipi_dual_channel_en, 359 !!(conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)); 360 VOP_CTRL_SET(vop, data01_swap, 361 !!(conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) || 362 crtc_state->dual_channel_swap); 363 break; 364 case DRM_MODE_CONNECTOR_DisplayPort: 365 VOP_CTRL_SET(vop, dp_dclk_pol, 0); 366 VOP_CTRL_SET(vop, dp_pin_pol, val); 367 VOP_CTRL_SET(vop, dp_en, 1); 368 break; 369 case DRM_MODE_CONNECTOR_TV: 370 if (vdisplay == CVBS_PAL_VDISPLAY) 371 VOP_CTRL_SET(vop, tve_sw_mode, 1); 372 else 373 VOP_CTRL_SET(vop, tve_sw_mode, 0); 374 VOP_CTRL_SET(vop, tve_dclk_pol, 1); 375 VOP_CTRL_SET(vop, tve_dclk_en, 1); 376 /* use the same pol reg with hdmi */ 377 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 378 VOP_CTRL_SET(vop, sw_genlock, 1); 379 VOP_CTRL_SET(vop, sw_uv_offset_en, 1); 380 VOP_CTRL_SET(vop, dither_up, 1); 381 break; 382 default: 383 printf("unsupport connector_type[%d]\n", conn_state->type); 384 } 385 386 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 387 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 388 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 389 390 switch (conn_state->bus_format) { 391 case MEDIA_BUS_FMT_RGB565_1X16: 392 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565); 393 break; 394 case MEDIA_BUS_FMT_RGB666_1X18: 395 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 396 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 397 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: 398 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666); 399 break; 400 case MEDIA_BUS_FMT_YUV8_1X24: 401 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 402 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1); 403 break; 404 case MEDIA_BUS_FMT_YUV10_1X30: 405 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 406 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 407 break; 408 case MEDIA_BUS_FMT_RGB888_1X24: 409 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 410 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 411 default: 412 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 413 break; 414 } 415 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 416 val |= PRE_DITHER_DOWN_EN(0); 417 else 418 val |= PRE_DITHER_DOWN_EN(1); 419 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO); 420 VOP_CTRL_SET(vop, dither_down, val); 421 422 VOP_CTRL_SET(vop, dclk_ddr, 423 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 424 VOP_CTRL_SET(vop, hdmi_dclk_out_en, 425 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 426 427 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode) || 428 is_rb_swap(conn_state->bus_format, conn_state->output_mode)) 429 VOP_CTRL_SET(vop, dsp_rb_swap, 1); 430 else 431 VOP_CTRL_SET(vop, dsp_data_swap, 0); 432 433 VOP_CTRL_SET(vop, out_mode, conn_state->output_mode); 434 435 if (VOP_CTRL_SUPPORT(vop, overlay_mode)) { 436 yuv_overlay = is_yuv_output(conn_state->bus_format); 437 VOP_CTRL_SET(vop, overlay_mode, yuv_overlay); 438 } 439 /* 440 * todo: r2y for win csc 441 */ 442 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(conn_state->bus_format)); 443 444 if (yuv_overlay) { 445 if (!is_yuv_output(conn_state->bus_format)) 446 post_y2r_en = true; 447 } else { 448 if (is_yuv_output(conn_state->bus_format)) 449 post_r2y_en = true; 450 } 451 452 crtc_state->yuv_overlay = yuv_overlay; 453 post_csc_mode = to_vop_csc_mode(conn_state->color_space); 454 VOP_CTRL_SET(vop, bcsh_r2y_en, post_r2y_en); 455 VOP_CTRL_SET(vop, bcsh_y2r_en, post_y2r_en); 456 VOP_CTRL_SET(vop, bcsh_r2y_csc_mode, post_csc_mode); 457 VOP_CTRL_SET(vop, bcsh_y2r_csc_mode, post_csc_mode); 458 459 /* 460 * Background color is 10bit depth if vop version >= 3.5 461 */ 462 if (!is_yuv_output(conn_state->bus_format)) 463 val = 0; 464 else if (VOP_MAJOR(vop->version) == 3 && 465 VOP_MINOR(vop->version) >= 5) 466 val = 0x20010200; 467 else 468 val = 0x801080; 469 VOP_CTRL_SET(vop, dsp_background, val); 470 471 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 472 val = hact_st << 16; 473 val |= hact_end; 474 VOP_CTRL_SET(vop, hact_st_end, val); 475 val = vact_st << 16; 476 val |= vact_end; 477 VOP_CTRL_SET(vop, vact_st_end, val); 478 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 479 u16 vact_st_f1 = vtotal + vact_st + 1; 480 u16 vact_end_f1 = vact_st_f1 + vdisplay; 481 482 val = vact_st_f1 << 16 | vact_end_f1; 483 VOP_CTRL_SET(vop, vact_st_end_f1, val); 484 485 val = vtotal << 16 | (vtotal + vsync_len); 486 VOP_CTRL_SET(vop, vs_st_end_f1, val); 487 VOP_CTRL_SET(vop, dsp_interlace, 1); 488 VOP_CTRL_SET(vop, p2i_en, 1); 489 vtotal += vtotal + 1; 490 act_end = vact_end_f1; 491 } else { 492 VOP_CTRL_SET(vop, dsp_interlace, 0); 493 VOP_CTRL_SET(vop, p2i_en, 0); 494 act_end = vact_end; 495 } 496 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 497 vop_post_config(state, vop); 498 VOP_CTRL_SET(vop, core_dclk_div, 499 !!(mode->flags & DRM_MODE_FLAG_DBLCLK)); 500 501 VOP_LINE_FLAG_SET(vop, line_flag_num[0], act_end - 3); 502 VOP_LINE_FLAG_SET(vop, line_flag_num[1], 503 act_end - us_to_vertical_line(mode, 1000)); 504 if (state->crtc_state.mcu_timing.mcu_pix_total > 0) 505 vop_mcu_mode(state, vop); 506 vop_cfg_done(vop); 507 508 return 0; 509 } 510 511 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 512 uint32_t dst, bool is_horizontal, 513 int vsu_mode, int *vskiplines) 514 { 515 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 516 517 if (is_horizontal) { 518 if (mode == SCALE_UP) 519 val = GET_SCL_FT_BIC(src, dst); 520 else if (mode == SCALE_DOWN) 521 val = GET_SCL_FT_BILI_DN(src, dst); 522 } else { 523 if (mode == SCALE_UP) { 524 if (vsu_mode == SCALE_UP_BIL) 525 val = GET_SCL_FT_BILI_UP(src, dst); 526 else 527 val = GET_SCL_FT_BIC(src, dst); 528 } else if (mode == SCALE_DOWN) { 529 if (vskiplines) { 530 *vskiplines = scl_get_vskiplines(src, dst); 531 val = scl_get_bili_dn_vskip(src, dst, 532 *vskiplines); 533 } else { 534 val = GET_SCL_FT_BILI_DN(src, dst); 535 } 536 } 537 } 538 539 return val; 540 } 541 542 static void scl_vop_cal_scl_fac(struct vop *vop, 543 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 544 uint32_t dst_h, uint32_t pixel_format) 545 { 546 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 547 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 548 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 549 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 550 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 551 bool is_yuv = false; 552 uint16_t cbcr_src_w = src_w / hsub; 553 uint16_t cbcr_src_h = src_h / vsub; 554 uint16_t vsu_mode; 555 uint16_t lb_mode; 556 uint32_t val; 557 int vskiplines = 0; 558 559 if (!vop->win->scl) 560 return; 561 562 if (!vop->win->scl->ext) { 563 VOP_SCL_SET(vop, scale_yrgb_x, 564 scl_cal_scale2(src_w, dst_w)); 565 VOP_SCL_SET(vop, scale_yrgb_y, 566 scl_cal_scale2(src_h, dst_h)); 567 if (is_yuv) { 568 VOP_SCL_SET(vop, scale_cbcr_x, 569 scl_cal_scale2(src_w, dst_w)); 570 VOP_SCL_SET(vop, scale_cbcr_y, 571 scl_cal_scale2(src_h, dst_h)); 572 } 573 return; 574 } 575 576 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 577 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 578 579 if (is_yuv) { 580 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 581 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 582 if (cbcr_hor_scl_mode == SCALE_DOWN) 583 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 584 else 585 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 586 } else { 587 if (yrgb_hor_scl_mode == SCALE_DOWN) 588 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 589 else 590 lb_mode = scl_vop_cal_lb_mode(src_w, false); 591 } 592 593 VOP_SCL_SET_EXT(vop, lb_mode, lb_mode); 594 if (lb_mode == LB_RGB_3840X2) { 595 if (yrgb_ver_scl_mode != SCALE_NONE) { 596 printf("ERROR : not allow yrgb ver scale\n"); 597 return; 598 } 599 if (cbcr_ver_scl_mode != SCALE_NONE) { 600 printf("ERROR : not allow cbcr ver scale\n"); 601 return; 602 } 603 vsu_mode = SCALE_UP_BIL; 604 } else if (lb_mode == LB_RGB_2560X4) { 605 vsu_mode = SCALE_UP_BIL; 606 } else { 607 vsu_mode = SCALE_UP_BIC; 608 } 609 610 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 611 true, 0, NULL); 612 VOP_SCL_SET(vop, scale_yrgb_x, val); 613 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 614 false, vsu_mode, &vskiplines); 615 VOP_SCL_SET(vop, scale_yrgb_y, val); 616 617 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt4, vskiplines == 4); 618 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt2, vskiplines == 2); 619 620 VOP_SCL_SET_EXT(vop, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 621 VOP_SCL_SET_EXT(vop, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 622 VOP_SCL_SET_EXT(vop, yrgb_hsd_mode, SCALE_DOWN_BIL); 623 VOP_SCL_SET_EXT(vop, yrgb_vsd_mode, SCALE_DOWN_BIL); 624 VOP_SCL_SET_EXT(vop, yrgb_vsu_mode, vsu_mode); 625 if (is_yuv) { 626 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 627 dst_w, true, 0, NULL); 628 VOP_SCL_SET(vop, scale_cbcr_x, val); 629 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 630 dst_h, false, vsu_mode, &vskiplines); 631 VOP_SCL_SET(vop, scale_cbcr_y, val); 632 633 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt4, vskiplines == 4); 634 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt2, vskiplines == 2); 635 VOP_SCL_SET_EXT(vop, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 636 VOP_SCL_SET_EXT(vop, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 637 VOP_SCL_SET_EXT(vop, cbcr_hsd_mode, SCALE_DOWN_BIL); 638 VOP_SCL_SET_EXT(vop, cbcr_vsd_mode, SCALE_DOWN_BIL); 639 VOP_SCL_SET_EXT(vop, cbcr_vsu_mode, vsu_mode); 640 } 641 } 642 643 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table) 644 { 645 int i; 646 647 /* 648 * so far the csc offset is not 0 and in the feature the csc offset 649 * impossible be 0, so when the offset is 0, should return here. 650 */ 651 if (!table || offset == 0) 652 return; 653 654 for (i = 0; i < 8; i++) 655 vop_writel(vop, offset + i * 4, table[i]); 656 } 657 658 static int rockchip_vop_setup_csc_table(struct display_state *state) 659 { 660 struct crtc_state *crtc_state = &state->crtc_state; 661 struct connector_state *conn_state = &state->conn_state; 662 struct vop *vop = crtc_state->private; 663 const uint32_t *csc_table = NULL; 664 665 if (!vop->csc_table || !crtc_state->yuv_overlay) 666 return 0; 667 /* todo: only implement r2y*/ 668 switch (conn_state->color_space) { 669 case V4L2_COLORSPACE_SMPTE170M: 670 csc_table = vop->csc_table->r2y_bt601_12_235; 671 break; 672 case V4L2_COLORSPACE_REC709: 673 case V4L2_COLORSPACE_DEFAULT: 674 case V4L2_COLORSPACE_JPEG: 675 csc_table = vop->csc_table->r2y_bt709; 676 break; 677 case V4L2_COLORSPACE_BT2020: 678 csc_table = vop->csc_table->r2y_bt2020; 679 break; 680 default: 681 csc_table = vop->csc_table->r2y_bt601; 682 break; 683 } 684 685 vop_load_csc_table(vop, vop->win_csc->r2y_offset, csc_table); 686 VOP_WIN_CSC_SET(vop, r2y_en, 1); 687 688 return 0; 689 } 690 691 static int rockchip_vop_set_plane(struct display_state *state) 692 { 693 struct crtc_state *crtc_state = &state->crtc_state; 694 const struct rockchip_crtc *crtc = crtc_state->crtc; 695 const struct vop_data *vop_data = crtc->data; 696 struct connector_state *conn_state = &state->conn_state; 697 struct drm_display_mode *mode = &conn_state->mode; 698 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 699 struct vop *vop = crtc_state->private; 700 int src_w = crtc_state->src_rect.w; 701 int src_h = crtc_state->src_rect.h; 702 int crtc_x = crtc_state->crtc_rect.x; 703 int crtc_y = crtc_state->crtc_rect.y; 704 int crtc_w = crtc_state->crtc_rect.w; 705 int crtc_h = crtc_state->crtc_rect.h; 706 int xvir = crtc_state->xvir; 707 int x_mirror = 0, y_mirror = 0; 708 709 if (crtc_w > crtc_state->max_output.width) { 710 printf("ERROR: output w[%d] exceeded max width[%d]\n", 711 crtc_w, crtc_state->max_output.width); 712 return -EINVAL; 713 } 714 715 act_info = (src_h - 1) << 16; 716 act_info |= (src_w - 1) & 0xffff; 717 718 dsp_info = (crtc_h - 1) << 16; 719 dsp_info |= (crtc_w - 1) & 0xffff; 720 721 dsp_stx = crtc_x + mode->crtc_htotal - mode->crtc_hsync_start; 722 dsp_sty = crtc_y + mode->crtc_vtotal - mode->crtc_vsync_start; 723 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 724 /* 725 * vop full need to treats rgb888 as bgr888 so we reverse the rb swap to workaround 726 */ 727 if (crtc_state->format == ROCKCHIP_FMT_RGB888 && VOP_MAJOR(vop_data->version) == 3) 728 crtc_state->rb_swap = !crtc_state->rb_swap; 729 730 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 731 y_mirror = 1; 732 else 733 y_mirror = 0; 734 if (mode->flags & DRM_MODE_FLAG_XMIRROR) 735 x_mirror = 1; 736 else 737 x_mirror = 0; 738 if (crtc_state->ymirror ^ y_mirror) 739 y_mirror = 1; 740 else 741 y_mirror = 0; 742 if (y_mirror) { 743 if (VOP_CTRL_SUPPORT(vop, ymirror)) 744 crtc_state->dma_addr += (src_h - 1) * xvir * 4; 745 else 746 y_mirror = 0; 747 } 748 VOP_CTRL_SET(vop, ymirror, y_mirror); 749 VOP_CTRL_SET(vop, xmirror, x_mirror); 750 751 VOP_WIN_SET(vop, format, crtc_state->format); 752 VOP_WIN_SET(vop, yrgb_vir, xvir); 753 VOP_WIN_SET(vop, yrgb_mst, crtc_state->dma_addr); 754 755 scl_vop_cal_scl_fac(vop, src_w, src_h, crtc_w, crtc_h, 756 crtc_state->format); 757 758 VOP_WIN_SET(vop, act_info, act_info); 759 VOP_WIN_SET(vop, dsp_info, dsp_info); 760 VOP_WIN_SET(vop, dsp_st, dsp_st); 761 VOP_WIN_SET(vop, rb_swap, crtc_state->rb_swap); 762 763 VOP_WIN_SET(vop, src_alpha_ctl, 0); 764 765 rockchip_vop_setup_csc_table(state); 766 VOP_WIN_SET(vop, enable, 1); 767 VOP_WIN_SET(vop, gate, 1); 768 vop_cfg_done(vop); 769 770 return 0; 771 } 772 773 static int rockchip_vop_prepare(struct display_state *state) 774 { 775 return 0; 776 } 777 778 static int rockchip_vop_enable(struct display_state *state) 779 { 780 struct crtc_state *crtc_state = &state->crtc_state; 781 struct vop *vop = crtc_state->private; 782 783 VOP_CTRL_SET(vop, standby, 0); 784 vop_cfg_done(vop); 785 if (crtc_state->mcu_timing.mcu_pix_total > 0) 786 VOP_CTRL_SET(vop, mcu_hold_mode, 0); 787 788 return 0; 789 } 790 791 static int rockchip_vop_disable(struct display_state *state) 792 { 793 struct crtc_state *crtc_state = &state->crtc_state; 794 struct vop *vop = crtc_state->private; 795 796 VOP_CTRL_SET(vop, standby, 1); 797 vop_cfg_done(vop); 798 return 0; 799 } 800 801 static int rockchip_vop_fixup_dts(struct display_state *state, void *blob) 802 { 803 #if 0 804 struct crtc_state *crtc_state = &state->crtc_state; 805 struct panel_state *pstate = &state->panel_state; 806 uint32_t phandle; 807 char path[100]; 808 int ret, dsp_lut_node; 809 810 if (!ofnode_valid(pstate->dsp_lut_node)) 811 return 0; 812 ret = fdt_get_path(state->blob, pstate->dsp_lut_node, path, sizeof(path)); 813 if (ret < 0) { 814 printf("failed to get dsp_lut path[%s], ret=%d\n", 815 path, ret); 816 return ret; 817 } 818 819 dsp_lut_node = fdt_path_offset(blob, path); 820 phandle = fdt_get_phandle(blob, dsp_lut_node); 821 if (!phandle) { 822 phandle = fdt_alloc_phandle(blob); 823 if (!phandle) { 824 printf("failed to alloc phandle\n"); 825 return -ENOMEM; 826 } 827 828 fdt_set_phandle(blob, dsp_lut_node, phandle); 829 } 830 831 ret = fdt_get_path(state->blob, crtc_state->node, path, sizeof(path)); 832 if (ret < 0) { 833 printf("failed to get route path[%s], ret=%d\n", 834 path, ret); 835 return ret; 836 } 837 838 do_fixup_by_path_u32(blob, path, "dsp-lut", phandle, 1); 839 #endif 840 return 0; 841 } 842 843 static int rockchip_vop_send_mcu_cmd(struct display_state *state, 844 u32 type, u32 value) 845 { 846 struct crtc_state *crtc_state = &state->crtc_state; 847 struct vop *vop = crtc_state->private; 848 849 if (vop) { 850 switch (type) { 851 case MCU_WRCMD: 852 set_vop_mcu_rs(vop, 0); 853 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value); 854 set_vop_mcu_rs(vop, 1); 855 break; 856 case MCU_WRDATA: 857 set_vop_mcu_rs(vop, 1); 858 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value); 859 break; 860 case MCU_SETBYPASS: 861 VOP_CTRL_SET(vop, mcu_bypass, value ? 1 : 0); 862 break; 863 default: 864 break; 865 } 866 } 867 868 return 0; 869 } 870 871 static int rockchip_vop_mode_valid(struct display_state *state) 872 { 873 struct connector_state *conn_state = &state->conn_state; 874 struct drm_display_mode *mode = &conn_state->mode; 875 struct videomode vm; 876 877 drm_display_mode_to_videomode(mode, &vm); 878 879 if (vm.hactive < 32 || vm.vactive < 32 || 880 (vm.hfront_porch * vm.hsync_len * vm.hback_porch * 881 vm.vfront_porch * vm.vsync_len * vm.vback_porch == 0)) { 882 printf("ERROR: unsupported display timing\n"); 883 return -EINVAL; 884 } 885 886 return 0; 887 } 888 889 static int rockchip_vop_plane_check(struct display_state *state) 890 { 891 struct crtc_state *crtc_state = &state->crtc_state; 892 const struct rockchip_crtc *crtc = crtc_state->crtc; 893 const struct vop_data *vop_data = crtc->data; 894 const struct vop_win *win = vop_data->win; 895 struct display_rect *src = &crtc_state->src_rect; 896 struct display_rect *dst = &crtc_state->crtc_rect; 897 int min_scale, max_scale; 898 int hscale, vscale; 899 900 min_scale = win->scl ? FRAC_16_16(1, 8) : VOP_PLANE_NO_SCALING; 901 max_scale = win->scl ? FRAC_16_16(8, 1) : VOP_PLANE_NO_SCALING; 902 903 hscale = display_rect_calc_hscale(src, dst, min_scale, max_scale); 904 vscale = display_rect_calc_vscale(src, dst, min_scale, max_scale); 905 if (hscale < 0 || vscale < 0) { 906 printf("ERROR: scale factor is out of range\n"); 907 return -ERANGE; 908 } 909 910 return 0; 911 } 912 913 static int rockchip_vop_mode_fixup(struct display_state *state) 914 { 915 struct crtc_state *crtc_state = &state->crtc_state; 916 struct connector_state *conn_state = &state->conn_state; 917 struct drm_display_mode *mode = &conn_state->mode; 918 919 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE); 920 921 mode->crtc_clock *= rockchip_drm_get_cycles_per_pixel(conn_state->bus_format); 922 if (crtc_state->mcu_timing.mcu_pix_total) 923 mode->crtc_clock *= crtc_state->mcu_timing.mcu_pix_total + 1; 924 925 return 0; 926 } 927 928 const struct rockchip_crtc_funcs rockchip_vop_funcs = { 929 .preinit = rockchip_vop_preinit, 930 .init = rockchip_vop_init, 931 .set_plane = rockchip_vop_set_plane, 932 .prepare = rockchip_vop_prepare, 933 .enable = rockchip_vop_enable, 934 .disable = rockchip_vop_disable, 935 .fixup_dts = rockchip_vop_fixup_dts, 936 .send_mcu_cmd = rockchip_vop_send_mcu_cmd, 937 .mode_valid = rockchip_vop_mode_valid, 938 .plane_check = rockchip_vop_plane_check, 939 .mode_fixup = rockchip_vop_mode_fixup, 940 }; 941