1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <asm/io.h> 15 #include <linux/list.h> 16 #include <linux/media-bus-format.h> 17 #include <clk.h> 18 #include <asm/arch/clock.h> 19 #include <linux/err.h> 20 #include <dm/device.h> 21 #include <dm/read.h> 22 23 #include "rockchip_display.h" 24 #include "rockchip_crtc.h" 25 #include "rockchip_connector.h" 26 #include "rockchip_vop.h" 27 28 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 29 { 30 return us * mode->clock / mode->htotal / 1000; 31 } 32 33 static int to_vop_csc_mode(int csc_mode) 34 { 35 switch (csc_mode) { 36 case V4L2_COLORSPACE_SMPTE170M: 37 return CSC_BT601L; 38 case V4L2_COLORSPACE_REC709: 39 case V4L2_COLORSPACE_DEFAULT: 40 return CSC_BT709L; 41 case V4L2_COLORSPACE_JPEG: 42 return CSC_BT601F; 43 case V4L2_COLORSPACE_BT2020: 44 return CSC_BT2020; 45 default: 46 return CSC_BT709L; 47 } 48 } 49 50 static bool is_yuv_output(uint32_t bus_format) 51 { 52 switch (bus_format) { 53 case MEDIA_BUS_FMT_YUV8_1X24: 54 case MEDIA_BUS_FMT_YUV10_1X30: 55 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 56 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 57 return true; 58 default: 59 return false; 60 } 61 } 62 63 static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode) 64 { 65 /* 66 * FIXME: 67 * 68 * There is no media type for YUV444 output, 69 * so when out_mode is AAAA or P888, assume output is YUV444 on 70 * yuv format. 71 * 72 * From H/W testing, YUV444 mode need a rb swap. 73 */ 74 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 75 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 76 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 77 output_mode == ROCKCHIP_OUT_MODE_P888)) 78 return true; 79 else 80 return false; 81 } 82 83 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) 84 { 85 struct crtc_state *crtc_state = &state->crtc_state; 86 struct connector_state *conn_state = &state->conn_state; 87 u32 *lut = conn_state->gamma.lut; 88 fdt_size_t lut_size; 89 int i, lut_len; 90 u32 *lut_regs; 91 92 if (!conn_state->gamma.lut) 93 return 0; 94 95 i = dev_read_stringlist_search(crtc_state->dev, "reg-names", "gamma_lut"); 96 if (i < 0) { 97 printf("Warning: vop not support gamma\n"); 98 return 0; 99 } 100 lut_regs = (u32 *)dev_read_addr_size(crtc_state->dev, "reg", &lut_size); 101 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 102 printf("failed to get gamma lut register\n"); 103 return 0; 104 } 105 lut_len = lut_size / 4; 106 if (lut_len != 256 && lut_len != 1024) { 107 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 108 return 0; 109 } 110 111 if (conn_state->gamma.size != lut_len) { 112 int size = conn_state->gamma.size; 113 u32 j, r, g, b, color; 114 115 for (i = 0; i < lut_len; i++) { 116 j = i * size / lut_len; 117 r = lut[j] / size / size * lut_len / size; 118 g = lut[j] / size % size * lut_len / size; 119 b = lut[j] % size * lut_len / size; 120 color = r * lut_len * lut_len + g * lut_len + b; 121 122 writel(color, lut_regs + (i << 2)); 123 } 124 } else { 125 for (i = 0; i < lut_len; i++) 126 writel(lut[i], lut_regs + (i << 2)); 127 } 128 129 VOP_CTRL_SET(vop, dsp_lut_en, 1); 130 VOP_CTRL_SET(vop, update_gamma_lut, 1); 131 132 return 0; 133 } 134 135 static void vop_post_config(struct display_state *state, struct vop *vop) 136 { 137 struct connector_state *conn_state = &state->conn_state; 138 struct drm_display_mode *mode = &conn_state->mode; 139 u16 vtotal = mode->crtc_vtotal; 140 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 141 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 142 u16 hdisplay = mode->crtc_hdisplay; 143 u16 vdisplay = mode->crtc_vdisplay; 144 u16 hsize = hdisplay * (conn_state->overscan.left_margin + conn_state->overscan.right_margin) / 200; 145 u16 vsize = vdisplay * (conn_state->overscan.top_margin + conn_state->overscan.bottom_margin) / 200; 146 u16 hact_end, vact_end; 147 u32 val; 148 149 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 150 vsize = round_down(vsize, 2); 151 152 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 153 hact_end = hact_st + hsize; 154 val = hact_st << 16; 155 val |= hact_end; 156 157 VOP_CTRL_SET(vop, hpost_st_end, val); 158 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 159 vact_end = vact_st + vsize; 160 val = vact_st << 16; 161 val |= vact_end; 162 VOP_CTRL_SET(vop, vpost_st_end, val); 163 val = scl_cal_scale2(vdisplay, vsize) << 16; 164 val |= scl_cal_scale2(hdisplay, hsize); 165 VOP_CTRL_SET(vop, post_scl_factor, val); 166 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 167 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 168 VOP_CTRL_SET(vop, post_scl_ctrl, 169 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 170 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 171 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 172 u16 vact_st_f1 = vtotal + vact_st + 1; 173 u16 vact_end_f1 = vact_st_f1 + vsize; 174 175 val = vact_st_f1 << 16 | vact_end_f1; 176 VOP_CTRL_SET(vop, vpost_st_end_f1, val); 177 } 178 } 179 180 static int rockchip_vop_init(struct display_state *state) 181 { 182 struct crtc_state *crtc_state = &state->crtc_state; 183 struct connector_state *conn_state = &state->conn_state; 184 struct drm_display_mode *mode = &conn_state->mode; 185 const struct rockchip_crtc *crtc = crtc_state->crtc; 186 const struct vop_data *vop_data = crtc->data; 187 struct vop *vop; 188 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 189 u16 hdisplay = mode->crtc_hdisplay; 190 u16 htotal = mode->crtc_htotal; 191 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 192 u16 hact_end = hact_st + hdisplay; 193 u16 vdisplay = mode->crtc_vdisplay; 194 u16 vtotal = mode->crtc_vtotal; 195 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 196 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 197 u16 vact_end = vact_st + vdisplay; 198 struct clk dclk, aclk; 199 u32 val, act_end; 200 int ret; 201 bool yuv_overlay = false, post_r2y_en = false, post_y2r_en = false; 202 u16 post_csc_mode; 203 204 vop = malloc(sizeof(*vop)); 205 if (!vop) 206 return -ENOMEM; 207 memset(vop, 0, sizeof(*vop)); 208 209 crtc_state->private = vop; 210 vop->regs = dev_read_addr_ptr(crtc_state->dev); 211 vop->regsbak = malloc(vop_data->reg_len); 212 vop->win = vop_data->win; 213 vop->win_offset = vop_data->win_offset; 214 vop->ctrl = vop_data->ctrl; 215 vop->line_flag = vop_data->line_flag; 216 vop->version = vop_data->version; 217 218 /* 219 * TODO: 220 * Set Dclk pll parent 221 */ 222 223 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &dclk); 224 if (!ret) 225 ret = clk_set_rate(&dclk, mode->clock * 1000); 226 if (IS_ERR_VALUE(ret)) { 227 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret); 228 return ret; 229 } 230 231 ret = clk_get_by_name(crtc_state->dev, "aclk_vop", &aclk); 232 if (!ret) 233 ret = clk_set_rate(&aclk, 400 * 1000 * 1000); 234 if (IS_ERR_VALUE(ret)) 235 printf("%s: Failed to set aclk: ret=%d\n", __func__, ret); 236 237 memcpy(vop->regsbak, vop->regs, vop_data->reg_len); 238 239 rockchip_vop_init_gamma(vop, state); 240 241 VOP_CTRL_SET(vop, global_regdone_en, 1); 242 VOP_CTRL_SET(vop, axi_outstanding_max_num, 30); 243 VOP_CTRL_SET(vop, axi_max_outstanding_en, 1); 244 VOP_CTRL_SET(vop, reg_done_frm, 1); 245 VOP_CTRL_SET(vop, win_gate[0], 1); 246 VOP_CTRL_SET(vop, win_gate[1], 1); 247 VOP_CTRL_SET(vop, win_channel[0], 0x12); 248 VOP_CTRL_SET(vop, win_channel[1], 0x34); 249 VOP_CTRL_SET(vop, win_channel[2], 0x56); 250 VOP_CTRL_SET(vop, dsp_blank, 0); 251 252 val = 0x8; 253 val |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 254 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 255 VOP_CTRL_SET(vop, pin_pol, val); 256 257 switch (conn_state->type) { 258 case DRM_MODE_CONNECTOR_LVDS: 259 VOP_CTRL_SET(vop, rgb_en, 1); 260 VOP_CTRL_SET(vop, rgb_pin_pol, val); 261 break; 262 case DRM_MODE_CONNECTOR_eDP: 263 VOP_CTRL_SET(vop, edp_en, 1); 264 VOP_CTRL_SET(vop, edp_pin_pol, val); 265 break; 266 case DRM_MODE_CONNECTOR_HDMIA: 267 VOP_CTRL_SET(vop, hdmi_en, 1); 268 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 269 break; 270 case DRM_MODE_CONNECTOR_DSI: 271 VOP_CTRL_SET(vop, mipi_en, 1); 272 VOP_CTRL_SET(vop, mipi_pin_pol, val); 273 VOP_CTRL_SET(vop, mipi_dual_channel_en, 274 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_CHANNEL)); 275 VOP_CTRL_SET(vop, data01_swap, 276 !!(conn_state->output_type & ROCKCHIP_OUTPUT_DSI_DUAL_LINK)); 277 break; 278 case DRM_MODE_CONNECTOR_TV: 279 if (vdisplay == CVBS_PAL_VDISPLAY) 280 VOP_CTRL_SET(vop, tve_sw_mode, 1); 281 else 282 VOP_CTRL_SET(vop, tve_sw_mode, 0); 283 VOP_CTRL_SET(vop, tve_dclk_pol, 1); 284 VOP_CTRL_SET(vop, tve_dclk_en, 1); 285 /* use the same pol reg with hdmi */ 286 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 287 VOP_CTRL_SET(vop, sw_genlock, 1); 288 VOP_CTRL_SET(vop, sw_uv_offset_en, 1); 289 VOP_CTRL_SET(vop, dither_up, 1); 290 break; 291 default: 292 printf("unsupport connector_type[%d]\n", conn_state->type); 293 } 294 295 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 296 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 297 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 298 299 switch (conn_state->bus_format) { 300 case MEDIA_BUS_FMT_RGB565_1X16: 301 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565); 302 break; 303 case MEDIA_BUS_FMT_RGB666_1X18: 304 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 305 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666); 306 break; 307 case MEDIA_BUS_FMT_YUV8_1X24: 308 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 309 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1); 310 break; 311 case MEDIA_BUS_FMT_YUV10_1X30: 312 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 313 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 314 break; 315 case MEDIA_BUS_FMT_RGB888_1X24: 316 default: 317 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 318 break; 319 } 320 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 321 val |= PRE_DITHER_DOWN_EN(0); 322 else 323 val |= PRE_DITHER_DOWN_EN(1); 324 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO); 325 VOP_CTRL_SET(vop, dither_down, val); 326 327 VOP_CTRL_SET(vop, dclk_ddr, 328 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 329 VOP_CTRL_SET(vop, hdmi_dclk_out_en, 330 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 331 332 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 333 VOP_CTRL_SET(vop, dsp_data_swap, DSP_RB_SWAP); 334 else 335 VOP_CTRL_SET(vop, dsp_data_swap, 0); 336 337 VOP_CTRL_SET(vop, out_mode, conn_state->output_mode); 338 339 if (VOP_CTRL_SUPPORT(vop, overlay_mode)) { 340 yuv_overlay = is_yuv_output(conn_state->bus_format); 341 VOP_CTRL_SET(vop, overlay_mode, yuv_overlay); 342 } 343 /* 344 * todo: r2y for win csc 345 */ 346 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(conn_state->bus_format)); 347 348 if (yuv_overlay) { 349 if (!is_yuv_output(conn_state->bus_format)) 350 post_y2r_en = true; 351 } else { 352 if (is_yuv_output(conn_state->bus_format)) 353 post_r2y_en = true; 354 } 355 356 post_csc_mode = to_vop_csc_mode(conn_state->color_space); 357 VOP_CTRL_SET(vop, bcsh_r2y_en, post_r2y_en); 358 VOP_CTRL_SET(vop, bcsh_y2r_en, post_y2r_en); 359 VOP_CTRL_SET(vop, bcsh_r2y_csc_mode, post_csc_mode); 360 VOP_CTRL_SET(vop, bcsh_y2r_csc_mode, post_csc_mode); 361 362 /* 363 * Background color is 10bit depth if vop version >= 3.5 364 */ 365 if (!is_yuv_output(conn_state->bus_format)) 366 val = 0; 367 else if (VOP_MAJOR(vop->version) == 3 && 368 VOP_MINOR(vop->version) >= 5) 369 val = 0x20010200; 370 else 371 val = 0x801080; 372 VOP_CTRL_SET(vop, dsp_background, val); 373 374 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 375 val = hact_st << 16; 376 val |= hact_end; 377 VOP_CTRL_SET(vop, hact_st_end, val); 378 val = vact_st << 16; 379 val |= vact_end; 380 VOP_CTRL_SET(vop, vact_st_end, val); 381 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 382 u16 vact_st_f1 = vtotal + vact_st + 1; 383 u16 vact_end_f1 = vact_st_f1 + vdisplay; 384 385 val = vact_st_f1 << 16 | vact_end_f1; 386 VOP_CTRL_SET(vop, vact_st_end_f1, val); 387 388 val = vtotal << 16 | (vtotal + vsync_len); 389 VOP_CTRL_SET(vop, vs_st_end_f1, val); 390 VOP_CTRL_SET(vop, dsp_interlace, 1); 391 VOP_CTRL_SET(vop, p2i_en, 1); 392 vtotal += vtotal + 1; 393 act_end = vact_end_f1; 394 } else { 395 VOP_CTRL_SET(vop, dsp_interlace, 0); 396 VOP_CTRL_SET(vop, p2i_en, 0); 397 act_end = vact_end; 398 } 399 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 400 vop_post_config(state, vop); 401 VOP_CTRL_SET(vop, core_dclk_div, 402 !!(mode->flags & DRM_MODE_FLAG_DBLCLK)); 403 404 VOP_CTRL_SET(vop, standby, 1); 405 VOP_LINE_FLAG_SET(vop, line_flag_num[0], act_end - 3); 406 VOP_LINE_FLAG_SET(vop, line_flag_num[1], 407 act_end - us_to_vertical_line(mode, 1000)); 408 vop_cfg_done(vop); 409 410 return 0; 411 } 412 413 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 414 uint32_t dst, bool is_horizontal, 415 int vsu_mode, int *vskiplines) 416 { 417 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 418 419 if (is_horizontal) { 420 if (mode == SCALE_UP) 421 val = GET_SCL_FT_BIC(src, dst); 422 else if (mode == SCALE_DOWN) 423 val = GET_SCL_FT_BILI_DN(src, dst); 424 } else { 425 if (mode == SCALE_UP) { 426 if (vsu_mode == SCALE_UP_BIL) 427 val = GET_SCL_FT_BILI_UP(src, dst); 428 else 429 val = GET_SCL_FT_BIC(src, dst); 430 } else if (mode == SCALE_DOWN) { 431 if (vskiplines) { 432 *vskiplines = scl_get_vskiplines(src, dst); 433 val = scl_get_bili_dn_vskip(src, dst, 434 *vskiplines); 435 } else { 436 val = GET_SCL_FT_BILI_DN(src, dst); 437 } 438 } 439 } 440 441 return val; 442 } 443 444 static void scl_vop_cal_scl_fac(struct vop *vop, 445 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 446 uint32_t dst_h, uint32_t pixel_format) 447 { 448 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 449 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 450 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 451 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 452 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 453 bool is_yuv = false; 454 uint16_t cbcr_src_w = src_w / hsub; 455 uint16_t cbcr_src_h = src_h / vsub; 456 uint16_t vsu_mode; 457 uint16_t lb_mode; 458 uint32_t val; 459 int vskiplines = 0; 460 461 if (!vop->win->scl) 462 return; 463 464 if (dst_w > 3840) { 465 printf("Maximum destination width (3840) exceeded\n"); 466 return; 467 } 468 469 if (!vop->win->scl->ext) { 470 VOP_SCL_SET(vop, scale_yrgb_x, 471 scl_cal_scale2(src_w, dst_w)); 472 VOP_SCL_SET(vop, scale_yrgb_y, 473 scl_cal_scale2(src_h, dst_h)); 474 if (is_yuv) { 475 VOP_SCL_SET(vop, scale_cbcr_x, 476 scl_cal_scale2(src_w, dst_w)); 477 VOP_SCL_SET(vop, scale_cbcr_y, 478 scl_cal_scale2(src_h, dst_h)); 479 } 480 return; 481 } 482 483 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 484 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 485 486 if (is_yuv) { 487 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 488 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 489 if (cbcr_hor_scl_mode == SCALE_DOWN) 490 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 491 else 492 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 493 } else { 494 if (yrgb_hor_scl_mode == SCALE_DOWN) 495 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 496 else 497 lb_mode = scl_vop_cal_lb_mode(src_w, false); 498 } 499 500 VOP_SCL_SET_EXT(vop, lb_mode, lb_mode); 501 if (lb_mode == LB_RGB_3840X2) { 502 if (yrgb_ver_scl_mode != SCALE_NONE) { 503 printf("ERROR : not allow yrgb ver scale\n"); 504 return; 505 } 506 if (cbcr_ver_scl_mode != SCALE_NONE) { 507 printf("ERROR : not allow cbcr ver scale\n"); 508 return; 509 } 510 vsu_mode = SCALE_UP_BIL; 511 } else if (lb_mode == LB_RGB_2560X4) { 512 vsu_mode = SCALE_UP_BIL; 513 } else { 514 vsu_mode = SCALE_UP_BIC; 515 } 516 517 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 518 true, 0, NULL); 519 VOP_SCL_SET(vop, scale_yrgb_x, val); 520 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 521 false, vsu_mode, &vskiplines); 522 VOP_SCL_SET(vop, scale_yrgb_y, val); 523 524 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt4, vskiplines == 4); 525 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt2, vskiplines == 2); 526 527 VOP_SCL_SET_EXT(vop, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 528 VOP_SCL_SET_EXT(vop, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 529 VOP_SCL_SET_EXT(vop, yrgb_hsd_mode, SCALE_DOWN_BIL); 530 VOP_SCL_SET_EXT(vop, yrgb_vsd_mode, SCALE_DOWN_BIL); 531 VOP_SCL_SET_EXT(vop, yrgb_vsu_mode, vsu_mode); 532 if (is_yuv) { 533 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 534 dst_w, true, 0, NULL); 535 VOP_SCL_SET(vop, scale_cbcr_x, val); 536 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 537 dst_h, false, vsu_mode, &vskiplines); 538 VOP_SCL_SET(vop, scale_cbcr_y, val); 539 540 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt4, vskiplines == 4); 541 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt2, vskiplines == 2); 542 VOP_SCL_SET_EXT(vop, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 543 VOP_SCL_SET_EXT(vop, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 544 VOP_SCL_SET_EXT(vop, cbcr_hsd_mode, SCALE_DOWN_BIL); 545 VOP_SCL_SET_EXT(vop, cbcr_vsd_mode, SCALE_DOWN_BIL); 546 VOP_SCL_SET_EXT(vop, cbcr_vsu_mode, vsu_mode); 547 } 548 } 549 550 static int rockchip_vop_set_plane(struct display_state *state) 551 { 552 struct crtc_state *crtc_state = &state->crtc_state; 553 struct connector_state *conn_state = &state->conn_state; 554 struct drm_display_mode *mode = &conn_state->mode; 555 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 556 struct vop *vop = crtc_state->private; 557 int src_w = crtc_state->src_w; 558 int src_h = crtc_state->src_h; 559 int crtc_x = crtc_state->crtc_x; 560 int crtc_y = crtc_state->crtc_y; 561 int crtc_w = crtc_state->crtc_w; 562 int crtc_h = crtc_state->crtc_h; 563 int xvir = crtc_state->xvir; 564 565 act_info = (src_h - 1) << 16; 566 act_info |= (src_w - 1) & 0xffff; 567 568 dsp_info = (crtc_h - 1) << 16; 569 dsp_info |= (crtc_w - 1) & 0xffff; 570 571 dsp_stx = crtc_x + mode->htotal - mode->hsync_start; 572 dsp_sty = crtc_y + mode->vtotal - mode->vsync_start; 573 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 574 575 if (crtc_state->ymirror) 576 crtc_state->dma_addr += (src_h - 1) * xvir * 4; 577 VOP_WIN_SET(vop, ymirror, crtc_state->ymirror); 578 VOP_WIN_SET(vop, format, crtc_state->format); 579 VOP_WIN_SET(vop, yrgb_vir, xvir); 580 VOP_WIN_SET(vop, yrgb_mst, crtc_state->dma_addr); 581 582 scl_vop_cal_scl_fac(vop, src_w, src_h, crtc_w, crtc_h, 583 crtc_state->format); 584 585 VOP_WIN_SET(vop, act_info, act_info); 586 VOP_WIN_SET(vop, dsp_info, dsp_info); 587 VOP_WIN_SET(vop, dsp_st, dsp_st); 588 VOP_WIN_SET(vop, rb_swap, crtc_state->rb_swap); 589 590 VOP_WIN_SET(vop, src_alpha_ctl, 0); 591 592 VOP_WIN_SET(vop, enable, 1); 593 vop_cfg_done(vop); 594 595 return 0; 596 } 597 598 static int rockchip_vop_prepare(struct display_state *state) 599 { 600 return 0; 601 } 602 603 static int rockchip_vop_enable(struct display_state *state) 604 { 605 struct crtc_state *crtc_state = &state->crtc_state; 606 struct vop *vop = crtc_state->private; 607 608 VOP_CTRL_SET(vop, standby, 0); 609 vop_cfg_done(vop); 610 611 return 0; 612 } 613 614 static int rockchip_vop_disable(struct display_state *state) 615 { 616 struct crtc_state *crtc_state = &state->crtc_state; 617 struct vop *vop = crtc_state->private; 618 619 VOP_CTRL_SET(vop, standby, 1); 620 vop_cfg_done(vop); 621 return 0; 622 } 623 624 static int rockchip_vop_fixup_dts(struct display_state *state, void *blob) 625 { 626 #if 0 627 struct crtc_state *crtc_state = &state->crtc_state; 628 struct panel_state *pstate = &state->panel_state; 629 uint32_t phandle; 630 char path[100]; 631 int ret, dsp_lut_node; 632 633 if (!ofnode_valid(pstate->dsp_lut_node)) 634 return 0; 635 ret = fdt_get_path(state->blob, pstate->dsp_lut_node, path, sizeof(path)); 636 if (ret < 0) { 637 printf("failed to get dsp_lut path[%s], ret=%d\n", 638 path, ret); 639 return ret; 640 } 641 642 dsp_lut_node = fdt_path_offset(blob, path); 643 phandle = fdt_get_phandle(blob, dsp_lut_node); 644 if (!phandle) { 645 phandle = fdt_alloc_phandle(blob); 646 if (!phandle) { 647 printf("failed to alloc phandle\n"); 648 return -ENOMEM; 649 } 650 651 fdt_set_phandle(blob, dsp_lut_node, phandle); 652 } 653 654 ret = fdt_get_path(state->blob, crtc_state->node, path, sizeof(path)); 655 if (ret < 0) { 656 printf("failed to get route path[%s], ret=%d\n", 657 path, ret); 658 return ret; 659 } 660 661 do_fixup_by_path_u32(blob, path, "dsp-lut", phandle, 1); 662 #endif 663 return 0; 664 } 665 666 const struct rockchip_crtc_funcs rockchip_vop_funcs = { 667 .init = rockchip_vop_init, 668 .set_plane = rockchip_vop_set_plane, 669 .prepare = rockchip_vop_prepare, 670 .enable = rockchip_vop_enable, 671 .disable = rockchip_vop_disable, 672 .fixup_dts = rockchip_vop_fixup_dts, 673 }; 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