1 /* 2 * (C) Copyright 2008-2017 Fuzhou Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <config.h> 8 #include <common.h> 9 #include <errno.h> 10 #include <malloc.h> 11 #include <fdtdec.h> 12 #include <fdt_support.h> 13 #include <asm/unaligned.h> 14 #include <asm/io.h> 15 #include <linux/list.h> 16 #include <linux/media-bus-format.h> 17 #include <clk.h> 18 #include <asm/arch/clock.h> 19 #include <linux/err.h> 20 #include <dm/device.h> 21 #include <dm/read.h> 22 #include <syscon.h> 23 24 #include "rockchip_display.h" 25 #include "rockchip_crtc.h" 26 #include "rockchip_connector.h" 27 #include "rockchip_vop.h" 28 29 static inline int us_to_vertical_line(struct drm_display_mode *mode, int us) 30 { 31 return us * mode->clock / mode->htotal / 1000; 32 } 33 34 static inline void set_vop_mcu_rs(struct vop *vop, int v) 35 { 36 if (dm_gpio_is_valid(&vop->mcu_rs_gpio)) 37 dm_gpio_set_value(&vop->mcu_rs_gpio, v); 38 else 39 VOP_CTRL_SET(vop, mcu_rs, v); 40 } 41 42 static int to_vop_csc_mode(int csc_mode) 43 { 44 switch (csc_mode) { 45 case V4L2_COLORSPACE_SMPTE170M: 46 return CSC_BT601L; 47 case V4L2_COLORSPACE_REC709: 48 case V4L2_COLORSPACE_DEFAULT: 49 return CSC_BT709L; 50 case V4L2_COLORSPACE_JPEG: 51 return CSC_BT601F; 52 case V4L2_COLORSPACE_BT2020: 53 return CSC_BT2020; 54 default: 55 return CSC_BT709L; 56 } 57 } 58 59 static bool is_yuv_output(uint32_t bus_format) 60 { 61 switch (bus_format) { 62 case MEDIA_BUS_FMT_YUV8_1X24: 63 case MEDIA_BUS_FMT_YUV10_1X30: 64 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 65 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 66 return true; 67 default: 68 return false; 69 } 70 } 71 72 static bool is_uv_swap(uint32_t bus_format, uint32_t output_mode) 73 { 74 /* 75 * FIXME: 76 * 77 * There is no media type for YUV444 output, 78 * so when out_mode is AAAA or P888, assume output is YUV444 on 79 * yuv format. 80 * 81 * From H/W testing, YUV444 mode need a rb swap. 82 */ 83 if ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 || 84 bus_format == MEDIA_BUS_FMT_YUV10_1X30) && 85 (output_mode == ROCKCHIP_OUT_MODE_AAAA || 86 output_mode == ROCKCHIP_OUT_MODE_P888)) 87 return true; 88 else 89 return false; 90 } 91 92 static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state) 93 { 94 struct crtc_state *crtc_state = &state->crtc_state; 95 struct connector_state *conn_state = &state->conn_state; 96 u32 *lut = conn_state->gamma.lut; 97 fdt_size_t lut_size; 98 int i, lut_len; 99 u32 *lut_regs; 100 101 if (!conn_state->gamma.lut) 102 return 0; 103 104 i = dev_read_stringlist_search(crtc_state->dev, "reg-names", "gamma_lut"); 105 if (i < 0) { 106 printf("Warning: vop not support gamma\n"); 107 return 0; 108 } 109 lut_regs = (u32 *)dev_read_addr_size(crtc_state->dev, "reg", &lut_size); 110 if (lut_regs == (u32 *)FDT_ADDR_T_NONE) { 111 printf("failed to get gamma lut register\n"); 112 return 0; 113 } 114 lut_len = lut_size / 4; 115 if (lut_len != 256 && lut_len != 1024) { 116 printf("Warning: unsupport gamma lut table[%d]\n", lut_len); 117 return 0; 118 } 119 120 if (conn_state->gamma.size != lut_len) { 121 int size = conn_state->gamma.size; 122 u32 j, r, g, b, color; 123 124 for (i = 0; i < lut_len; i++) { 125 j = i * size / lut_len; 126 r = lut[j] / size / size * lut_len / size; 127 g = lut[j] / size % size * lut_len / size; 128 b = lut[j] % size * lut_len / size; 129 color = r * lut_len * lut_len + g * lut_len + b; 130 131 writel(color, lut_regs + (i << 2)); 132 } 133 } else { 134 for (i = 0; i < lut_len; i++) 135 writel(lut[i], lut_regs + (i << 2)); 136 } 137 138 VOP_CTRL_SET(vop, dsp_lut_en, 1); 139 VOP_CTRL_SET(vop, update_gamma_lut, 1); 140 141 return 0; 142 } 143 144 static void vop_post_config(struct display_state *state, struct vop *vop) 145 { 146 struct connector_state *conn_state = &state->conn_state; 147 struct drm_display_mode *mode = &conn_state->mode; 148 u16 vtotal = mode->crtc_vtotal; 149 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 150 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 151 u16 hdisplay = mode->crtc_hdisplay; 152 u16 vdisplay = mode->crtc_vdisplay; 153 u16 hsize = hdisplay * (conn_state->overscan.left_margin + conn_state->overscan.right_margin) / 200; 154 u16 vsize = vdisplay * (conn_state->overscan.top_margin + conn_state->overscan.bottom_margin) / 200; 155 u16 hact_end, vact_end; 156 u32 val; 157 158 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 159 vsize = round_down(vsize, 2); 160 161 hact_st += hdisplay * (100 - conn_state->overscan.left_margin) / 200; 162 hact_end = hact_st + hsize; 163 val = hact_st << 16; 164 val |= hact_end; 165 166 VOP_CTRL_SET(vop, hpost_st_end, val); 167 vact_st += vdisplay * (100 - conn_state->overscan.top_margin) / 200; 168 vact_end = vact_st + vsize; 169 val = vact_st << 16; 170 val |= vact_end; 171 VOP_CTRL_SET(vop, vpost_st_end, val); 172 val = scl_cal_scale2(vdisplay, vsize) << 16; 173 val |= scl_cal_scale2(hdisplay, hsize); 174 VOP_CTRL_SET(vop, post_scl_factor, val); 175 #define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0) 176 #define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1) 177 VOP_CTRL_SET(vop, post_scl_ctrl, 178 POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) | 179 POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize)); 180 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 181 u16 vact_st_f1 = vtotal + vact_st + 1; 182 u16 vact_end_f1 = vact_st_f1 + vsize; 183 184 val = vact_st_f1 << 16 | vact_end_f1; 185 VOP_CTRL_SET(vop, vpost_st_end_f1, val); 186 } 187 } 188 189 static void vop_mcu_mode(struct display_state *state, struct vop *vop) 190 { 191 struct crtc_state *crtc_state = &state->crtc_state; 192 193 VOP_CTRL_SET(vop, mcu_clk_sel, 1); 194 VOP_CTRL_SET(vop, mcu_type, 1); 195 196 VOP_CTRL_SET(vop, mcu_hold_mode, 1); 197 VOP_CTRL_SET(vop, mcu_pix_total, crtc_state->mcu_timing.mcu_pix_total); 198 VOP_CTRL_SET(vop, mcu_cs_pst, crtc_state->mcu_timing.mcu_cs_pst); 199 VOP_CTRL_SET(vop, mcu_cs_pend, crtc_state->mcu_timing.mcu_cs_pend); 200 VOP_CTRL_SET(vop, mcu_rw_pst, crtc_state->mcu_timing.mcu_rw_pst); 201 VOP_CTRL_SET(vop, mcu_rw_pend, crtc_state->mcu_timing.mcu_rw_pend); 202 } 203 204 static int rockchip_vop_preinit(struct display_state *state) 205 { 206 const struct vop_data *vop_data = state->crtc_state.crtc->data; 207 208 state->crtc_state.max_output = vop_data->max_output; 209 210 return 0; 211 } 212 213 static int rockchip_vop_init(struct display_state *state) 214 { 215 struct crtc_state *crtc_state = &state->crtc_state; 216 struct connector_state *conn_state = &state->conn_state; 217 struct drm_display_mode *mode = &conn_state->mode; 218 const struct rockchip_crtc *crtc = crtc_state->crtc; 219 const struct vop_data *vop_data = crtc->data; 220 struct vop *vop; 221 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start; 222 u16 hdisplay = mode->crtc_hdisplay; 223 u16 htotal = mode->crtc_htotal; 224 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start; 225 u16 hact_end = hact_st + hdisplay; 226 u16 vdisplay = mode->crtc_vdisplay; 227 u16 vtotal = mode->crtc_vtotal; 228 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start; 229 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start; 230 u16 vact_end = vact_st + vdisplay; 231 struct clk dclk; 232 u32 val, act_end; 233 int ret; 234 bool yuv_overlay = false, post_r2y_en = false, post_y2r_en = false; 235 u16 post_csc_mode; 236 bool dclk_inv; 237 238 vop = malloc(sizeof(*vop)); 239 if (!vop) 240 return -ENOMEM; 241 memset(vop, 0, sizeof(*vop)); 242 243 crtc_state->private = vop; 244 vop->regs = dev_read_addr_ptr(crtc_state->dev); 245 vop->regsbak = malloc(vop_data->reg_len); 246 vop->win = vop_data->win; 247 vop->win_offset = vop_data->win_offset; 248 vop->ctrl = vop_data->ctrl; 249 vop->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 250 if (vop->grf <= 0) 251 printf("%s: Get syscon grf failed (ret=%p)\n", 252 __func__, vop->grf); 253 254 vop->grf_ctrl = vop_data->grf_ctrl; 255 vop->line_flag = vop_data->line_flag; 256 vop->csc_table = vop_data->csc_table; 257 vop->win_csc = vop_data->win_csc; 258 vop->version = vop_data->version; 259 260 /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ 261 ret = clk_set_defaults(crtc_state->dev); 262 if (ret) 263 debug("%s clk_set_defaults failed %d\n", __func__, ret); 264 265 ret = clk_get_by_name(crtc_state->dev, "dclk_vop", &dclk); 266 if (!ret) 267 ret = clk_set_rate(&dclk, mode->clock * 1000); 268 if (IS_ERR_VALUE(ret)) { 269 printf("%s: Failed to set dclk: ret=%d\n", __func__, ret); 270 return ret; 271 } 272 273 memcpy(vop->regsbak, vop->regs, vop_data->reg_len); 274 275 rockchip_vop_init_gamma(vop, state); 276 277 ret = gpio_request_by_name(crtc_state->dev, "mcu-rs-gpios", 278 0, &vop->mcu_rs_gpio, GPIOD_IS_OUT); 279 if (ret && ret != -ENOENT) 280 printf("%s: Cannot get mcu rs GPIO: %d\n", __func__, ret); 281 282 VOP_CTRL_SET(vop, global_regdone_en, 1); 283 VOP_CTRL_SET(vop, axi_outstanding_max_num, 30); 284 VOP_CTRL_SET(vop, axi_max_outstanding_en, 1); 285 VOP_CTRL_SET(vop, reg_done_frm, 1); 286 VOP_CTRL_SET(vop, win_gate[0], 1); 287 VOP_CTRL_SET(vop, win_gate[1], 1); 288 VOP_CTRL_SET(vop, win_channel[0], 0x12); 289 VOP_CTRL_SET(vop, win_channel[1], 0x34); 290 VOP_CTRL_SET(vop, win_channel[2], 0x56); 291 VOP_CTRL_SET(vop, dsp_blank, 0); 292 293 dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1; 294 VOP_CTRL_SET(vop, dclk_pol, dclk_inv); 295 296 val = 0x8; 297 val |= (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1; 298 val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1); 299 VOP_CTRL_SET(vop, pin_pol, val); 300 301 switch (conn_state->type) { 302 case DRM_MODE_CONNECTOR_LVDS: 303 VOP_CTRL_SET(vop, rgb_en, 1); 304 VOP_CTRL_SET(vop, rgb_pin_pol, val); 305 VOP_CTRL_SET(vop, rgb_dclk_pol, dclk_inv); 306 VOP_CTRL_SET(vop, lvds_en, 1); 307 VOP_CTRL_SET(vop, lvds_pin_pol, val); 308 VOP_CTRL_SET(vop, lvds_dclk_pol, dclk_inv); 309 if (!IS_ERR_OR_NULL(vop->grf)) 310 VOP_GRF_SET(vop, grf_dclk_inv, dclk_inv); 311 break; 312 case DRM_MODE_CONNECTOR_eDP: 313 VOP_CTRL_SET(vop, edp_en, 1); 314 VOP_CTRL_SET(vop, edp_pin_pol, val); 315 VOP_CTRL_SET(vop, edp_dclk_pol, dclk_inv); 316 break; 317 case DRM_MODE_CONNECTOR_HDMIA: 318 VOP_CTRL_SET(vop, hdmi_en, 1); 319 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 320 VOP_CTRL_SET(vop, hdmi_dclk_pol, 1); 321 break; 322 case DRM_MODE_CONNECTOR_DSI: 323 VOP_CTRL_SET(vop, mipi_en, 1); 324 VOP_CTRL_SET(vop, mipi_pin_pol, val); 325 VOP_CTRL_SET(vop, mipi_dclk_pol, dclk_inv); 326 VOP_CTRL_SET(vop, mipi_dual_channel_en, 327 !!(conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)); 328 VOP_CTRL_SET(vop, data01_swap, 329 !!(conn_state->output_flags & ROCKCHIP_OUTPUT_DATA_SWAP) || 330 crtc_state->dual_channel_swap); 331 break; 332 case DRM_MODE_CONNECTOR_DisplayPort: 333 VOP_CTRL_SET(vop, dp_dclk_pol, 0); 334 VOP_CTRL_SET(vop, dp_pin_pol, val); 335 VOP_CTRL_SET(vop, dp_en, 1); 336 break; 337 case DRM_MODE_CONNECTOR_TV: 338 if (vdisplay == CVBS_PAL_VDISPLAY) 339 VOP_CTRL_SET(vop, tve_sw_mode, 1); 340 else 341 VOP_CTRL_SET(vop, tve_sw_mode, 0); 342 VOP_CTRL_SET(vop, tve_dclk_pol, 1); 343 VOP_CTRL_SET(vop, tve_dclk_en, 1); 344 /* use the same pol reg with hdmi */ 345 VOP_CTRL_SET(vop, hdmi_pin_pol, val); 346 VOP_CTRL_SET(vop, sw_genlock, 1); 347 VOP_CTRL_SET(vop, sw_uv_offset_en, 1); 348 VOP_CTRL_SET(vop, dither_up, 1); 349 break; 350 default: 351 printf("unsupport connector_type[%d]\n", conn_state->type); 352 } 353 354 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA && 355 !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT)) 356 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 357 358 switch (conn_state->bus_format) { 359 case MEDIA_BUS_FMT_RGB565_1X16: 360 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565); 361 break; 362 case MEDIA_BUS_FMT_RGB666_1X18: 363 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI: 364 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 365 case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA: 366 val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666); 367 break; 368 case MEDIA_BUS_FMT_YUV8_1X24: 369 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 370 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1); 371 break; 372 case MEDIA_BUS_FMT_YUV10_1X30: 373 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 374 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 375 break; 376 case MEDIA_BUS_FMT_RGB888_1X24: 377 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 378 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 379 default: 380 val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0); 381 break; 382 } 383 if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA) 384 val |= PRE_DITHER_DOWN_EN(0); 385 else 386 val |= PRE_DITHER_DOWN_EN(1); 387 val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO); 388 VOP_CTRL_SET(vop, dither_down, val); 389 390 VOP_CTRL_SET(vop, dclk_ddr, 391 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 392 VOP_CTRL_SET(vop, hdmi_dclk_out_en, 393 conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0); 394 395 if (is_uv_swap(conn_state->bus_format, conn_state->output_mode)) 396 VOP_CTRL_SET(vop, dsp_data_swap, DSP_RB_SWAP); 397 else 398 VOP_CTRL_SET(vop, dsp_data_swap, 0); 399 400 VOP_CTRL_SET(vop, out_mode, conn_state->output_mode); 401 402 if (VOP_CTRL_SUPPORT(vop, overlay_mode)) { 403 yuv_overlay = is_yuv_output(conn_state->bus_format); 404 VOP_CTRL_SET(vop, overlay_mode, yuv_overlay); 405 } 406 /* 407 * todo: r2y for win csc 408 */ 409 VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(conn_state->bus_format)); 410 411 if (yuv_overlay) { 412 if (!is_yuv_output(conn_state->bus_format)) 413 post_y2r_en = true; 414 } else { 415 if (is_yuv_output(conn_state->bus_format)) 416 post_r2y_en = true; 417 } 418 419 crtc_state->yuv_overlay = yuv_overlay; 420 post_csc_mode = to_vop_csc_mode(conn_state->color_space); 421 VOP_CTRL_SET(vop, bcsh_r2y_en, post_r2y_en); 422 VOP_CTRL_SET(vop, bcsh_y2r_en, post_y2r_en); 423 VOP_CTRL_SET(vop, bcsh_r2y_csc_mode, post_csc_mode); 424 VOP_CTRL_SET(vop, bcsh_y2r_csc_mode, post_csc_mode); 425 426 /* 427 * Background color is 10bit depth if vop version >= 3.5 428 */ 429 if (!is_yuv_output(conn_state->bus_format)) 430 val = 0; 431 else if (VOP_MAJOR(vop->version) == 3 && 432 VOP_MINOR(vop->version) >= 5) 433 val = 0x20010200; 434 else 435 val = 0x801080; 436 VOP_CTRL_SET(vop, dsp_background, val); 437 438 VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len); 439 val = hact_st << 16; 440 val |= hact_end; 441 VOP_CTRL_SET(vop, hact_st_end, val); 442 val = vact_st << 16; 443 val |= vact_end; 444 VOP_CTRL_SET(vop, vact_st_end, val); 445 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 446 u16 vact_st_f1 = vtotal + vact_st + 1; 447 u16 vact_end_f1 = vact_st_f1 + vdisplay; 448 449 val = vact_st_f1 << 16 | vact_end_f1; 450 VOP_CTRL_SET(vop, vact_st_end_f1, val); 451 452 val = vtotal << 16 | (vtotal + vsync_len); 453 VOP_CTRL_SET(vop, vs_st_end_f1, val); 454 VOP_CTRL_SET(vop, dsp_interlace, 1); 455 VOP_CTRL_SET(vop, p2i_en, 1); 456 vtotal += vtotal + 1; 457 act_end = vact_end_f1; 458 } else { 459 VOP_CTRL_SET(vop, dsp_interlace, 0); 460 VOP_CTRL_SET(vop, p2i_en, 0); 461 act_end = vact_end; 462 } 463 VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len); 464 vop_post_config(state, vop); 465 VOP_CTRL_SET(vop, core_dclk_div, 466 !!(mode->flags & DRM_MODE_FLAG_DBLCLK)); 467 468 VOP_LINE_FLAG_SET(vop, line_flag_num[0], act_end - 3); 469 VOP_LINE_FLAG_SET(vop, line_flag_num[1], 470 act_end - us_to_vertical_line(mode, 1000)); 471 if (state->crtc_state.mcu_timing.mcu_pix_total > 0) 472 vop_mcu_mode(state, vop); 473 vop_cfg_done(vop); 474 475 return 0; 476 } 477 478 static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src, 479 uint32_t dst, bool is_horizontal, 480 int vsu_mode, int *vskiplines) 481 { 482 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT; 483 484 if (is_horizontal) { 485 if (mode == SCALE_UP) 486 val = GET_SCL_FT_BIC(src, dst); 487 else if (mode == SCALE_DOWN) 488 val = GET_SCL_FT_BILI_DN(src, dst); 489 } else { 490 if (mode == SCALE_UP) { 491 if (vsu_mode == SCALE_UP_BIL) 492 val = GET_SCL_FT_BILI_UP(src, dst); 493 else 494 val = GET_SCL_FT_BIC(src, dst); 495 } else if (mode == SCALE_DOWN) { 496 if (vskiplines) { 497 *vskiplines = scl_get_vskiplines(src, dst); 498 val = scl_get_bili_dn_vskip(src, dst, 499 *vskiplines); 500 } else { 501 val = GET_SCL_FT_BILI_DN(src, dst); 502 } 503 } 504 } 505 506 return val; 507 } 508 509 static void scl_vop_cal_scl_fac(struct vop *vop, 510 uint32_t src_w, uint32_t src_h, uint32_t dst_w, 511 uint32_t dst_h, uint32_t pixel_format) 512 { 513 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode; 514 uint16_t cbcr_hor_scl_mode = SCALE_NONE; 515 uint16_t cbcr_ver_scl_mode = SCALE_NONE; 516 int hsub = drm_format_horz_chroma_subsampling(pixel_format); 517 int vsub = drm_format_vert_chroma_subsampling(pixel_format); 518 bool is_yuv = false; 519 uint16_t cbcr_src_w = src_w / hsub; 520 uint16_t cbcr_src_h = src_h / vsub; 521 uint16_t vsu_mode; 522 uint16_t lb_mode; 523 uint32_t val; 524 int vskiplines = 0; 525 526 if (!vop->win->scl) 527 return; 528 529 if (!vop->win->scl->ext) { 530 VOP_SCL_SET(vop, scale_yrgb_x, 531 scl_cal_scale2(src_w, dst_w)); 532 VOP_SCL_SET(vop, scale_yrgb_y, 533 scl_cal_scale2(src_h, dst_h)); 534 if (is_yuv) { 535 VOP_SCL_SET(vop, scale_cbcr_x, 536 scl_cal_scale2(src_w, dst_w)); 537 VOP_SCL_SET(vop, scale_cbcr_y, 538 scl_cal_scale2(src_h, dst_h)); 539 } 540 return; 541 } 542 543 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w); 544 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h); 545 546 if (is_yuv) { 547 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w); 548 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h); 549 if (cbcr_hor_scl_mode == SCALE_DOWN) 550 lb_mode = scl_vop_cal_lb_mode(dst_w, true); 551 else 552 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true); 553 } else { 554 if (yrgb_hor_scl_mode == SCALE_DOWN) 555 lb_mode = scl_vop_cal_lb_mode(dst_w, false); 556 else 557 lb_mode = scl_vop_cal_lb_mode(src_w, false); 558 } 559 560 VOP_SCL_SET_EXT(vop, lb_mode, lb_mode); 561 if (lb_mode == LB_RGB_3840X2) { 562 if (yrgb_ver_scl_mode != SCALE_NONE) { 563 printf("ERROR : not allow yrgb ver scale\n"); 564 return; 565 } 566 if (cbcr_ver_scl_mode != SCALE_NONE) { 567 printf("ERROR : not allow cbcr ver scale\n"); 568 return; 569 } 570 vsu_mode = SCALE_UP_BIL; 571 } else if (lb_mode == LB_RGB_2560X4) { 572 vsu_mode = SCALE_UP_BIL; 573 } else { 574 vsu_mode = SCALE_UP_BIC; 575 } 576 577 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w, 578 true, 0, NULL); 579 VOP_SCL_SET(vop, scale_yrgb_x, val); 580 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h, 581 false, vsu_mode, &vskiplines); 582 VOP_SCL_SET(vop, scale_yrgb_y, val); 583 584 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt4, vskiplines == 4); 585 VOP_SCL_SET_EXT(vop, vsd_yrgb_gt2, vskiplines == 2); 586 587 VOP_SCL_SET_EXT(vop, yrgb_hor_scl_mode, yrgb_hor_scl_mode); 588 VOP_SCL_SET_EXT(vop, yrgb_ver_scl_mode, yrgb_ver_scl_mode); 589 VOP_SCL_SET_EXT(vop, yrgb_hsd_mode, SCALE_DOWN_BIL); 590 VOP_SCL_SET_EXT(vop, yrgb_vsd_mode, SCALE_DOWN_BIL); 591 VOP_SCL_SET_EXT(vop, yrgb_vsu_mode, vsu_mode); 592 if (is_yuv) { 593 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w, 594 dst_w, true, 0, NULL); 595 VOP_SCL_SET(vop, scale_cbcr_x, val); 596 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h, 597 dst_h, false, vsu_mode, &vskiplines); 598 VOP_SCL_SET(vop, scale_cbcr_y, val); 599 600 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt4, vskiplines == 4); 601 VOP_SCL_SET_EXT(vop, vsd_cbcr_gt2, vskiplines == 2); 602 VOP_SCL_SET_EXT(vop, cbcr_hor_scl_mode, cbcr_hor_scl_mode); 603 VOP_SCL_SET_EXT(vop, cbcr_ver_scl_mode, cbcr_ver_scl_mode); 604 VOP_SCL_SET_EXT(vop, cbcr_hsd_mode, SCALE_DOWN_BIL); 605 VOP_SCL_SET_EXT(vop, cbcr_vsd_mode, SCALE_DOWN_BIL); 606 VOP_SCL_SET_EXT(vop, cbcr_vsu_mode, vsu_mode); 607 } 608 } 609 610 static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table) 611 { 612 int i; 613 614 /* 615 * so far the csc offset is not 0 and in the feature the csc offset 616 * impossible be 0, so when the offset is 0, should return here. 617 */ 618 if (!table || offset == 0) 619 return; 620 621 for (i = 0; i < 8; i++) 622 vop_writel(vop, offset + i * 4, table[i]); 623 } 624 625 static int rockchip_vop_setup_csc_table(struct display_state *state) 626 { 627 struct crtc_state *crtc_state = &state->crtc_state; 628 struct connector_state *conn_state = &state->conn_state; 629 struct vop *vop = crtc_state->private; 630 const uint32_t *csc_table = NULL; 631 632 if (!vop->csc_table || !crtc_state->yuv_overlay) 633 return 0; 634 /* todo: only implement r2y*/ 635 switch (conn_state->color_space) { 636 case V4L2_COLORSPACE_SMPTE170M: 637 csc_table = vop->csc_table->r2y_bt601_12_235; 638 break; 639 case V4L2_COLORSPACE_REC709: 640 case V4L2_COLORSPACE_DEFAULT: 641 case V4L2_COLORSPACE_JPEG: 642 csc_table = vop->csc_table->r2y_bt709; 643 break; 644 case V4L2_COLORSPACE_BT2020: 645 csc_table = vop->csc_table->r2y_bt2020; 646 break; 647 default: 648 csc_table = vop->csc_table->r2y_bt601; 649 break; 650 } 651 652 vop_load_csc_table(vop, vop->win_csc->r2y_offset, csc_table); 653 VOP_WIN_CSC_SET(vop, r2y_en, 1); 654 655 return 0; 656 } 657 658 static int rockchip_vop_set_plane(struct display_state *state) 659 { 660 struct crtc_state *crtc_state = &state->crtc_state; 661 const struct rockchip_crtc *crtc = crtc_state->crtc; 662 const struct vop_data *vop_data = crtc->data; 663 struct connector_state *conn_state = &state->conn_state; 664 struct drm_display_mode *mode = &conn_state->mode; 665 u32 act_info, dsp_info, dsp_st, dsp_stx, dsp_sty; 666 struct vop *vop = crtc_state->private; 667 int src_w = crtc_state->src_w; 668 int src_h = crtc_state->src_h; 669 int crtc_x = crtc_state->crtc_x; 670 int crtc_y = crtc_state->crtc_y; 671 int crtc_w = crtc_state->crtc_w; 672 int crtc_h = crtc_state->crtc_h; 673 int xvir = crtc_state->xvir; 674 int x_mirror = 0, y_mirror = 0; 675 676 if (crtc_w > crtc_state->max_output.width) { 677 printf("ERROR: output w[%d] exceeded max width[%d]\n", 678 crtc_w, crtc_state->max_output.width); 679 return -EINVAL; 680 } 681 682 act_info = (src_h - 1) << 16; 683 act_info |= (src_w - 1) & 0xffff; 684 685 dsp_info = (crtc_h - 1) << 16; 686 dsp_info |= (crtc_w - 1) & 0xffff; 687 688 dsp_stx = crtc_x + mode->crtc_htotal - mode->crtc_hsync_start; 689 dsp_sty = crtc_y + mode->crtc_vtotal - mode->crtc_vsync_start; 690 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff); 691 /* 692 * vop full need to treats rgb888 as bgr888 so we reverse the rb swap to workaround 693 */ 694 if (crtc_state->format == ROCKCHIP_FMT_RGB888 && VOP_MAJOR(vop_data->version) == 3) 695 crtc_state->rb_swap = !crtc_state->rb_swap; 696 697 if (mode->flags & DRM_MODE_FLAG_YMIRROR) 698 y_mirror = 1; 699 else 700 y_mirror = 0; 701 if (mode->flags & DRM_MODE_FLAG_XMIRROR) 702 x_mirror = 1; 703 else 704 x_mirror = 0; 705 if (crtc_state->ymirror ^ y_mirror) 706 y_mirror = 1; 707 else 708 y_mirror = 0; 709 if (y_mirror) { 710 if (VOP_CTRL_SUPPORT(vop, ymirror)) 711 crtc_state->dma_addr += (src_h - 1) * xvir * 4; 712 else 713 y_mirror = 0; 714 } 715 VOP_CTRL_SET(vop, ymirror, y_mirror); 716 VOP_CTRL_SET(vop, xmirror, x_mirror); 717 718 VOP_WIN_SET(vop, format, crtc_state->format); 719 VOP_WIN_SET(vop, yrgb_vir, xvir); 720 VOP_WIN_SET(vop, yrgb_mst, crtc_state->dma_addr); 721 722 scl_vop_cal_scl_fac(vop, src_w, src_h, crtc_w, crtc_h, 723 crtc_state->format); 724 725 VOP_WIN_SET(vop, act_info, act_info); 726 VOP_WIN_SET(vop, dsp_info, dsp_info); 727 VOP_WIN_SET(vop, dsp_st, dsp_st); 728 VOP_WIN_SET(vop, rb_swap, crtc_state->rb_swap); 729 730 VOP_WIN_SET(vop, src_alpha_ctl, 0); 731 732 rockchip_vop_setup_csc_table(state); 733 VOP_WIN_SET(vop, enable, 1); 734 VOP_WIN_SET(vop, gate, 1); 735 vop_cfg_done(vop); 736 737 return 0; 738 } 739 740 static int rockchip_vop_prepare(struct display_state *state) 741 { 742 return 0; 743 } 744 745 static int rockchip_vop_enable(struct display_state *state) 746 { 747 struct crtc_state *crtc_state = &state->crtc_state; 748 struct vop *vop = crtc_state->private; 749 750 VOP_CTRL_SET(vop, standby, 0); 751 vop_cfg_done(vop); 752 if (crtc_state->mcu_timing.mcu_pix_total > 0) 753 VOP_CTRL_SET(vop, mcu_hold_mode, 0); 754 755 return 0; 756 } 757 758 static int rockchip_vop_disable(struct display_state *state) 759 { 760 struct crtc_state *crtc_state = &state->crtc_state; 761 struct vop *vop = crtc_state->private; 762 763 VOP_CTRL_SET(vop, standby, 1); 764 vop_cfg_done(vop); 765 return 0; 766 } 767 768 static int rockchip_vop_fixup_dts(struct display_state *state, void *blob) 769 { 770 #if 0 771 struct crtc_state *crtc_state = &state->crtc_state; 772 struct panel_state *pstate = &state->panel_state; 773 uint32_t phandle; 774 char path[100]; 775 int ret, dsp_lut_node; 776 777 if (!ofnode_valid(pstate->dsp_lut_node)) 778 return 0; 779 ret = fdt_get_path(state->blob, pstate->dsp_lut_node, path, sizeof(path)); 780 if (ret < 0) { 781 printf("failed to get dsp_lut path[%s], ret=%d\n", 782 path, ret); 783 return ret; 784 } 785 786 dsp_lut_node = fdt_path_offset(blob, path); 787 phandle = fdt_get_phandle(blob, dsp_lut_node); 788 if (!phandle) { 789 phandle = fdt_alloc_phandle(blob); 790 if (!phandle) { 791 printf("failed to alloc phandle\n"); 792 return -ENOMEM; 793 } 794 795 fdt_set_phandle(blob, dsp_lut_node, phandle); 796 } 797 798 ret = fdt_get_path(state->blob, crtc_state->node, path, sizeof(path)); 799 if (ret < 0) { 800 printf("failed to get route path[%s], ret=%d\n", 801 path, ret); 802 return ret; 803 } 804 805 do_fixup_by_path_u32(blob, path, "dsp-lut", phandle, 1); 806 #endif 807 return 0; 808 } 809 810 static int rockchip_vop_send_mcu_cmd(struct display_state *state, 811 u32 type, u32 value) 812 { 813 struct crtc_state *crtc_state = &state->crtc_state; 814 struct vop *vop = crtc_state->private; 815 816 if (vop) { 817 switch (type) { 818 case MCU_WRCMD: 819 set_vop_mcu_rs(vop, 0); 820 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value); 821 set_vop_mcu_rs(vop, 1); 822 break; 823 case MCU_WRDATA: 824 set_vop_mcu_rs(vop, 1); 825 VOP_CTRL_SET(vop, mcu_rw_bypass_port, value); 826 break; 827 case MCU_SETBYPASS: 828 VOP_CTRL_SET(vop, mcu_bypass, value ? 1 : 0); 829 break; 830 default: 831 break; 832 } 833 } 834 835 return 0; 836 } 837 838 const struct rockchip_crtc_funcs rockchip_vop_funcs = { 839 .preinit = rockchip_vop_preinit, 840 .init = rockchip_vop_init, 841 .set_plane = rockchip_vop_set_plane, 842 .prepare = rockchip_vop_prepare, 843 .enable = rockchip_vop_enable, 844 .disable = rockchip_vop_disable, 845 .fixup_dts = rockchip_vop_fixup_dts, 846 .send_mcu_cmd = rockchip_vop_send_mcu_cmd, 847 }; 848