1 /* 2 * SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 #include <common.h> 6 #include <malloc.h> 7 #include <fdtdec.h> 8 #include <fdt_support.h> 9 #include <asm/io.h> 10 #include <linux/media-bus-format.h> 11 #include <asm/arch-rockchip/clock.h> 12 #include <dm/device.h> 13 #include <dm/read.h> 14 #include <dm/uclass-internal.h> 15 #include <linux/fb.h> 16 #include <edid.h> 17 #include <syscon.h> 18 #include <boot_rkimg.h> 19 #include <mapmem.h> 20 #include <misc.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "rockchip_phy.h" 26 #include "rockchip_tve.h" 27 28 #define RK322X_VDAC_STANDARD 0x15 29 30 static const struct drm_display_mode tve_modes[] = { 31 /* 0 - 720x576i@50Hz */ 32 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 753, 33 816, 864, 576, 580, 586, 625, 0, 34 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 35 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 36 .vrefresh = 50, }, 37 /* 1 - 720x480i@60Hz */ 38 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 753, 39 815, 858, 480, 483, 486, 525, 0, 40 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 41 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 42 .vrefresh = 60, }, 43 }; 44 45 struct env_config { 46 u32 offset; 47 u32 value; 48 }; 49 50 static struct env_config ntsc_bt656_config[] = { 51 { BT656_DECODER_CROP, 0x00000000 }, 52 { BT656_DECODER_SIZE, 0x01e002d0 }, 53 { BT656_DECODER_HTOTAL_HS_END, 0x035a003e }, 54 { BT656_DECODER_VACT_ST_HACT_ST, 0x00160069 }, 55 { BT656_DECODER_VTOTAL_VS_END, 0x020d0003 }, 56 { BT656_DECODER_VS_ST_END_F1, 0x01060109 }, 57 { BT656_DECODER_DBG_REG, 0x024002d0 }, 58 { BT656_DECODER_CTRL, 0x00000009 }, 59 }; 60 61 static struct env_config ntsc_tve_config[] = { 62 { TVE_MODE_CTRL, 0x000af906 }, 63 { TVE_HOR_TIMING1, 0x00c07a81 }, 64 { TVE_HOR_TIMING2, 0x169810fc }, 65 { TVE_HOR_TIMING3, 0x96b40000 }, 66 { TVE_SUB_CAR_FRQ, 0x21f07bd7 }, 67 { TVE_IMAGE_POSITION, 0x001500d6 }, 68 { TVE_ROUTING, 0x10088880 }, 69 { TVE_SYNC_ADJUST, 0x00000000 }, 70 { TVE_STATUS, 0x00000000 }, 71 { TVE_CTRL, 0x00000000 }, 72 { TVE_INTR_STATUS, 0x00000000 }, 73 { TVE_INTR_EN, 0x00000000 }, 74 { TVE_INTR_CLR, 0x00000000 }, 75 { TVE_COLOR_BUSRT_SAT, 0x0052543c }, 76 { TVE_CHROMA_BANDWIDTH, 0x00000002 }, 77 { TVE_BRIGHTNESS_CONTRAST, 0x00008300 }, 78 { TVE_CLAMP, 0x00000000 }, 79 }; 80 81 static struct env_config pal_bt656_config[] = { 82 { BT656_DECODER_CROP, 0x00000000 }, 83 { BT656_DECODER_SIZE, 0x024002d0 }, 84 { BT656_DECODER_HTOTAL_HS_END, 0x0360003f }, 85 { BT656_DECODER_VACT_ST_HACT_ST, 0x0016006f }, 86 { BT656_DECODER_VTOTAL_VS_END, 0x02710003 }, 87 { BT656_DECODER_VS_ST_END_F1, 0x0138013b }, 88 { BT656_DECODER_DBG_REG, 0x024002d0 }, 89 { BT656_DECODER_CTRL, 0x00000009 }, 90 }; 91 92 static struct env_config pal_tve_config[] = { 93 { TVE_MODE_CTRL, 0x010ab906 }, 94 { TVE_HOR_TIMING1, 0x00c28381 }, 95 { TVE_HOR_TIMING2, 0x267d111d }, 96 { TVE_HOR_TIMING3, 0x76c00880 }, 97 { TVE_SUB_CAR_FRQ, 0x2a098acb }, 98 { TVE_IMAGE_POSITION, 0x001500f6 }, 99 { TVE_ROUTING, 0x10008882 }, 100 { TVE_SYNC_ADJUST, 0x00000000 }, 101 { TVE_STATUS, 0x000000b0 }, 102 { TVE_CTRL, 0x00000000 }, 103 { TVE_INTR_STATUS, 0x00000000 }, 104 { TVE_INTR_EN, 0x00000000 }, 105 { TVE_INTR_CLR, 0x00000000 }, 106 { TVE_COLOR_BUSRT_SAT, 0x00366044 }, 107 { TVE_CHROMA_BANDWIDTH, 0x00000022 }, 108 { TVE_BRIGHTNESS_CONTRAST, 0x0000a300 }, 109 { TVE_CLAMP, 0x00000000 }, 110 }; 111 112 #define BT656_ENV_CONFIG_SIZE (sizeof(ntsc_bt656_config) / sizeof(struct env_config)) 113 #define TVE_ENV_CONFIG_SIZE (sizeof(ntsc_tve_config) / sizeof(struct env_config)) 114 115 #define tve_writel(offset, v) writel(v, tve->reg_base + offset) 116 #define tve_readl(offset) readl(tve->reg_base + offset) 117 118 #define tve_dac_writel(offset, v) writel(v, tve->vdac_base + offset) 119 #define tve_dac_readl(offset) readl(tve->vdac_base + offset) 120 121 #define tve_grf_writel(offset, v) writel(v, tve->grf + offset) 122 #define tve_grf_readl(offset, v) readl(tve->grf + offset) 123 124 struct rockchip_tve_data { 125 int input_format; 126 int soc_type; 127 }; 128 129 struct rockchip_tve { 130 struct rockchip_connector connector; 131 struct udevice *dev; 132 void *reg_base; 133 void *vdac_base; 134 int soc_type; 135 int input_format; 136 int tv_format; 137 int test_mode; 138 int saturation; 139 int brightcontrast; 140 int adjtiming; 141 int lumafilter0; 142 int lumafilter1; 143 int lumafilter2; 144 int lumafilter3; 145 int lumafilter4; 146 int lumafilter5; 147 int lumafilter6; 148 int lumafilter7; 149 int daclevel; 150 int dac1level; 151 int preferred_mode; 152 int upsample_mode; 153 void *grf; 154 }; 155 156 static void tve_write_block(struct rockchip_tve *tve, struct env_config *config, int len) 157 { 158 int i; 159 160 for (i = 0; i < len; i++) 161 tve_writel(config[i].offset, config[i].value); 162 } 163 164 static void tve_set_mode(struct rockchip_tve *tve) 165 { 166 struct env_config *bt656_cfg, *tve_cfg; 167 int mode = tve->tv_format; 168 169 if (tve->soc_type == SOC_RK3528) { 170 tve_writel(TVE_LUMA_FILTER1, tve->lumafilter0); 171 tve_writel(TVE_LUMA_FILTER2, tve->lumafilter1); 172 tve_writel(TVE_LUMA_FILTER3, tve->lumafilter2); 173 tve_writel(TVE_LUMA_FILTER4, tve->lumafilter3); 174 tve_writel(TVE_LUMA_FILTER5, tve->lumafilter4); 175 tve_writel(TVE_LUMA_FILTER6, tve->lumafilter5); 176 tve_writel(TVE_LUMA_FILTER7, tve->lumafilter6); 177 tve_writel(TVE_LUMA_FILTER8, tve->lumafilter7); 178 } else { 179 if (tve->input_format == INPUT_FORMAT_RGB) 180 tve_writel(TV_CTRL, v_CVBS_MODE(mode) | v_CLK_UPSTREAM_EN(2) | 181 v_TIMING_EN(2) | v_LUMA_FILTER_GAIN(0) | 182 v_LUMA_FILTER_UPSAMPLE(1) | v_CSC_PATH(0)); 183 else 184 tve_writel(TV_CTRL, v_CVBS_MODE(mode) | v_CLK_UPSTREAM_EN(2) | 185 v_TIMING_EN(2) | v_LUMA_FILTER_GAIN(0) | 186 v_LUMA_FILTER_UPSAMPLE(1) | v_CSC_PATH(3)); 187 188 tve_writel(TV_LUMA_FILTER0, tve->lumafilter0); 189 tve_writel(TV_LUMA_FILTER1, tve->lumafilter1); 190 tve_writel(TV_LUMA_FILTER2, tve->lumafilter2); 191 } 192 193 if (mode == TVOUT_CVBS_NTSC) { 194 TVEDBG("tve set ntsc mode\n"); 195 196 if (tve->soc_type == SOC_RK3528) { 197 bt656_cfg = ntsc_bt656_config; 198 tve_cfg = ntsc_tve_config; 199 200 tve_write_block(tve, bt656_cfg, BT656_ENV_CONFIG_SIZE); 201 tve_write_block(tve, tve_cfg, TVE_ENV_CONFIG_SIZE); 202 } else { 203 tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) | v_Y_IRE_7_5(1) | 204 v_Y_AGC_PULSE_ON(0) | v_Y_VIDEO_ON(1) | 205 v_YPP_MODE(1) | v_Y_SYNC_ON(1) | v_PIC_MODE(mode)); 206 tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_NTSC) | 207 v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3)); 208 tve_writel(TV_SATURATION, 0x0042543C); 209 if (tve->test_mode) 210 tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00008300); 211 else 212 tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00007900); 213 214 tve_writel(TV_FREQ_SC, 0x21F07BD7); 215 tve_writel(TV_SYNC_TIMING, 0x00C07a81); 216 tve_writel(TV_ADJ_TIMING, 0x96B40000 | 0x70); 217 tve_writel(TV_ACT_ST, 0x001500D6); 218 tve_writel(TV_ACT_TIMING, 0x069800FC | (1 << 12) | (1 << 28)); 219 } 220 } else if (mode == TVOUT_CVBS_PAL) { 221 TVEDBG("tve set pal mode\n"); 222 223 if (tve->soc_type == SOC_RK3528) { 224 bt656_cfg = pal_bt656_config; 225 tve_cfg = pal_tve_config; 226 227 tve_write_block(tve, bt656_cfg, BT656_ENV_CONFIG_SIZE); 228 tve_write_block(tve, tve_cfg, TVE_ENV_CONFIG_SIZE); 229 } else { 230 tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) | v_Y_IRE_7_5(0) | 231 v_Y_AGC_PULSE_ON(0) | v_Y_VIDEO_ON(1) | 232 v_YPP_MODE(1) | v_Y_SYNC_ON(1) | v_PIC_MODE(mode)); 233 tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_PAL) | 234 v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3)); 235 236 tve_writel(TV_SATURATION, tve->saturation); 237 tve_writel(TV_BRIGHTNESS_CONTRAST, tve->brightcontrast); 238 239 tve_writel(TV_FREQ_SC, 0x2A098ACB); 240 tve_writel(TV_SYNC_TIMING, 0x00C28381); 241 tve_writel(TV_ADJ_TIMING, (0xc << 28) | 0x06c00800 | 0x80); 242 tve_writel(TV_ACT_ST, 0x001500F6); 243 tve_writel(TV_ACT_TIMING, 0x0694011D | (1 << 12) | (2 << 28)); 244 245 tve_writel(TV_ADJ_TIMING, tve->adjtiming); 246 tve_writel(TV_ACT_TIMING, 0x0694011D | (1 << 12) | (2 << 28)); 247 } 248 } 249 250 if (tve->soc_type == SOC_RK3528) { 251 u32 upsample_mode = 0; 252 u32 mask = 0; 253 u32 val = 0; 254 bool upsample_en; 255 256 upsample_en = tve->upsample_mode ? 1 : 0; 257 if (upsample_en) 258 upsample_mode = tve->upsample_mode - 1; 259 mask = m_TVE_DCLK_POL | m_TVE_DCLK_EN | m_DCLK_UPSAMPLE_2X4X | 260 m_DCLK_UPSAMPLE_EN | m_TVE_MODE | m_TVE_EN; 261 val = v_TVE_DCLK_POL(0) | v_TVE_DCLK_EN(1) | v_DCLK_UPSAMPLE_2X4X(upsample_mode) | 262 v_DCLK_UPSAMPLE_EN(upsample_en) | v_TVE_MODE(tve->tv_format) | v_TVE_EN(1); 263 264 tve_grf_writel(RK3528_VO_GRF_CVBS_CON, (mask << 16) | val); 265 } 266 } 267 268 static void dac_init(struct rockchip_tve *tve) 269 { 270 tve_dac_writel(VDAC_VDAC1, v_CUR_REG(tve->dac1level) | 271 m_DR_PWR_DOWN | m_BG_PWR_DOWN); 272 tve_dac_writel(VDAC_VDAC2, v_CUR_CTR(tve->daclevel)); 273 tve_dac_writel(VDAC_VDAC3, v_CAB_EN(0)); 274 } 275 276 static void dac_enable(struct rockchip_tve *tve, bool enable) 277 { 278 u32 mask = 0; 279 u32 val = 0; 280 u32 grfreg = 0; 281 u32 offset = 0; 282 283 if (enable) { 284 TVEDBG("tve enable\n"); 285 286 if (tve->soc_type == SOC_RK3036) { 287 mask = m_VBG_EN | m_DAC_EN | m_DAC_GAIN; 288 val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve->daclevel); 289 grfreg = RK3036_GRF_SOC_CON3; 290 } else if (tve->soc_type == SOC_RK312X) { 291 mask = m_VBG_EN | m_DAC_EN | m_DAC_GAIN; 292 val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve->daclevel); 293 grfreg = RK312X_GRF_TVE_CON; 294 } else if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) { 295 val = v_CUR_REG(tve->dac1level) | v_DR_PWR_DOWN(0) | v_BG_PWR_DOWN(0); 296 } else if (tve->soc_type == SOC_RK3528) { 297 /* 298 * Reset the vdac 299 */ 300 tve_dac_writel(VDAC_CLK_RST, v_ANALOG_RST(0) | v_DIGITAL_RST(0)); 301 mdelay(20); 302 tve_dac_writel(VDAC_CLK_RST, v_ANALOG_RST(1) | v_DIGITAL_RST(1)); 303 304 val = v_REF_VOLTAGE(7) | v_DAC_PWN(1) | v_BIAS_PWN(1); 305 offset = VDAC_PWM_REF_CTRL; 306 } 307 } else { 308 TVEDBG("tve disable\n"); 309 310 if (tve->soc_type == SOC_RK312X) { 311 mask = m_VBG_EN | m_DAC_EN; 312 grfreg = RK312X_GRF_TVE_CON; 313 } else if (tve->soc_type == SOC_RK3036) { 314 mask = m_VBG_EN | m_DAC_EN; 315 grfreg = RK3036_GRF_SOC_CON3; 316 } else if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) { 317 val = v_CUR_REG(tve->dac1level) | m_DR_PWR_DOWN | m_BG_PWR_DOWN; 318 offset = VDAC_VDAC1; 319 } else if (tve->soc_type == SOC_RK3528) { 320 val = v_DAC_PWN(0) | v_BIAS_PWN(0); 321 offset = VDAC_PWM_REF_CTRL; 322 } 323 } 324 325 if (grfreg) 326 tve_grf_writel(grfreg, (mask << 16) | val); 327 else if (tve->vdac_base) 328 tve_dac_writel(offset, val); 329 } 330 331 static u8 rk_get_vdac_value(void) 332 { 333 u8 value = 0; 334 #ifdef CONFIG_ROCKCHIP_EFUSE 335 #if defined(CONFIG_ROCKCHIP_RK322X) 336 struct udevice *dev; 337 u32 regs[2] = {0}; 338 u8 fuses[1]; 339 ofnode node; 340 int ret; 341 342 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(rockchip_efuse), &dev); 343 if (ret) { 344 printf("%s: no misc-device found\n", __func__); 345 return -EINVAL; 346 } 347 348 node = dev_read_subnode(dev, "tve_dac"); 349 if (!ofnode_valid(node)) 350 return -EINVAL; 351 352 ret = ofnode_read_u32_array(node, "reg", regs, 2); 353 if (ret) { 354 printf("Cannot get efuse reg\n"); 355 return -EINVAL; 356 } 357 358 ret = misc_read(dev, regs[0], &fuses, regs[1]); 359 if (ret) { 360 printf("%s: misc_read failed\n", __func__); 361 return 0; 362 } 363 364 value = fuses[0]; 365 value = (value >> 3) & 0x1f; 366 #endif 367 #endif /* CONFIG_RK_EFUSE */ 368 if (value > 0) 369 value += 5; 370 TVEDBG("%s value = 0x%x\n", __func__, value); 371 372 return value; 373 } 374 375 static int tve_parse_dt(struct rockchip_tve *tve) 376 { 377 tve->preferred_mode = dev_read_u32_default(tve->dev, "rockchip,tvemode", -1); 378 if (tve->preferred_mode < 0) { 379 tve->preferred_mode = 0; 380 } else if (tve->preferred_mode > 1) { 381 printf("tve mode value invalid\n"); 382 return -EINVAL; 383 } 384 385 tve->lumafilter0 = dev_read_u32_default(tve->dev, "rockchip,lumafilter0", 0); 386 if (tve->lumafilter0 == 0) { 387 printf("tve get lumafilter0 err\n"); 388 return -EINVAL; 389 } 390 391 tve->lumafilter1 = dev_read_u32_default(tve->dev, "rockchip,lumafilter1", 0); 392 if (tve->lumafilter1 == 0) { 393 printf("tve get lumafilter1 err\n"); 394 return -EINVAL; 395 } 396 397 tve->lumafilter2 = dev_read_u32_default(tve->dev, "rockchip,lumafilter2", 0); 398 if (tve->lumafilter2 == 0) { 399 printf("tve get lumafilter2 err\n"); 400 return -EINVAL; 401 } 402 403 tve->lumafilter3 = dev_read_u32_default(tve->dev, "rockchip,lumafilter3", 0); 404 if (tve->lumafilter3 == 0) { 405 printf("tve get lumafilter3 err\n"); 406 return -EINVAL; 407 } 408 409 tve->lumafilter4 = dev_read_u32_default(tve->dev, "rockchip,lumafilter4", 0); 410 if (tve->lumafilter4 == 0) { 411 printf("tve get lumafilter4 err\n"); 412 return -EINVAL; 413 } 414 415 tve->lumafilter5 = dev_read_u32_default(tve->dev, "rockchip,lumafilter5", 0); 416 if (tve->lumafilter5 == 0) { 417 printf("tve get lumafilter5 err\n"); 418 return -EINVAL; 419 } 420 421 tve->lumafilter6 = dev_read_u32_default(tve->dev, "rockchip,lumafilter6", 0); 422 if (tve->lumafilter6 == 0) { 423 printf("tve get lumafilter6 err\n"); 424 return -EINVAL; 425 } 426 427 tve->lumafilter7 = dev_read_u32_default(tve->dev, "rockchip,lumafilter7", 0); 428 if (tve->lumafilter7 == 0) { 429 printf("tve get lumafilter7 err\n"); 430 return -EINVAL; 431 } 432 433 tve->upsample_mode = dev_read_u32_default(tve->dev, "rockchip,tve-upsample", -1); 434 if (tve->upsample_mode < 0 || tve->upsample_mode > DCLK_UPSAMPLEx4) { 435 printf("tve get upsample_mode err\n"); 436 return -EINVAL; 437 } 438 439 TVEDBG("tve->preferred_mode = 0x%x\n", tve->preferred_mode); 440 TVEDBG("tve->lumafilter0 = 0x%x\n", tve->lumafilter0); 441 TVEDBG("tve->lumafilter1 = 0x%x\n", tve->lumafilter1); 442 TVEDBG("tve->lumafilter2 = 0x%x\n", tve->lumafilter2); 443 TVEDBG("tve->lumafilter3 = 0x%x\n", tve->lumafilter3); 444 TVEDBG("tve->lumafilter4 = 0x%x\n", tve->lumafilter4); 445 TVEDBG("tve->lumafilter5 = 0x%x\n", tve->lumafilter5); 446 TVEDBG("tve->lumafilter6 = 0x%x\n", tve->lumafilter6); 447 TVEDBG("tve->lumafilter7 = 0x%x\n", tve->lumafilter7); 448 TVEDBG("tve->upsample_mode = 0x%x\n", tve->upsample_mode); 449 450 return 0; 451 } 452 453 static int tve_parse_dt_legacy(struct rockchip_tve *tve) 454 { 455 int dac_value, getvdac; 456 457 if (tve->soc_type == SOC_RK312X) 458 tve->test_mode = dev_read_u32_default(tve->dev, "test_mode", 0); 459 460 tve->preferred_mode = dev_read_u32_default(tve->dev, "rockchip,tvemode", -1); 461 if (tve->preferred_mode < 0) { 462 tve->preferred_mode = 0; 463 } else if (tve->preferred_mode > 1) { 464 printf("tve mode value invalid\n"); 465 return -EINVAL; 466 } 467 468 tve->saturation = dev_read_u32_default(tve->dev, "rockchip,saturation", 0); 469 if (tve->saturation == 0) { 470 printf("tve get saturation err\n"); 471 return -EINVAL; 472 } 473 474 tve->brightcontrast = dev_read_u32_default(tve->dev, "rockchip,brightcontrast", 0); 475 if (tve->brightcontrast == 0) { 476 printf("tve get brightcontrast err\n"); 477 return -EINVAL; 478 } 479 480 tve->adjtiming = dev_read_u32_default(tve->dev, "rockchip,adjtiming", 0); 481 if (tve->adjtiming == 0) { 482 printf("tve get adjtiming err\n"); 483 return -EINVAL; 484 } 485 486 tve->lumafilter0 = dev_read_u32_default(tve->dev, "rockchip,lumafilter0", 0); 487 if (tve->lumafilter0 == 0) { 488 printf("tve get lumafilter0 err\n"); 489 return -EINVAL; 490 } 491 492 tve->lumafilter1 = dev_read_u32_default(tve->dev, "rockchip,lumafilter1", 0); 493 if (tve->lumafilter1 == 0) { 494 printf("tve get lumafilter1 err\n"); 495 return -EINVAL; 496 } 497 498 tve->lumafilter2 = dev_read_u32_default(tve->dev, "rockchip,lumafilter2", 0); 499 if (tve->lumafilter2 == 0) { 500 printf("tve get lumafilter2 err\n"); 501 return -EINVAL; 502 } 503 504 dac_value = dev_read_u32_default(tve->dev, "rockchip,daclevel", 0); 505 if (dac_value == 0) { 506 printf("tve get dac_value err\n"); 507 return -EINVAL; 508 } 509 510 tve->daclevel = dac_value; 511 if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) { 512 getvdac = rk_get_vdac_value(); 513 if (getvdac > 0) { 514 tve->daclevel = dac_value + getvdac - RK322X_VDAC_STANDARD; 515 if (tve->daclevel > 0x3f || tve->daclevel < 0) { 516 printf("rk322x daclevel error!\n"); 517 tve->daclevel = dac_value; 518 } 519 } else if (getvdac < 0) { 520 printf("get rk322x daclevel error\n"); 521 return -EINVAL; 522 } 523 } 524 525 if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) { 526 tve->dac1level = dev_read_u32_default(tve->dev, "rockchip,dac1level", 0); 527 if (tve->dac1level == 0) { 528 printf("rk322x dac1level error!\n"); 529 return -EINVAL; 530 } 531 } 532 533 TVEDBG("tve->test_mode = 0x%x\n", tve->test_mode); 534 TVEDBG("tve->saturation = 0x%x\n", tve->saturation); 535 TVEDBG("tve->brightcontrast = 0x%x\n", tve->brightcontrast); 536 TVEDBG("tve->adjtiming = 0x%x\n", tve->adjtiming); 537 TVEDBG("tve->lumafilter0 = 0x%x\n", tve->lumafilter0); 538 TVEDBG("tve->lumafilter1 = 0x%x\n", tve->lumafilter1); 539 TVEDBG("tve->lumafilter2 = 0x%x\n", tve->lumafilter2); 540 TVEDBG("tve->daclevel = 0x%x\n", tve->daclevel); 541 542 return 0; 543 } 544 545 static int rockchip_drm_tve_init(struct rockchip_connector *conn, struct display_state *state) 546 { 547 struct rockchip_tve *tve = dev_get_priv(conn->dev); 548 struct connector_state *conn_state = &state->conn_state; 549 fdt_addr_t addr; 550 int ret; 551 552 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 553 conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24; 554 if (tve->soc_type == SOC_RK3528) 555 conn_state->output_if |= VOP_OUTPUT_IF_BT656; 556 conn_state->color_space = V4L2_COLORSPACE_SMPTE170M; 557 558 if (tve->soc_type == SOC_RK3528) 559 ret = tve_parse_dt(tve); 560 else 561 ret = tve_parse_dt_legacy(tve); 562 if (ret) { 563 printf("tve parse dts error\n"); 564 return -EINVAL; 565 } 566 567 addr = dev_read_addr_index(conn->dev, 0); 568 if (addr == FDT_ADDR_T_NONE) { 569 printf("failed to get tve reg_base\n"); 570 return -EINVAL; 571 } 572 tve->reg_base = (void *)addr; 573 574 if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328 || 575 tve->soc_type == SOC_RK3528) { 576 addr = dev_read_addr_index(conn->dev, 1); 577 if (addr == FDT_ADDR_T_NONE) { 578 printf("failed to get tve vdac_base\n"); 579 return -EINVAL; 580 } 581 tve->vdac_base = (void *)addr; 582 } 583 584 tve->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 585 586 if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) 587 dac_init(tve); 588 589 return 0; 590 } 591 592 static int rockchip_drm_tve_enable(struct rockchip_connector *conn, struct display_state *state) 593 { 594 struct rockchip_tve *tve = dev_get_priv(conn->dev); 595 struct connector_state *conn_state = &state->conn_state; 596 struct drm_display_mode *mode = &conn_state->mode; 597 598 #ifdef CONFIG_ROCKCHIP_INNO_HDMI_PHY 599 /* set inno hdmi phy clk. */ 600 if (tve->soc_type != SOC_RK3528) 601 rockchip_phy_set_pll(conn->phy, 27000000); 602 #endif 603 if (mode->vdisplay == 576) 604 tve->tv_format = TVOUT_CVBS_PAL; 605 else 606 tve->tv_format = TVOUT_CVBS_NTSC; 607 608 tve_set_mode(tve); 609 mdelay(1000); 610 dac_enable(tve, true); 611 612 return 0; 613 } 614 615 static void rockchip_drm_tve_deinit(struct rockchip_connector *conn, struct display_state *state) 616 { 617 struct rockchip_tve *tve = dev_get_priv(conn->dev); 618 619 dac_enable(tve, false); 620 } 621 622 static int rockchip_drm_tve_prepare(struct rockchip_connector *conn, struct display_state *state) 623 { 624 return 0; 625 } 626 627 static int rockchip_drm_tve_disable(struct rockchip_connector *conn, struct display_state *state) 628 { 629 struct rockchip_tve *tve = dev_get_priv(conn->dev); 630 631 dac_enable(tve, false); 632 633 return 0; 634 } 635 636 static int rockchip_drm_tve_detect(struct rockchip_connector *conn, struct display_state *state) 637 { 638 return 1; 639 } 640 641 static void tve_selete_output(struct rockchip_tve *tve, struct overscan *overscan, 642 struct drm_display_mode *mode) 643 { 644 int ret, i, screen_size; 645 struct base_screen_info *screen_info = NULL; 646 struct base_disp_info base_parameter; 647 struct drm_display_mode modes[2]; 648 const struct base_overscan *scan; 649 char baseparameter_buf[8 * RK_BLK_SIZE] __aligned(ARCH_DMA_MINALIGN); 650 struct blk_desc *dev_desc; 651 disk_partition_t part_info; 652 int max_scan = 100; 653 int min_scan = 50; 654 655 for (i = 0; i < 2; i++) { 656 modes[i] = tve_modes[i]; 657 if (i == tve->preferred_mode) 658 modes[i].type |= DRM_MODE_TYPE_PREFERRED; 659 } 660 *mode = modes[tve->preferred_mode]; 661 662 dev_desc = rockchip_get_bootdev(); 663 if (!dev_desc) { 664 printf("%s: Could not find device\n", __func__); 665 return; 666 } 667 668 if (part_get_info_by_name(dev_desc, "baseparameter", &part_info) < 0) { 669 printf("Could not find baseparameter partition\n"); 670 return; 671 } 672 673 ret = blk_dread(dev_desc, part_info.start, 1, (void *)baseparameter_buf); 674 if (ret < 0) { 675 printf("read baseparameter failed\n"); 676 return; 677 } 678 679 memcpy(&base_parameter, baseparameter_buf, sizeof(base_parameter)); 680 scan = &base_parameter.scan; 681 682 screen_size = sizeof(base_parameter.screen_list) / sizeof(base_parameter.screen_list[0]); 683 684 for (i = 0; i < screen_size; i++) { 685 if (base_parameter.screen_list[i].type == DRM_MODE_CONNECTOR_TV) { 686 screen_info = &base_parameter.screen_list[i]; 687 break; 688 } 689 } 690 691 if (scan->leftscale < min_scan || scan->leftscale > max_scan) 692 overscan->left_margin = max_scan; 693 else 694 overscan->left_margin = scan->leftscale; 695 696 if (scan->rightscale < min_scan || scan->rightscale > max_scan) 697 overscan->right_margin = max_scan; 698 else 699 overscan->right_margin = scan->rightscale; 700 701 if (scan->topscale < min_scan || scan->topscale > max_scan) 702 overscan->top_margin = max_scan; 703 else 704 overscan->top_margin = scan->topscale; 705 706 if (scan->bottomscale < min_scan || scan->bottomscale > max_scan) 707 overscan->bottom_margin = max_scan; 708 else 709 overscan->bottom_margin = scan->bottomscale; 710 711 if (screen_info && 712 (screen_info->mode.hdisplay == 720 && 713 screen_info->mode.vdisplay == 576)) 714 *mode = modes[0]; 715 else if (screen_info && 716 (screen_info->mode.hdisplay == 720 && 717 screen_info->mode.vdisplay == 480)) 718 *mode = modes[1]; 719 720 if (screen_info) 721 printf("base_parameter mode: %dx%d\n", 722 screen_info->mode.hdisplay, screen_info->mode.vdisplay); 723 } 724 725 static int rockchip_drm_tve_get_timing(struct rockchip_connector *conn, struct display_state *state) 726 { 727 struct rockchip_tve *tve = dev_get_priv(conn->dev); 728 struct connector_state *conn_state = &state->conn_state; 729 struct drm_display_mode *mode = &conn_state->mode; 730 731 tve_selete_output(tve, &conn_state->overscan, mode); 732 733 return 0; 734 } 735 736 const struct rockchip_connector_funcs rockchip_drm_tve_funcs = { 737 .init = rockchip_drm_tve_init, 738 .deinit = rockchip_drm_tve_deinit, 739 .prepare = rockchip_drm_tve_prepare, 740 .enable = rockchip_drm_tve_enable, 741 .disable = rockchip_drm_tve_disable, 742 .get_timing = rockchip_drm_tve_get_timing, 743 .detect = rockchip_drm_tve_detect, 744 }; 745 746 static int rockchip_drm_tve_probe(struct udevice *dev) 747 { 748 struct rockchip_tve *tve = dev_get_priv(dev); 749 const struct rockchip_tve_data *data; 750 751 tve->dev = dev; 752 data = (const struct rockchip_tve_data *)dev_get_driver_data(dev); 753 tve->soc_type = data->soc_type; 754 tve->input_format = data->input_format; 755 756 rockchip_connector_bind(&tve->connector, dev, 0, &rockchip_drm_tve_funcs, NULL, DRM_MODE_CONNECTOR_TV); 757 758 return 0; 759 } 760 761 static const struct rockchip_tve_data rk3036_tve = { 762 .soc_type = SOC_RK3036, 763 .input_format = INPUT_FORMAT_RGB, 764 }; 765 766 static const struct rockchip_tve_data rk312x_tve = { 767 .soc_type = SOC_RK312X, 768 .input_format = INPUT_FORMAT_RGB, 769 }; 770 771 static const struct rockchip_tve_data rk322x_tve = { 772 .soc_type = SOC_RK322X, 773 .input_format = INPUT_FORMAT_YUV, 774 }; 775 776 static const struct rockchip_tve_data rk3328_tve = { 777 .soc_type = SOC_RK3328, 778 .input_format = INPUT_FORMAT_YUV, 779 }; 780 781 static const struct rockchip_tve_data rk3528_tve = { 782 .soc_type = SOC_RK3528, 783 .input_format = INPUT_FORMAT_YUV, 784 }; 785 786 static const struct udevice_id rockchip_drm_tve_ids[] = { 787 { .compatible = "rockchip,rk3036-tve", .data = (ulong)&rk3036_tve }, 788 { .compatible = "rockchip,rk312x-tve", .data = (ulong)&rk312x_tve }, 789 { .compatible = "rockchip,rk322x-tve", .data = (ulong)&rk322x_tve }, 790 { .compatible = "rockchip,rk3328-tve", .data = (ulong)&rk3328_tve }, 791 { .compatible = "rockchip,rk3528-tve", .data = (ulong)&rk3528_tve }, 792 }; 793 794 U_BOOT_DRIVER(rockchip_drm_tve) = { 795 .name = "rockchip_drm_tve", 796 .id = UCLASS_DISPLAY, 797 .of_match = rockchip_drm_tve_ids, 798 .probe = rockchip_drm_tve_probe, 799 .priv_auto_alloc_size = sizeof(struct rockchip_tve), 800 }; 801