1 /* 2 * SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 #include <common.h> 6 #include <malloc.h> 7 #include <fdtdec.h> 8 #include <fdt_support.h> 9 #include <asm/io.h> 10 #include <linux/media-bus-format.h> 11 #include <asm/arch-rockchip/clock.h> 12 #include <dm/device.h> 13 #include <dm/read.h> 14 #include <dm/uclass-internal.h> 15 #include <linux/fb.h> 16 #include <edid.h> 17 #include <syscon.h> 18 #include <boot_rkimg.h> 19 #include <mapmem.h> 20 #include <misc.h> 21 22 #include "rockchip_display.h" 23 #include "rockchip_crtc.h" 24 #include "rockchip_connector.h" 25 #include "rockchip_phy.h" 26 #include "rockchip_tve.h" 27 28 #define RK322X_VDAC_STANDARD 0x15 29 30 static const struct drm_display_mode tve_modes[] = { 31 /* 0 - 720x576i@50Hz */ 32 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 753, 33 816, 864, 576, 580, 586, 625, 0, 34 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 35 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 36 .vrefresh = 50, }, 37 /* 1 - 720x480i@60Hz */ 38 { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 753, 39 815, 858, 480, 483, 486, 525, 0, 40 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 41 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 42 .vrefresh = 60, }, 43 }; 44 45 struct env_config { 46 u32 offset; 47 u32 value; 48 }; 49 50 static struct env_config ntsc_bt656_config[] = { 51 { BT656_DECODER_CROP, 0x00000000 }, 52 { BT656_DECODER_SIZE, 0x01e002d0 }, 53 { BT656_DECODER_HTOTAL_HS_END, 0x035a003e }, 54 { BT656_DECODER_VACT_ST_HACT_ST, 0x00160069 }, 55 { BT656_DECODER_VTOTAL_VS_END, 0x020d0003 }, 56 { BT656_DECODER_VS_ST_END_F1, 0x01060109 }, 57 { BT656_DECODER_DBG_REG, 0x024002d0 }, 58 { BT656_DECODER_CTRL, 0x00000009 }, 59 }; 60 61 static struct env_config ntsc_tve_config[] = { 62 { TVE_MODE_CTRL, 0x000af906 }, 63 { TVE_HOR_TIMING1, 0x00c07a81 }, 64 { TVE_HOR_TIMING2, 0x169810fc }, 65 { TVE_HOR_TIMING3, 0x96b40000 }, 66 { TVE_SUB_CAR_FRQ, 0x21f07bd7 }, 67 { TVE_IMAGE_POSITION, 0x001500d6 }, 68 { TVE_ROUTING, 0x10088880 }, 69 { TVE_SYNC_ADJUST, 0x00000000 }, 70 { TVE_STATUS, 0x00000000 }, 71 { TVE_CTRL, 0x00000000 }, 72 { TVE_INTR_STATUS, 0x00000000 }, 73 { TVE_INTR_EN, 0x00000000 }, 74 { TVE_INTR_CLR, 0x00000000 }, 75 { TVE_COLOR_BUSRT_SAT, 0x0052543c }, 76 { TVE_CHROMA_BANDWIDTH, 0x00000002 }, 77 { TVE_BRIGHTNESS_CONTRAST, 0x00008300 }, 78 { TVE_CLAMP, 0x00000000 }, 79 }; 80 81 static struct env_config pal_bt656_config[] = { 82 { BT656_DECODER_CROP, 0x00000000 }, 83 { BT656_DECODER_SIZE, 0x024002d0 }, 84 { BT656_DECODER_HTOTAL_HS_END, 0x0360003f }, 85 { BT656_DECODER_VACT_ST_HACT_ST, 0x0016006f }, 86 { BT656_DECODER_VTOTAL_VS_END, 0x02710003 }, 87 { BT656_DECODER_VS_ST_END_F1, 0x0138013b }, 88 { BT656_DECODER_DBG_REG, 0x024002d0 }, 89 { BT656_DECODER_CTRL, 0x00000009 }, 90 }; 91 92 static struct env_config pal_tve_config[] = { 93 { TVE_MODE_CTRL, 0x010ab906 }, 94 { TVE_HOR_TIMING1, 0x00c28381 }, 95 { TVE_HOR_TIMING2, 0x267d111d }, 96 { TVE_HOR_TIMING3, 0x66c00880 }, 97 { TVE_SUB_CAR_FRQ, 0x2a098acb }, 98 { TVE_IMAGE_POSITION, 0x001500f6 }, 99 { TVE_ROUTING, 0x10008882 }, 100 { TVE_SYNC_ADJUST, 0x00000000 }, 101 { TVE_STATUS, 0x000000b0 }, 102 { TVE_CTRL, 0x00000000 }, 103 { TVE_INTR_STATUS, 0x00000000 }, 104 { TVE_INTR_EN, 0x00000000 }, 105 { TVE_INTR_CLR, 0x00000000 }, 106 { TVE_COLOR_BUSRT_SAT, 0x00356245 }, 107 { TVE_CHROMA_BANDWIDTH, 0x00000022 }, 108 { TVE_BRIGHTNESS_CONTRAST, 0x0000aa00 }, 109 { TVE_CLAMP, 0x00000000 }, 110 }; 111 112 #define BT656_ENV_CONFIG_SIZE (sizeof(ntsc_bt656_config) / sizeof(struct env_config)) 113 #define TVE_ENV_CONFIG_SIZE (sizeof(ntsc_tve_config) / sizeof(struct env_config)) 114 115 #define tve_writel(offset, v) writel(v, tve->reg_base + offset) 116 #define tve_readl(offset) readl(tve->reg_base + offset) 117 118 #define tve_dac_writel(offset, v) writel(v, tve->vdac_base + offset) 119 #define tve_dac_readl(offset) readl(tve->vdac_base + offset) 120 121 #define tve_grf_writel(offset, v) writel(v, tve->grf + offset) 122 #define tve_grf_readl(offset, v) readl(tve->grf + offset) 123 124 struct rockchip_tve_data { 125 int input_format; 126 int soc_type; 127 }; 128 129 struct rockchip_tve { 130 struct rockchip_connector connector; 131 struct udevice *dev; 132 void *reg_base; 133 void *vdac_base; 134 int soc_type; 135 int input_format; 136 int tv_format; 137 int test_mode; 138 int saturation; 139 int brightcontrast; 140 int adjtiming; 141 int lumafilter0; 142 int lumafilter1; 143 int lumafilter2; 144 int lumafilter3; 145 int lumafilter4; 146 int lumafilter5; 147 int lumafilter6; 148 int lumafilter7; 149 int daclevel; 150 int dac1level; 151 int preferred_mode; 152 int upsample_mode; 153 void *grf; 154 }; 155 156 static void tve_write_block(struct rockchip_tve *tve, struct env_config *config, int len) 157 { 158 int i; 159 160 for (i = 0; i < len; i++) 161 tve_writel(config[i].offset, config[i].value); 162 } 163 164 static void tve_set_mode(struct rockchip_tve *tve) 165 { 166 struct env_config *bt656_cfg, *tve_cfg; 167 int mode = tve->tv_format; 168 169 if (tve->soc_type == SOC_RK3528) { 170 tve_writel(TVE_LUMA_FILTER1, tve->lumafilter0); 171 tve_writel(TVE_LUMA_FILTER2, tve->lumafilter1); 172 tve_writel(TVE_LUMA_FILTER3, tve->lumafilter2); 173 tve_writel(TVE_LUMA_FILTER4, tve->lumafilter3); 174 tve_writel(TVE_LUMA_FILTER5, tve->lumafilter4); 175 tve_writel(TVE_LUMA_FILTER6, tve->lumafilter5); 176 tve_writel(TVE_LUMA_FILTER7, tve->lumafilter6); 177 tve_writel(TVE_LUMA_FILTER8, tve->lumafilter7); 178 } else { 179 if (tve->input_format == INPUT_FORMAT_RGB) 180 tve_writel(TV_CTRL, v_CVBS_MODE(mode) | v_CLK_UPSTREAM_EN(2) | 181 v_TIMING_EN(2) | v_LUMA_FILTER_GAIN(0) | 182 v_LUMA_FILTER_UPSAMPLE(1) | v_CSC_PATH(0)); 183 else 184 tve_writel(TV_CTRL, v_CVBS_MODE(mode) | v_CLK_UPSTREAM_EN(2) | 185 v_TIMING_EN(2) | v_LUMA_FILTER_GAIN(0) | 186 v_LUMA_FILTER_UPSAMPLE(1) | v_CSC_PATH(3)); 187 188 tve_writel(TV_LUMA_FILTER0, tve->lumafilter0); 189 tve_writel(TV_LUMA_FILTER1, tve->lumafilter1); 190 tve_writel(TV_LUMA_FILTER2, tve->lumafilter2); 191 } 192 193 if (mode == TVOUT_CVBS_NTSC) { 194 TVEDBG("tve set ntsc mode\n"); 195 196 if (tve->soc_type == SOC_RK3528) { 197 bt656_cfg = ntsc_bt656_config; 198 tve_cfg = ntsc_tve_config; 199 200 tve_write_block(tve, bt656_cfg, BT656_ENV_CONFIG_SIZE); 201 tve_write_block(tve, tve_cfg, TVE_ENV_CONFIG_SIZE); 202 } else { 203 tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) | v_Y_IRE_7_5(1) | 204 v_Y_AGC_PULSE_ON(0) | v_Y_VIDEO_ON(1) | 205 v_YPP_MODE(1) | v_Y_SYNC_ON(1) | v_PIC_MODE(mode)); 206 tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_NTSC) | 207 v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3)); 208 tve_writel(TV_SATURATION, 0x0042543C); 209 if (tve->test_mode) 210 tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00008300); 211 else 212 tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00007900); 213 214 tve_writel(TV_FREQ_SC, 0x21F07BD7); 215 tve_writel(TV_SYNC_TIMING, 0x00C07a81); 216 tve_writel(TV_ADJ_TIMING, 0x96B40000 | 0x70); 217 tve_writel(TV_ACT_ST, 0x001500D6); 218 tve_writel(TV_ACT_TIMING, 0x069800FC | (1 << 12) | (1 << 28)); 219 } 220 } else if (mode == TVOUT_CVBS_PAL) { 221 TVEDBG("tve set pal mode\n"); 222 223 if (tve->soc_type == SOC_RK3528) { 224 bt656_cfg = pal_bt656_config; 225 tve_cfg = pal_tve_config; 226 227 tve_write_block(tve, bt656_cfg, BT656_ENV_CONFIG_SIZE); 228 tve_write_block(tve, tve_cfg, TVE_ENV_CONFIG_SIZE); 229 } else { 230 tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) | v_Y_IRE_7_5(0) | 231 v_Y_AGC_PULSE_ON(0) | v_Y_VIDEO_ON(1) | 232 v_YPP_MODE(1) | v_Y_SYNC_ON(1) | v_PIC_MODE(mode)); 233 tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_PAL) | 234 v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3)); 235 236 tve_writel(TV_SATURATION, tve->saturation); 237 tve_writel(TV_BRIGHTNESS_CONTRAST, tve->brightcontrast); 238 239 tve_writel(TV_FREQ_SC, 0x2A098ACB); 240 tve_writel(TV_SYNC_TIMING, 0x00C28381); 241 tve_writel(TV_ADJ_TIMING, (0xc << 28) | 0x06c00800 | 0x80); 242 tve_writel(TV_ACT_ST, 0x001500F6); 243 tve_writel(TV_ACT_TIMING, 0x0694011D | (1 << 12) | (2 << 28)); 244 245 tve_writel(TV_ADJ_TIMING, tve->adjtiming); 246 tve_writel(TV_ACT_TIMING, 0x0694011D | (1 << 12) | (2 << 28)); 247 } 248 } 249 250 if (tve->soc_type == SOC_RK3528) { 251 u32 upsample_mode = 0; 252 u32 mask = 0; 253 u32 val = 0; 254 bool upsample_en; 255 256 upsample_en = tve->upsample_mode ? 1 : 0; 257 if (upsample_en) 258 upsample_mode = tve->upsample_mode - 1; 259 mask = m_TVE_DCLK_POL | m_TVE_DCLK_EN | m_DCLK_UPSAMPLE_2X4X | 260 m_DCLK_UPSAMPLE_EN | m_TVE_MODE | m_TVE_EN; 261 val = v_TVE_DCLK_POL(0) | v_TVE_DCLK_EN(1) | v_DCLK_UPSAMPLE_2X4X(upsample_mode) | 262 v_DCLK_UPSAMPLE_EN(upsample_en) | v_TVE_MODE(tve->tv_format) | v_TVE_EN(1); 263 264 tve_grf_writel(RK3528_VO_GRF_CVBS_CON, (mask << 16) | val); 265 } 266 } 267 268 static void dac_init(struct rockchip_tve *tve) 269 { 270 tve_dac_writel(VDAC_VDAC1, v_CUR_REG(tve->dac1level) | 271 m_DR_PWR_DOWN | m_BG_PWR_DOWN); 272 tve_dac_writel(VDAC_VDAC2, v_CUR_CTR(tve->daclevel)); 273 tve_dac_writel(VDAC_VDAC3, v_CAB_EN(0)); 274 } 275 276 static void dac_enable(struct rockchip_tve *tve, bool enable) 277 { 278 u32 mask = 0; 279 u32 val = 0; 280 u32 grfreg = 0; 281 u32 offset = 0; 282 283 if (enable) { 284 TVEDBG("tve enable\n"); 285 286 if (tve->soc_type == SOC_RK3036) { 287 mask = m_VBG_EN | m_DAC_EN | m_DAC_GAIN; 288 val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve->daclevel); 289 grfreg = RK3036_GRF_SOC_CON3; 290 } else if (tve->soc_type == SOC_RK312X) { 291 mask = m_VBG_EN | m_DAC_EN | m_DAC_GAIN; 292 val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve->daclevel); 293 grfreg = RK312X_GRF_TVE_CON; 294 } else if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) { 295 val = v_CUR_REG(tve->dac1level) | v_DR_PWR_DOWN(0) | v_BG_PWR_DOWN(0); 296 } else if (tve->soc_type == SOC_RK3528) { 297 /* 298 * Reset the vdac 299 */ 300 tve_dac_writel(VDAC_CLK_RST, v_ANALOG_RST(0) | v_DIGITAL_RST(0)); 301 mdelay(20); 302 tve_dac_writel(VDAC_CLK_RST, v_ANALOG_RST(1) | v_DIGITAL_RST(1)); 303 304 tve_dac_writel(VDAC_CURRENT_CTRL, v_OUT_CURRENT(0xd2)); 305 306 val = v_REF_VOLTAGE(7) | v_DAC_PWN(1) | v_BIAS_PWN(1); 307 offset = VDAC_PWM_REF_CTRL; 308 } 309 } else { 310 TVEDBG("tve disable\n"); 311 312 if (tve->soc_type == SOC_RK312X) { 313 mask = m_VBG_EN | m_DAC_EN; 314 grfreg = RK312X_GRF_TVE_CON; 315 } else if (tve->soc_type == SOC_RK3036) { 316 mask = m_VBG_EN | m_DAC_EN; 317 grfreg = RK3036_GRF_SOC_CON3; 318 } else if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) { 319 val = v_CUR_REG(tve->dac1level) | m_DR_PWR_DOWN | m_BG_PWR_DOWN; 320 offset = VDAC_VDAC1; 321 } else if (tve->soc_type == SOC_RK3528) { 322 val = v_DAC_PWN(0) | v_BIAS_PWN(0); 323 offset = VDAC_PWM_REF_CTRL; 324 } 325 } 326 327 if (grfreg) 328 tve_grf_writel(grfreg, (mask << 16) | val); 329 else if (tve->vdac_base) 330 tve_dac_writel(offset, val); 331 } 332 333 static u8 rk_get_vdac_value(void) 334 { 335 u8 value = 0; 336 #ifdef CONFIG_ROCKCHIP_EFUSE 337 #if defined(CONFIG_ROCKCHIP_RK322X) 338 struct udevice *dev; 339 u32 regs[2] = {0}; 340 u8 fuses[1]; 341 ofnode node; 342 int ret; 343 344 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(rockchip_efuse), &dev); 345 if (ret) { 346 printf("%s: no misc-device found\n", __func__); 347 return -EINVAL; 348 } 349 350 node = dev_read_subnode(dev, "tve_dac"); 351 if (!ofnode_valid(node)) 352 return -EINVAL; 353 354 ret = ofnode_read_u32_array(node, "reg", regs, 2); 355 if (ret) { 356 printf("Cannot get efuse reg\n"); 357 return -EINVAL; 358 } 359 360 ret = misc_read(dev, regs[0], &fuses, regs[1]); 361 if (ret) { 362 printf("%s: misc_read failed\n", __func__); 363 return 0; 364 } 365 366 value = fuses[0]; 367 value = (value >> 3) & 0x1f; 368 #endif 369 #endif /* CONFIG_RK_EFUSE */ 370 if (value > 0) 371 value += 5; 372 TVEDBG("%s value = 0x%x\n", __func__, value); 373 374 return value; 375 } 376 377 static int tve_parse_dt(struct rockchip_tve *tve) 378 { 379 tve->preferred_mode = dev_read_u32_default(tve->dev, "rockchip,tvemode", -1); 380 if (tve->preferred_mode < 0) { 381 tve->preferred_mode = 0; 382 } else if (tve->preferred_mode > 1) { 383 printf("tve mode value invalid\n"); 384 return -EINVAL; 385 } 386 387 tve->lumafilter0 = dev_read_u32_default(tve->dev, "rockchip,lumafilter0", 0); 388 if (tve->lumafilter0 == 0) { 389 printf("tve get lumafilter0 err\n"); 390 return -EINVAL; 391 } 392 393 tve->lumafilter1 = dev_read_u32_default(tve->dev, "rockchip,lumafilter1", 0); 394 if (tve->lumafilter1 == 0) { 395 printf("tve get lumafilter1 err\n"); 396 return -EINVAL; 397 } 398 399 tve->lumafilter2 = dev_read_u32_default(tve->dev, "rockchip,lumafilter2", 0); 400 if (tve->lumafilter2 == 0) { 401 printf("tve get lumafilter2 err\n"); 402 return -EINVAL; 403 } 404 405 tve->lumafilter3 = dev_read_u32_default(tve->dev, "rockchip,lumafilter3", 0); 406 if (tve->lumafilter3 == 0) { 407 printf("tve get lumafilter3 err\n"); 408 return -EINVAL; 409 } 410 411 tve->lumafilter4 = dev_read_u32_default(tve->dev, "rockchip,lumafilter4", 0); 412 if (tve->lumafilter4 == 0) { 413 printf("tve get lumafilter4 err\n"); 414 return -EINVAL; 415 } 416 417 tve->lumafilter5 = dev_read_u32_default(tve->dev, "rockchip,lumafilter5", 0); 418 if (tve->lumafilter5 == 0) { 419 printf("tve get lumafilter5 err\n"); 420 return -EINVAL; 421 } 422 423 tve->lumafilter6 = dev_read_u32_default(tve->dev, "rockchip,lumafilter6", 0); 424 if (tve->lumafilter6 == 0) { 425 printf("tve get lumafilter6 err\n"); 426 return -EINVAL; 427 } 428 429 tve->lumafilter7 = dev_read_u32_default(tve->dev, "rockchip,lumafilter7", 0); 430 if (tve->lumafilter7 == 0) { 431 printf("tve get lumafilter7 err\n"); 432 return -EINVAL; 433 } 434 435 tve->upsample_mode = dev_read_u32_default(tve->dev, "rockchip,tve-upsample", -1); 436 if (tve->upsample_mode < 0 || tve->upsample_mode > DCLK_UPSAMPLEx4) { 437 printf("tve get upsample_mode err\n"); 438 return -EINVAL; 439 } 440 441 TVEDBG("tve->preferred_mode = 0x%x\n", tve->preferred_mode); 442 TVEDBG("tve->lumafilter0 = 0x%x\n", tve->lumafilter0); 443 TVEDBG("tve->lumafilter1 = 0x%x\n", tve->lumafilter1); 444 TVEDBG("tve->lumafilter2 = 0x%x\n", tve->lumafilter2); 445 TVEDBG("tve->lumafilter3 = 0x%x\n", tve->lumafilter3); 446 TVEDBG("tve->lumafilter4 = 0x%x\n", tve->lumafilter4); 447 TVEDBG("tve->lumafilter5 = 0x%x\n", tve->lumafilter5); 448 TVEDBG("tve->lumafilter6 = 0x%x\n", tve->lumafilter6); 449 TVEDBG("tve->lumafilter7 = 0x%x\n", tve->lumafilter7); 450 TVEDBG("tve->upsample_mode = 0x%x\n", tve->upsample_mode); 451 452 return 0; 453 } 454 455 static int tve_parse_dt_legacy(struct rockchip_tve *tve) 456 { 457 int dac_value, getvdac; 458 459 if (tve->soc_type == SOC_RK312X) 460 tve->test_mode = dev_read_u32_default(tve->dev, "test_mode", 0); 461 462 tve->preferred_mode = dev_read_u32_default(tve->dev, "rockchip,tvemode", -1); 463 if (tve->preferred_mode < 0) { 464 tve->preferred_mode = 0; 465 } else if (tve->preferred_mode > 1) { 466 printf("tve mode value invalid\n"); 467 return -EINVAL; 468 } 469 470 tve->saturation = dev_read_u32_default(tve->dev, "rockchip,saturation", 0); 471 if (tve->saturation == 0) { 472 printf("tve get saturation err\n"); 473 return -EINVAL; 474 } 475 476 tve->brightcontrast = dev_read_u32_default(tve->dev, "rockchip,brightcontrast", 0); 477 if (tve->brightcontrast == 0) { 478 printf("tve get brightcontrast err\n"); 479 return -EINVAL; 480 } 481 482 tve->adjtiming = dev_read_u32_default(tve->dev, "rockchip,adjtiming", 0); 483 if (tve->adjtiming == 0) { 484 printf("tve get adjtiming err\n"); 485 return -EINVAL; 486 } 487 488 tve->lumafilter0 = dev_read_u32_default(tve->dev, "rockchip,lumafilter0", 0); 489 if (tve->lumafilter0 == 0) { 490 printf("tve get lumafilter0 err\n"); 491 return -EINVAL; 492 } 493 494 tve->lumafilter1 = dev_read_u32_default(tve->dev, "rockchip,lumafilter1", 0); 495 if (tve->lumafilter1 == 0) { 496 printf("tve get lumafilter1 err\n"); 497 return -EINVAL; 498 } 499 500 tve->lumafilter2 = dev_read_u32_default(tve->dev, "rockchip,lumafilter2", 0); 501 if (tve->lumafilter2 == 0) { 502 printf("tve get lumafilter2 err\n"); 503 return -EINVAL; 504 } 505 506 dac_value = dev_read_u32_default(tve->dev, "rockchip,daclevel", 0); 507 if (dac_value == 0) { 508 printf("tve get dac_value err\n"); 509 return -EINVAL; 510 } 511 512 tve->daclevel = dac_value; 513 if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) { 514 getvdac = rk_get_vdac_value(); 515 if (getvdac > 0) { 516 tve->daclevel = dac_value + getvdac - RK322X_VDAC_STANDARD; 517 if (tve->daclevel > 0x3f || tve->daclevel < 0) { 518 printf("rk322x daclevel error!\n"); 519 tve->daclevel = dac_value; 520 } 521 } else if (getvdac < 0) { 522 printf("get rk322x daclevel error\n"); 523 return -EINVAL; 524 } 525 } 526 527 if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) { 528 tve->dac1level = dev_read_u32_default(tve->dev, "rockchip,dac1level", 0); 529 if (tve->dac1level == 0) { 530 printf("rk322x dac1level error!\n"); 531 return -EINVAL; 532 } 533 } 534 535 TVEDBG("tve->test_mode = 0x%x\n", tve->test_mode); 536 TVEDBG("tve->saturation = 0x%x\n", tve->saturation); 537 TVEDBG("tve->brightcontrast = 0x%x\n", tve->brightcontrast); 538 TVEDBG("tve->adjtiming = 0x%x\n", tve->adjtiming); 539 TVEDBG("tve->lumafilter0 = 0x%x\n", tve->lumafilter0); 540 TVEDBG("tve->lumafilter1 = 0x%x\n", tve->lumafilter1); 541 TVEDBG("tve->lumafilter2 = 0x%x\n", tve->lumafilter2); 542 TVEDBG("tve->daclevel = 0x%x\n", tve->daclevel); 543 544 return 0; 545 } 546 547 static int rockchip_drm_tve_init(struct rockchip_connector *conn, struct display_state *state) 548 { 549 struct rockchip_tve *tve = dev_get_priv(conn->dev); 550 struct connector_state *conn_state = &state->conn_state; 551 fdt_addr_t addr; 552 int ret; 553 554 conn_state->output_mode = ROCKCHIP_OUT_MODE_P888; 555 conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24; 556 if (tve->soc_type == SOC_RK3528) 557 conn_state->output_if |= VOP_OUTPUT_IF_BT656; 558 conn_state->color_space = V4L2_COLORSPACE_SMPTE170M; 559 560 conn_state->disp_info = rockchip_get_disp_info(conn_state->type, 0); 561 562 if (tve->soc_type == SOC_RK3528) 563 ret = tve_parse_dt(tve); 564 else 565 ret = tve_parse_dt_legacy(tve); 566 if (ret) { 567 printf("tve parse dts error\n"); 568 return -EINVAL; 569 } 570 571 addr = dev_read_addr_index(conn->dev, 0); 572 if (addr == FDT_ADDR_T_NONE) { 573 printf("failed to get tve reg_base\n"); 574 return -EINVAL; 575 } 576 tve->reg_base = (void *)addr; 577 578 if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328 || 579 tve->soc_type == SOC_RK3528) { 580 addr = dev_read_addr_index(conn->dev, 1); 581 if (addr == FDT_ADDR_T_NONE) { 582 printf("failed to get tve vdac_base\n"); 583 return -EINVAL; 584 } 585 tve->vdac_base = (void *)addr; 586 } 587 588 tve->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 589 590 if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) 591 dac_init(tve); 592 593 return 0; 594 } 595 596 static int rockchip_drm_tve_enable(struct rockchip_connector *conn, struct display_state *state) 597 { 598 struct rockchip_tve *tve = dev_get_priv(conn->dev); 599 struct connector_state *conn_state = &state->conn_state; 600 struct drm_display_mode *mode = &conn_state->mode; 601 602 #ifdef CONFIG_ROCKCHIP_INNO_HDMI_PHY 603 /* set inno hdmi phy clk. */ 604 if (tve->soc_type != SOC_RK3528) 605 rockchip_phy_set_pll(conn->phy, 27000000); 606 #endif 607 if (mode->vdisplay == 576) 608 tve->tv_format = TVOUT_CVBS_PAL; 609 else 610 tve->tv_format = TVOUT_CVBS_NTSC; 611 612 tve_set_mode(tve); 613 mdelay(1000); 614 dac_enable(tve, true); 615 616 return 0; 617 } 618 619 static void rockchip_drm_tve_deinit(struct rockchip_connector *conn, struct display_state *state) 620 { 621 struct rockchip_tve *tve = dev_get_priv(conn->dev); 622 623 dac_enable(tve, false); 624 } 625 626 static int rockchip_drm_tve_prepare(struct rockchip_connector *conn, struct display_state *state) 627 { 628 return 0; 629 } 630 631 static int rockchip_drm_tve_disable(struct rockchip_connector *conn, struct display_state *state) 632 { 633 struct rockchip_tve *tve = dev_get_priv(conn->dev); 634 635 dac_enable(tve, false); 636 637 return 0; 638 } 639 640 static int rockchip_drm_tve_detect(struct rockchip_connector *conn, struct display_state *state) 641 { 642 return 1; 643 } 644 645 static void tve_select_output(struct rockchip_tve *tve, struct connector_state *conn_state, 646 struct drm_display_mode *mode) 647 { 648 int ret, i, screen_size; 649 struct base_screen_info *screen_info = NULL; 650 struct base2_screen_info *screen_info2 = NULL; 651 struct base_disp_info base_parameter; 652 struct base2_disp_info *base2_parameter = conn_state->disp_info; 653 struct drm_display_mode modes[2]; 654 const struct base_overscan *scan; 655 struct overscan *overscan = &conn_state->overscan; 656 char baseparameter_buf[8 * RK_BLK_SIZE] __aligned(ARCH_DMA_MINALIGN); 657 struct blk_desc *dev_desc; 658 disk_partition_t part_info; 659 int max_scan = 100; 660 int min_scan = 50; 661 int offset = 0; 662 bool found = false; 663 664 for (i = 0; i < 2; i++) { 665 modes[i] = tve_modes[i]; 666 if (i == tve->preferred_mode) 667 modes[i].type |= DRM_MODE_TYPE_PREFERRED; 668 } 669 *mode = modes[tve->preferred_mode]; 670 671 if (!base2_parameter) { 672 dev_desc = rockchip_get_bootdev(); 673 if (!dev_desc) { 674 printf("%s: Could not find device\n", __func__); 675 goto null_basep; 676 } 677 678 ret = part_get_info_by_name(dev_desc, "baseparameter", 679 &part_info); 680 if (ret < 0) { 681 printf("Could not find baseparameter partition\n"); 682 goto null_basep; 683 } 684 685 read_aux: 686 ret = blk_dread(dev_desc, part_info.start + offset, 1, 687 (void *)baseparameter_buf); 688 if (ret < 0) { 689 printf("read baseparameter failed\n"); 690 goto null_basep; 691 } 692 693 memcpy(&base_parameter, baseparameter_buf, 694 sizeof(base_parameter)); 695 scan = &base_parameter.scan; 696 697 screen_size = sizeof(base_parameter.screen_list) / 698 sizeof(base_parameter.screen_list[0]); 699 700 for (i = 0; i < screen_size; i++) { 701 if (base_parameter.screen_list[i].type == 702 DRM_MODE_CONNECTOR_TV) { 703 found = true; 704 screen_info = &base_parameter.screen_list[i]; 705 break; 706 } 707 } 708 709 if (!found && !offset) { 710 printf("cvbs info isn't saved in main block\n"); 711 offset += 16; 712 goto read_aux; 713 } 714 } else { 715 scan = &base2_parameter->overscan_info; 716 screen_size = sizeof(base2_parameter->screen_info) / 717 sizeof(base2_parameter->screen_info[0]); 718 719 for (i = 0; i < screen_size; i++) { 720 if (base2_parameter->screen_info[i].type == 721 DRM_MODE_CONNECTOR_TV) { 722 screen_info2 = 723 &base2_parameter->screen_info[i]; 724 break; 725 } 726 } 727 screen_info = malloc(sizeof(*screen_info)); 728 729 screen_info->type = screen_info2->type; 730 screen_info->mode = screen_info2->resolution; 731 screen_info->format = screen_info2->format; 732 screen_info->depth = screen_info2->depthc; 733 screen_info->feature = screen_info2->feature; 734 } 735 736 if (scan->leftscale < min_scan && scan->leftscale > 0) 737 overscan->left_margin = min_scan; 738 else if (scan->leftscale < max_scan && scan->leftscale > 0) 739 overscan->left_margin = scan->leftscale; 740 741 if (scan->rightscale < min_scan && scan->rightscale > 0) 742 overscan->right_margin = min_scan; 743 else if (scan->rightscale < max_scan && scan->rightscale > 0) 744 overscan->right_margin = scan->rightscale; 745 746 if (scan->topscale < min_scan && scan->topscale > 0) 747 overscan->top_margin = min_scan; 748 else if (scan->topscale < max_scan && scan->topscale > 0) 749 overscan->top_margin = scan->topscale; 750 751 if (scan->bottomscale < min_scan && scan->bottomscale > 0) 752 overscan->bottom_margin = min_scan; 753 else if (scan->bottomscale < max_scan && scan->bottomscale > 0) 754 overscan->bottom_margin = scan->bottomscale; 755 756 null_basep: 757 758 if (screen_info) 759 printf("cvbs base_parameter.mode:%dx%d\n", 760 screen_info->mode.hdisplay, 761 screen_info->mode.vdisplay); 762 763 if (screen_info && 764 (screen_info->mode.hdisplay == 720 && 765 screen_info->mode.vdisplay == 576)) 766 *mode = modes[0]; 767 else if (screen_info && 768 (screen_info->mode.hdisplay == 720 && 769 screen_info->mode.vdisplay == 480)) 770 *mode = modes[1]; 771 } 772 773 static int rockchip_drm_tve_get_timing(struct rockchip_connector *conn, struct display_state *state) 774 { 775 struct rockchip_tve *tve = dev_get_priv(conn->dev); 776 struct connector_state *conn_state = &state->conn_state; 777 struct drm_display_mode *mode = &conn_state->mode; 778 779 tve_select_output(tve, conn_state, mode); 780 781 return 0; 782 } 783 784 const struct rockchip_connector_funcs rockchip_drm_tve_funcs = { 785 .init = rockchip_drm_tve_init, 786 .deinit = rockchip_drm_tve_deinit, 787 .prepare = rockchip_drm_tve_prepare, 788 .enable = rockchip_drm_tve_enable, 789 .disable = rockchip_drm_tve_disable, 790 .get_timing = rockchip_drm_tve_get_timing, 791 .detect = rockchip_drm_tve_detect, 792 }; 793 794 static int rockchip_drm_tve_probe(struct udevice *dev) 795 { 796 struct rockchip_tve *tve = dev_get_priv(dev); 797 const struct rockchip_tve_data *data; 798 799 tve->dev = dev; 800 data = (const struct rockchip_tve_data *)dev_get_driver_data(dev); 801 tve->soc_type = data->soc_type; 802 tve->input_format = data->input_format; 803 804 rockchip_connector_bind(&tve->connector, dev, 0, &rockchip_drm_tve_funcs, NULL, DRM_MODE_CONNECTOR_TV); 805 806 return 0; 807 } 808 809 static const struct rockchip_tve_data rk3036_tve = { 810 .soc_type = SOC_RK3036, 811 .input_format = INPUT_FORMAT_RGB, 812 }; 813 814 static const struct rockchip_tve_data rk312x_tve = { 815 .soc_type = SOC_RK312X, 816 .input_format = INPUT_FORMAT_RGB, 817 }; 818 819 static const struct rockchip_tve_data rk322x_tve = { 820 .soc_type = SOC_RK322X, 821 .input_format = INPUT_FORMAT_YUV, 822 }; 823 824 static const struct rockchip_tve_data rk3328_tve = { 825 .soc_type = SOC_RK3328, 826 .input_format = INPUT_FORMAT_YUV, 827 }; 828 829 static const struct rockchip_tve_data rk3528_tve = { 830 .soc_type = SOC_RK3528, 831 .input_format = INPUT_FORMAT_YUV, 832 }; 833 834 static const struct udevice_id rockchip_drm_tve_ids[] = { 835 { .compatible = "rockchip,rk3036-tve", .data = (ulong)&rk3036_tve }, 836 { .compatible = "rockchip,rk312x-tve", .data = (ulong)&rk312x_tve }, 837 { .compatible = "rockchip,rk322x-tve", .data = (ulong)&rk322x_tve }, 838 { .compatible = "rockchip,rk3328-tve", .data = (ulong)&rk3328_tve }, 839 { .compatible = "rockchip,rk3528-tve", .data = (ulong)&rk3528_tve }, 840 }; 841 842 U_BOOT_DRIVER(rockchip_drm_tve) = { 843 .name = "rockchip_drm_tve", 844 .id = UCLASS_DISPLAY, 845 .of_match = rockchip_drm_tve_ids, 846 .probe = rockchip_drm_tve_probe, 847 .priv_auto_alloc_size = sizeof(struct rockchip_tve), 848 }; 849